Showing papers on "Master clock published in 2007"

Circadian clocks during embryonic and fetal development.

Abstract: Circadian rhythmicity is a fundamental characteristic of organisms, which helps ensure that vital functions occur in an appropriate and precise temporal sequence and in accordance with cyclic environmental changes. Living beings are endowed with a system of biological clocks that measure time on a 24-hr basis, termed the circadian timing system. In mammals, the system is organized as a master clock located in the suprachiasmatic nucleus (SCN) of the hypothalamus, commanding peripheral clocks located in almost every tissue of the body. At the cell level, interlocking transcription/translation feedback loops of the genes Bmal-1, Clock, Per1-2, and Cry1-2, named clock genes, and their protein products results in circadian oscillation of clock genes and of genes involved in almost every cellular function. During gestation, the conceptus follows a complex and dynamic program by which it is simultaneously fit to develop and live in a circadian environment provided by its mother and to prepare for the very different environment that it will experience after birth. It has been known for a number of years that the mother tells the fetus the time of day and season of the year, and that the fetus uses this information to set the phase of fetal and neonatal circadian rhythms. There is evidence that the maternal rhythm of melatonin is one of the time signals to the fetus. In the last few years, the study of the development of the circadian system has turned to the investigation of the oscillatory expression of clock genes and their possible role in development, and to answering questions on the organization of the fetal circadian system. Emerging evidence shows that clock genes are expressed in the oocyte and during early and late development in embryo/fetal organs in the rat and in a fetal primate. The data available raise the intriguing possibility that the fetal SCN and fetal tissues may be peripheral clocks commanded by separate maternal signals. The rapid methodological and conceptual advances on chronobiology may help to unravel how the developing embryo and fetus faces time in this plastic period of life.

Atomic Clocks and Oscillators for Deep-Space Navigation and Radio Science

Abstract: This paper describes new oscillator and atomic clock technologies that, when combined, create a master oscillator for use in deep-space navigation and science measurements. This atomic clock promises to execute spacecraft navigation using a one-way downlink only method, saving many millions of dollars per year. We will describe the complementary technology developments by the Jet Propulsion Laboratory toward a space-ready mercury atomic-ion clock and by the Applied Physics Laboratory, Johns Hopkins University, in reducing the size, mass, and operating power of its quartz, ultrastable oscillator.

Regulation of Circadian Gene Expression in Liver by Systemic Signals and Hepatocyte Oscillators

Abstract: The mammalian circadian timing system has a hierarchical structure, in that a master pacemaker located in the suprachiasmatic nuclei (SCN) coordinates slave oscillators present in virtually all body cells. In both the SCN and peripheral organs, the rhythm-generating oscillators are self-sustained and cell-autonomous, and it is likely that the molecular makeup of master and slave oscillators is nearly identical. However, due to variations in period length, the phase coherence between peripheral oscillators in intact animals must be established by daily signals emanating directly or indirectly from the SCN master clock. The synchronization of individual cellular clocks in peripheral organs is probably accomplished by immediate-early genes that interpret the cyclic systemic signals and convey this phase information to core clock components. This model predicts that circadian gene expression in peripheral organs can be influenced either by systemic signals emanating from the SCN master clock, local oscillators, or both. We developed a transgenic mouse strain in which hepatocyte clocks are only operative when the tetracycline analog doxycycline is added to the food or drinking water. The genome-wide mapping of genes whose cyclic expression in liver does not depend on functional hepatocyte oscillators unveiled putative signaling pathways that may participate in the phase entrainment of peripheral clocks.

Clock genes beyond the clock: CLOCK genotype biases neural correlates of moral valence decision in depressed patients.

Abstract: Gene polymorphisms in the mammalian biological clock system influence individual rhythms. A single nucleotide polymorphism (SNP) in the 3' flanking region of CLOCK (3111 T/C; rs1801260) influenced diurnal preference in healthy humans and caused sleep phase delay and insomnia in patients affected by bipolar disorder. Genes of the biological clock are expressed in many brain structures other than in the 'master clock' suprachiasmatic nuclei. These areas, such as cingulate cortex, are involved in the control of many human behaviors. Clock genes could then bias 'nonclock' functions such as information processing and decision making. Thirty inpatients affected by a major depressive episode underwent blood oxygen-level dependent (BOLD) functional magnetic resonance imaging (fMRI). The cognitive activation paradigm was based on a go/no-go task. Morally connoted words were presented. Genotyping of CLOCK was performed for each patients. We measured activity levels through actimetry during the day before the fMRI study. CLOCK 3111 T/C SNP was associated with activity levels in the second part of the day, neuropsychological performance and BOLD fMRI correlates (interaction of genotype and moral valence of the stimuli). Our results support the hypothesis that individual clock genotype may influence several variables linked with human behaviors in normal and psychopathological conditions.

Peripheral clocks: keeping up with the master clock.

Abstract: Circadian clocks influence most aspects of physiology and behavior, so perhaps it is not surprising that circadian oscillators exist in nearly all mammalian cells. These cells remain synchronized to the outside world in hierarchical fashion, with a “master clock” tissue in the suprachiasmatic nucleus of the hypothalamus receiving light input from the retina and then conveying timing information to “slave” clocks in peripheral tissues. Recent research has highlighted both the similarities and differences between central and peripheral clocks and provided new insight into their communication. Above all, however, this parallelism of clockwork has provided a unique opportunity to study at the cellular level a regulatory mechanism that affects complex behaviors.

IEEE 1588 applied in the environment of high availability LANs

Abstract: High availability applications typically count on the network's ability to reconfigure in case of a failure. Since the precision time protocol (PTP) measures the delay of communication paths, it has to cope with network topology changes. The concept of peer-to-peer transparent clocks (TC), introduced with PTP version 2, facilitates the handling of path switchover by measuring the link delays from each node to its neighbors in advance. The parallel redundancy protocol (PRP) follows a different approach from the well-known reconfiguration protocols. It makes use of two independent Ethernet networks. Frames are replicated by the sending node and transmitted over both networks. Duplicates are discarded by the receiving node. There is no distinction between a working and a backup path. The combination of PTP and PRP is studied in this paper. Different models are presented and evaluated with respect to synchronization switchover and implementation issues. An experimental implementation is outlined. The results show that master clock failure as well as network failures can be handled with very low impact on synchronization quality.

System and method for synchronizing playback of audio and video

Abstract: A system and method for providing a digital In-Flight Entertainment (IFE) system in a vehicle, such as an aircraft, that is capable of presenting a video program and associated audio in a synchronized manner to a large number of individual video monitors and speakers. The system and method employ processing operations in at least one decoder of the IFE system, to perform operations such as adjusting a local clock based on a master clock, setting a delay time in relation to a master clock, and adjusting video and audio playback based on the delay, to substantially synchronize playback of the audio and video data by the audio and video players, to thus eliminate or at least minimize the negative effects of source and load based jitter, network delays, clock drifts, network errors and decoder buffering differences, on synchronizing video and audio playback.

Method for data converter sample clock distribution

Abstract: A unit for use in a communication system comprises a communication module having an oscillator configured to generate a master clock signal; a plurality of conversion modules; and a distribution component configured to distribute the master clock signal from the communication module to each of the plurality of conversion modules. Each of the plurality of conversion modules comprises a filter configured to filter the master clock signal; and a converter configured to use the filtered master clock signal in converting between analog and digital signals.

Capturing media in synchronized fashion

Abstract: Techniques for synchronizing audio and video content for presentation to a user at a same rate are provided. Streams of content from two or more sources of media, each media source having an associated clock, are synchronized by a synchronizing component and processor with respect to a master clock. As well, techniques are provided for ensuring that output devices are synchronized at preview startup. That is, such techniques ensure that the output devices start playing the media at the same time as well as at the same rate.

Data transfer circuit, solid-state imaging element, and camera system

Abstract: PROBLEM TO BE SOLVED: To provide a data transfer circuit, solid-state imaging element and camera system which can reduce the effect caused by wiring delay on a transfer line to a data output section, enable a data output section to exactly and highly accurately capture data and can achieve an increase in a scanning speed as a result. SOLUTION: In a data transfer circuit, basically, a column scanning circuit 13 supplies a master clock MCK supplied from a clock supply circuit 21, in order from a far-end side latch 131-0 for instance to latches 131-0 to 131-n constituting a shift register 131 via predetermined wiring, and data output circuits 17-0 to 17-n capture output data of sense amplifier circuits 171-0 to 171-n in accordance with a capture clock SACK where the phase of a clock is adjusted based on the master clock MCK. COPYRIGHT: (C)2009,JPO&INPIT

Network and method for clock synchronization of clusters in a time triggered network

Abstract: The invention relates to a network operating on a time triggered protocol using time slots, wherein at least two clusters are included in the network, each cluster includes at least a node. Further, it relates to a method for clock synchronization within a time triggered network. To provide a network and a method reducing the amount of time needed for aligning multiple communication clusters as much as possible it is proposed to provide a network operating on a time triggered protocol using time slots, wherein at least two clusters (A, B, X) are included in the network, each cluster (A, B, X) includes at least a node (11), wherein the node (11) includes a communication controller (15) having a node clock source (18) for determining a timing for the node (11), wherein the clusters (A, B, X) are connected to a coupling unit (10) having a clock alignment control logic (20) comprising a coupling unit clock source (21) which is more accurate than the node clock source (18), wherein the coupling unit clock source (21) is used for aligning the timing between the at least two clusters (A, B, X). Further it is proposed to provide a method for clock synchronization within a time triggered network using time slots, having at least two clusters (A, B, X), wherein each cluster includes at least one node (11), each node (11) comprises a node clock source (18) and a communication controller (15) and the clusters (A, B, X) are connected to a coupling unit (10) having a clock alignment control logic (20) comprising a coupling unit clock source (21) which is more accurate than the node clock source (18), the method comprising the steps of: monitoring the timing of the connected clusters (A, B, X) within the coupling unit (10); increasing or decreasing a cycle length λ of the timing within the clusters by use of the coupling unit clock source (21).

Automatic video format identification system

Abstract: A video format identification system includes a master clock circuit which provides timing and counting signals, a synchronization activity detector operatively coupled to the master clock circuit, and a synchronization width qualifier configured to filter out noise or reference burst signals from showing up as sync signals. The system also includes a synchronization detector which regulates the rate of the incoming sync signal, a color burst sampler providing a window for sampling a reference color burst after the sync signal has occurred, and a color burst detector which looks for at least three transitions from a burst signal before it qualifies the as an appropriate reference color burst. A format sample timer generates sample clock signals. A format sample counter produces “take format” signals which are utilized by a set of format counter. The system further includes a video format identifier which enables a particular video format to be directed to a respective video connector.

An Ultra-low-Power Quadrature PLL in 130nm CMOS for Impulse Radio Receivers

Abstract: This paper discusses an architecture for an integrated ultra-low power impulse radio receiver for low data rate applications such as biomedical sensor networks. Choosing a proper system architecture allows to implement a receiver with relaxed specifications for the typical building blocks which results in a low-power implementation. Furthermore a design in 130 nm CMOS of a fully integrated ultra-low power PLL, a critical block of such receivers, is presented. The PLL serves a double purpose. It acts as the master clock generator for the receiver and it is also used to generate a template waveform for pulse reception. The latter requires the PLL to have quadrature outputs since the receiver uses I/Q reception. Because rather relaxed specifications in terms of phase-noise are required, a differential ring VCO with an even amount of stages is a suitable topology. The VCO has a measured center frequency of 568 MHz and a tuning range of 23%. It achieves a phase-noise of -91 dBc/Hz @ 1 MHz offset. The PLL employs a divide-by-8 and locks to an externally applied 75 MHz clock. Measurements show a total power consumption less than 200 muW with an rms jitter of 24 ps on an output clock of 600 MHz.

Method and system for network clock synchronous

Abstract: This invention discloses a method and a system for synchronizing network clocks, which sets synchronous source nodes with mutual redundance in a wireless sensor network to design them a working clock node and a backup clock source node and selects a regional master clock node in network node to form a synchronous queue, the network node asks for clock synchronization to the nodes in the synchronous queue, the backup clock source node computes the mean queue synchronous clock based on the difference between the local clock and the synchronous clock of the working clock node and sends it to the regional master clock node in the queue so as to realize clock rectification to the regional master clock.

Method and system for i2c clock generation

Abstract: I2C clock generators are implemented using a variety of methods. Using one such method, a method is implemented using logic circuitry arranged in a state machine to control the clock signal (110) on the I2C bus. A first state (202) of the state machine determines whether to effect a clock stretching delay. A second state (206) of the state machine determines whether the I2C bus is configured to run in a standard clock mode or in another one of multiple faster clock modes. A third state (210) of the state machine drives the clock signal in one binary logic state for more than about 0.5 microseconds before allowing the clock signal (110) to be driven in the other binary logic state and allowing the clock signal to remain in the other binary logic state for more than about 0.5 microseconds.

Radio communication system, base station, and synchronization method

Abstract: PROBLEM TO BE SOLVED: To maintain a synchronous clock stably and accurately even when a reference clock that becomes a reference such as a GPS signal becomes impossible. A base station 110 according to the present invention compares a reference clock and a synchronization clock with a clock generator 212 that generates a synchronization clock of the own station, and synchronizes the synchronization clock of the clock generator 212 with the reference clock. The phase difference is derived by comparing the reference clock and the synchronization clock of the other base station, and deriving the phase difference between the clock correction unit 214 and the synchronization clock receiving unit 216 for receiving the synchronization clock of the other base station. Derivation unit 220, phase difference storage unit 222 that stores the phase difference, phase correction unit 224 that corrects the phase of the synchronization clock of another base station by the phase difference, and another base station whose phase difference is corrected from the reference clock And a change-over switch 226 for switching between the two synchronous clocks. [Selection] Figure 3

Apparatus and Method for Redundant and Spread Spectrum Clocking

Abstract: An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a predetermined range of frequencies. A slave clock synthesizer circuit is provided to track the output clock signal generated by the master clock synthesizer circuit. If the master clock synthesizer circuit fails or generates an invalid output clock signal, the slave clock synthesizer circuit takes over and functions as the master clock synthesizer circuit. In one embodiment a method of fault-tolerant spread spectrum clocking includes generating a first digital data stream; receiving the first digital data stream, a first input reference signal and a first clock signal in a master clock synthesizer circuit; generating an first output clock signal of varying frequency by the master clock synthesizer circuit in response to the first digital data stream and the first clock signal.

Method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog-to-digital converter (ADC)

Abstract: A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and digital circuits and other noise-generating circuits such as power converters, are operated by digital circuit clock signals. Both sets of clock signals are derived from the same master clock by a clock generator circuit, but an offset is applied in the clock generator circuit to move the edges of the digital circuit clock signals away from critical sampling intervals corresponding to edges of the sampling clocks. In one embodiment, the offset is applied by a processor core that forms part of the digital circuits by setting a value in the clock generator, which the clock generator then loads into the divider after halting the clock to the digital circuits.

Skew-Tolerant Global Synchronization Based on Periodically All-in-Phase Clocking for Multi-Core SOC Platforms

Abstract: A periodically all-in-phase clock generator and a skew-tolerant bus wrapper have been developed for multi-core SOC platforms. The clock generator produces clock frequencies in 81-steps, and the bus wrapper makes possible deterministic data transfer among different frequency clocks even when inter-clock skew is as high as 2 clock cycle times. A combination of the clock generator, the bus wrapper, and loosely balanced global clock distribution serves to ease chip-timing design while maintaining deterministic chip behavior.

Clock switch for generation of multi-frequency clock signal

Abstract: An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases.

Apparatus and method for selectively implementing launch off scan capability in at speed testing

Abstract: An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.

Verification and Optimization of the Physics Parameters of the Onboard Galileo Passive Hydrogen Maser

Abstract: : Atomic clocks represent critical equipment for a satellite navigation system. A Passive Hydrogen Maser (PHM), with its excellent frequency stability performance, has been chosen as the master clock in the Galileo navigation satellite payload, and will be the first one of its type ever to fly. Temex Neuchatel Time is responsible for the industrialization of the Physics Package (PP) of the PHM and has been developing numbers for the PP, including Engineering Qualification, Qualification, Proto-Flight, and Flight Models in the frame of the Galileo Satellite Test Bed (GSTB-V2) and the In-Orbit Validation (IOV) phase. This paper provides the verification results of PHM physics parameters, according to the measurement data and the theoretical analysis, for all the PPs produced up to now. A theoretical PHM physics model has been developed to extract inherent physics parameters (such as oscillation parameter, saturation factor, natural line width, various relaxation rates, and useful atomic flux) which cannot be measured directly, but are of great importance in order to evaluate the instrument performance.

Method and apparatus for synchronous clock distribution to a plurality of destinations

Abstract: Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may provide synchronized clock distribution for a first destination while the dependent synchronization circuit may provide synchronized clock distribution to a second destination. A method for synchronized clock distribution to a plurality of destinations is also described.

Data transmitting-receiving system

Abstract: PROBLEM TO BE SOLVED: To provide a data transmitting-receiving system which can secure the sound quality, not only on the receiving side but also on the transmitting side, and can also eliminate lackage of lip-sync problem. SOLUTION: Video data, audio data, additive data, and a video clock are transmitted from the transmitting side to the receiving side; while additive data and a video clock are transmitted from the receiving side to the transmitting side, and the clock rate of the video data and/or audio data is adjusted by using the video clock or its additive data which are generated on the receiving side and are transmitted to the transmitting side. Because making this structure such, the clock on the transmitting side is made continuously synchronized with the clock on the receiving side as a master clock, which makes high-quality AV reproduction available on both the transmitting and the receiving sides; and at the same time, shift in lip-synch problem can be solved also. COPYRIGHT: (C)2008,JPO&INPIT

Atomic Clocks and Oscillators for Deep-Space Navigation and Radio Science Onboard atomic clocks are being developed to allow spacecraft navigation via one-way downlink communications; this can substantially reduce the cost of Earth antenna stations.

Abstract: This paper describes new oscillator and atomic clock technologies that, when combined, create a master oscillator for use in deep-space navigation and science measurements. This atomic clock promises to execute space- craft navigation using a one-way downlink only method, saving many millions of dollars per year. We will describe the complementary technology developments by the Jet Propul- sion Laboratory toward a space-ready mercury atomic-ion clock and by the Applied Physics Laboratory, Johns Hopkins University, in reducing the size, mass, and operating power of its quartz, ultrastable oscillator.

Device and method for supplying master clock to stream processing apparatus for processing stream data frame by frame in synchronization with master clock

Abstract: The clock supply device, which supplies a master clock to a stream processing apparatus that processes stream data frame by frame in synchronization with the master clock, includes a clock supply section, a processing amount computation section and a clock control section. The clock supply section supplies a clock having a predetermined frequency to the stream processing apparatus as the master clock. The processing amount computation section computes, at predetermined processing timing in a series of data processing performed for each frame by the stream processing apparatus, a data processing amount accumulated until the processing timing for each frame. The clock control section outputs a control signal according to a comparison result between the computed data processing amount and a predetermined threshold. The clock supply section switches the frequency of the clock supplied to the stream processing apparatus in response to the control signal.

Data transmission/reception system, data transmitting apparatus, data receiving apparatus, and clock generating method

Abstract: PROBLEM TO BE SOLVED: To perform much higher-definition audio playback in an HDMI-connected AV system environment SOLUTION: A crystal-precision master clock CLK_M is generated at a synk side, and CTSr is generated and transmitted to a source side by the master clock CLK_M, a TMDS clock received from the source side and a frequency dividing ratio value N At the source side, an audio clock CLK_Arg is obtained by the received CTSr, TMDS clock and frequency dividing ratio value N The audio clock CLK_Arg is obtained by re-generating the master clock CLK_M A disk playback device that is a sink-side device is adapted to obtain a digital audio signal by executing disk playback processing in accordance with the audio clock CLK_Arg COPYRIGHT: (C)2009,JPO&INPIT

Timing Recovery for Backplane Ethernet

Abstract: The dominant solutions for single-chip multi-port backplane Ethernet transceivers utilize a dual-loop design - a combination of a single master phase-locked loop (PLL) and multiple slave delay-locked loops (DLL). Each transmitter or receiver port has its own DLL, which delays or advances a copy of the master clock from the master PLL to generate its own clock signal for synchronization. The DLLs are typically implemented using current-mode logic phase interpolators. This paper presents an alternative solution to this synchronization problem. Instead of moving the sampling phase, timing recovery is done by changing the group delay of the receiver-side forward equalizer by rotating its tap coefficients. The standard least-mean-square algorithm is used for coefficient rotation. This solution is equivalent to a first-order PLL/DLL, which suffers from steady-state timing offset when there is a frequency offset between the transmitter and the receiver. However, the degradation in performance caused by a frequency offset is significantly reduced by using a coefficient-rotation digital-signal processor capable of detecting and reducing the offset. With a practical frequency accuracy specification of plusmn100 ppm, the improved performance can approach that of the PLL/DLL dual-loop solution.

New Real Time UTC(CH) Generation Scheme at METAS: Recent Progress in Control and Calibration Methods

Abstract: In the course of the year 2007, UTC(CH) will change from a computed time scale definition to one based on a realtime master clock. In preparation for this important change, the time scale generation hardware was upgraded and new control software is being developed. This paper discusses recent progress in the development of control and calibration methods used in the new time scale generation system and reports experimental results obtained during validation testing.