Showing papers on "Master clock published in 2008"

An Enhanced IEEE 1588 Time Synchronization Algorithm for Asymmetric Communication Link using Block Burst Transmission

Abstract: IEEE 1588 is a standard to synchronize independent clocks running on separate nodes of a distributed measurement and control system. In IP based cellular network, it is considered as a key technology to synchronize base stations. Especially, interests for the low-cost and very-small home cellular base station called the Femtocell is increasing, and it is connected to the cellular core network using an asymmetric communication link such as xDSL. However, the conventional IEEE 1588 synchronization algorithm assumes symmetrical links, and makes errors for asymmetric links for the calculation of the time difference between the master clock (a clock source) and the slave clock (a clock consumer). We propose an enhanced synchronization algorithm to calculate the asymmetric ratio of the communication link, and the proposed algorithm enhances an accuracy of the time synchronization.

Step time change compensation in an industrial automation network

Abstract: One or more embodiments provide Common Industrial Protocol (CIP) based time synchronization systems and methods. The CIP Sync solution can be part of Ethernet/IP and can be based on standard UDP (User Datagram Protocol) and/or IEEE 1588 (Time Synchronization) Ethernet technology. According to an embodiment is a system that compensates for step changes in a master clock.

The nuclear hormone receptor family round the clock.

Abstract: Daily rhythms in behavior and physiology are observed in most organisms. These rhythms are controlled by internal self-sustained circadian ( approximately 24 h) clocks, which are present in virtually all cells. The 24-h oscillations are generated by a molecular mechanism entrained by external or internal time cues and which, in turn, regulate rhythmic outputs. In mammals, the circadian system comprises a master clock located in the hypothalamus that is directly entrained by the light-dark cycle and which coordinates the phases of local clocks in the periphery in order to ensure optimal timing of the physiology. Nuclear receptors (NRs) form a large family of transcription factors that include both ligand-inducible and orphan receptors. These NRs are key regulators of major biological processes such as reproduction, development, cell growth and death, inflammation, immunity, and metabolic homeostasis. Recent observations indicate that several NR signaling pathways play a critical role in central and peripheral circadian clocks. The REV-ERB/retinoid-related orphan receptor orphan NR subfamily regulates the expression of core clock genes and contributes to the robustness of the clock mechanism. Glucocorticoid and retinoic acid receptors are involved in the resetting of peripheral clocks. Several other NRs such as peroxisome proliferator-activated receptor-alpha, short heterodimer partner, and constitutive androstane receptor act as molecular links between clock genes and specific rhythmic metabolic outputs. The expanding functional links between NRs and circadian clocks open novel perspectives for understanding the hormonal regulation of the mammalian circadian system as well as for exploring the role of circadian clocks in the pathogenesis of NR-related diseases such as cancer and metabolic syndrome.

Systems and methods for distributing GPS clock to communications devices

Abstract: A method for synchronizing network elements to a global clock derived from the GPS clock acquired by a plurality of base stations. The global clock is distributed to controllers of various networks, and from there to network access devices. The network access devices further distribute the global clock to various wire-line and local wireless networks and from there, to the users served by these networks. The user equipment is enabled with a simple clock discipliner that adjusts the local clock to the global clock, resulting in a reliable synchronization across the converged communication networks.

Method, Apparatus and System for Frequency Synchronization Between Devices Communicating over a Packet Network

Abstract: An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop utilizes a frequency error estimator implemented as a maximum-likelihood estimator with slope fitting based on a sequence of arrival timestamps, and a loop filter implemented as a series combination of an adaptive-bandwidth filter and a proportional-integral controller. The clock recovery module may further comprise a discontinuity detector configured to detect a discontinuity in delays of respective timing messages, and a loop controller operative to place the clock recovery loop in a particular state responsive to detection of the discontinuity.

Automatic synthesis of clock distribution networks

Abstract: In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.

Keeping accurate time for a hybrid GPS receiver and mobile phone when powered off

Abstract: A hybrid navigation satellite receiver and mobile telephone uses only two crystal oscillators. One that operates a master clock around 27-MHz and that consumes milliwatts of power. The other oscillator consumes only microwatts of power and operates continuously on battery power at about 32-KHz. Only the second, low frequency oscillator is kept running during power “off”. On power “restart”, a real-time-clock counter is consulted to cause an estimate of the GPS system time to be regenerated and supplied to the GPS-DSP to quicken its initialization. The master clock is GPS-calibrated, and the accurate clock is used to drive NCO's for the mobile telephone part and host CPU.

Internal clock drift estimation in computer clusters

Abstract: Most computers have several high-resolution timing sources, from the programmable interrupt timer to the cycle counter. Yet, even at a precision of one cycle in ten millions, clocks may drift significantly in a single second at a clock frequency of several GHz. When tracing the low-level system events in computer clusters, such as packet sending or reception, each computer system records its own events using an internal clock. In order to properly understand the global system behavior and performance, as reported by the events recorded on each computer, it is important to estimate precisely the clock differences and drift between the different computers in the system. This article studies the clock precision and stability of several computer systems, with different architectures. It also studies the typical network delay characteristics, since time synchronization algorithms rely on the exchange of network packets and are dependent on the symmetry of the delays. A very precise clock, based on the atomic time provided by the GPS satellite network, was used as a reference to measure clock drifts and network delays. The results obtained are of immediate use to all applications which depend on computer clocks or network time synchronization accuracy.

Method and apparatus for master-salve clock synchronization

Abstract: The invention discloses a method and a device for synchronizing a master clock and a slave clock, the method comprises: sending synchronous request message to the master clock for many times in a simultaneous cycle by the slave clock, recording the corresponding time value, utilizing a median average filtering algorithm to obtain the optimum time migration amount, utilizing the time migration amount to regulate the slave clock, eliminating delay inequality which is caused by stochastic disturbance and burst interference of a network communication channel between the master clock and the slave clock, guaranteeing the stability of slave clock signals, and increasing the synchronous preciseness of the master clock and the slave clock.

System and method for time synchronization on network

Abstract: A system and method for time synchronization on a network is provided. According to the system and method for time synchronization, a slave clock device does not continuously receive a time synchronization message periodically transferred from a master clock device and thus does not correct its time upon all such occasions. Rather, the slave clock device requests time information from the master clock device only when the slave clock device needs to correct its time, and receives a time synchronization message transferred from the master clock device and compensates for its time deviation only while the slave clock device is activated, thereby reducing its power consumption and amount of computation.

Method and system for synchronizing clock of transmission network as well as subordinate clock side entity

Abstract: The invention discloses a clock synchronization method in a transmission network. The method comprises the steps of obtaining the arrival time t2 and the sending time t1 of first message through the interaction of a slave clock and a master clock; adopting external clock source to detect the time delay of the master clock and the salve clock; seeking clock error Offset according to the time delay between the master clock and the slave clock, t1 and t2; and adjusting the clock of the slave clock according to Offset. The invention further discloses a clock synchronization method in other two transmission networks, and also discloses a clock synchronization system of three transmission networks. The clock synchronization method of the invention can accurately calculate clock error Offset, thereby ensuring the synchronization of the slave clock and the master clock.

Timing distribution within a network element while supporting multiple timing domains

Abstract: According to one embodiment of the invention, a network element synchronizes a number of clocks within the system while supporting multiple independent timing domains. The network element includes a local clock, which is free-running and is not necessarily synchronized with an external reference, that synchronously provides a local time value to the slave and master interfaces of each timing domain. Each slave interface of each timing domain independently determines timing information based on a received master clock synchronization event and the value of the local time when that synchronization event was received. The timing information is distributed to the master interfaces of the appropriate timing domain, and each master interface calculates an adjusted synchronization event based on the received timing information and the value of the local time when that timing information was received. The adjusted synchronization events are transmitted out of the network element to an external slave interface.

Multi-radio wireless communication device method for synchronizing wireless network and bluetooth communications

Abstract: Embodiments of a multi-radio wireless communication device and methods for synchronizing wireless network and Bluetooth (BT) communications are generally described herein. Other embodiments may be described and claimed. In some embodiments, a BT radio module adjusts a master clock signal by a predetermined step size before each subsequent BT transmission in response to a frame sync pulse from a wireless network radio module to reduce a time difference between subsequent frame sync pulses and synchronization reference points of BT slots.

Simple Time and Frequency Dissemination Method Using Optical Fiber Network

Abstract: This paper describes a simple and cost-effective method of frequency dissemination. In current digital communication networks, node clocks are hierarchically synchronized to the atomic master clock through fiber links. This synchronized network is used as an intermediate link for remote calibration services like the global positioning system common-view method. A prototype reference signal generator has been developed for recovering the communication clock signal and synthesizing a 10-MHz signal from it. The generator output frequency at the client site can be traced to coordinated universal time (UTC) National Metrology Institute of Japan (NMIJ) with some uncertainty, depending on the stability of the node clocks and the distance from the master clock. The stability performance of the generated reference signal has been tested at Okinawa-the farthest prefecture from Tokyo, where the master clock is located (baseline distance of 1500 km). The primary rate (1.544 MHz) for telecommunication services was chosen for the 10-MHz signal generation in the experiment. A sinusoidal phase fluctuation within a one-day period is dominantly observed. This fluctuation is mainly caused by fiber expansion and contraction due to normal daily temperature changes. It degrades the stability (Allan deviation) to the level of 5 X 10-13 (t = 40 000 s, which is almost half a day). However, the major part of the phase fluctuation can be canceled by averaging a full day's data. In this case, the Allan deviation becomes 1 X 10-13, which is obtained at Okinawa over ten consecutive days of measurement. The worst average frequency offset relative to UTC (NMIJ) (one-day averaging) is -6.3 X 10-13. The results indicate that this method promises to be suitable for most applications, providing an uncertainty of less than 1 X 10-12 at an averaging time of one day.

Frequency Synchronization Using First and Second Frequency Error Estimators

Abstract: An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop comprises a primary loop having a first frequency error estimator for generating a first estimate of error between the master and slave clock frequencies, a second frequency error estimator outside of the primary loop for generating a second estimate of error between the master and slave clock frequencies, and an accumulator coupled between the second frequency error estimator and the primary loop. The second estimate is controllably injected into the primary loop via the accumulator.

Method and device for packet based clock recovery

Abstract: A master clock in a first radio network unit, configured for sending data packets at predetermined time intervals, is synchronized with a slave clock in a second radio network unit. To provide a method for packet based clock recovery being able to achieve the desired accuracy within an acceptable time while avoiding a high computational complexity, the following procedure is used. An estimate value is determined for the transmission delay time for each data packet in a predetermined set of data packets. At least one pair of data packets is selected that has a minimum estimate value for the transmission delay time. A difference of the reception times of the selected pair of data packets is determined. Finally, a clock estimate procedure is performed using the difference of the reception times of the selected pair of data packets to determine the quantity representative of the clock frequency difference and/or the clock time offset.

High-precision real-time synchronization method based on IEEE1588

Abstract: The invention relates to a real-time synchronization method based on PTP precision clock synchronization protocol of IEEE1588. The research on hardware of IEEE1588 protocol is still a blank at present. The method of the invention includes the following steps: sending messages; receiving messages; correcting the local system time; selecting the optimal master clock. And the synchronization action is different when the corresponding equipment is a master clock or a slave clock. The hardware method of the invention reduces the inherent fluctuation of data transmission time of internet technology, while not affecting the scope of precision control, thus resolving the problem of the clock uniformity and precision in a distributed network system.

Sleep apnoea: time to consider clock genes

Abstract: Most, and perhaps all, cells harbour a circadian clock. These clocks regulate hundreds of physiological processes, ranging from body temperature and sleep–wake cycle to serum cortisol and melatonin concentration. All clocks operate using a very similar molecular mechanism; they communicate with each other through a complex and still poorly understood neuroendocrine network 1. In the mammalian brain, for example, a key clock gene known as Bmal is turned on and off in a 24-h rhythm, not only in the suprachiasmatic nucleus of the hypothalamus (the seat of the master clock) but also in the hippocampus and neocortex 1. It is therefore expected that many processes occurring in the neocortex are subject to clock control. The question, then, is how such control is achieved and which neuoendocrine regulators play a role. The study by Burioka et al. 2 presented in the current issue of the European Respiratory Journal ( ERJ ) contributes significantly towards addressing this question. The circadian rhythm of vigilance, blood pressure, sympathetic activity, corticoid biogenesis and metabolism is severely altered in patients with obstructive sleep apnoea (OSA). Given the previously sketched importance of clock genes in the genesis of circadian rhythm, investigation of circadian gene activation in OSA patients seems to hold promise. Burioka et al. 2 have quantified the expression of the clock gene Per1 mRNA in peripheral blood cells using real-time PCR analysis at different points over 24 h. In contrast to the matched …

Estimating a time offset between stationary clocks

Abstract: The present invention is concerned with an improved time synchronisation of two stationary clocks. A global time signal from a global time reference or common time source is used to calculate a common view based clock offset between two stationary clocks. In parallel, a network based clock offset between the two clocks is calculated based on messages exchanged over a communication network interconnecting the two clocks and without reverting to the global time reference. The two most recent values of the common view and network based clock offsets are then combined or superposed in a seamless or hitless way to produce a final time offset estimate. The combination of the independently calculated common view and network based clock offsets is a weighted average of the two values, involving respective weights based on quality estimates of the latter. Preferably, the time synchronization schemes based on the Global Positioning System (GPS) and a wide area communication network are combined in order to synchronize the stationary clocks of the Phasor Measurement Units (PMUs) of a Wide Area Monitoring System to a central server clock at the Network Control Center (NCC) of the system.

High-Precision Relative Clock Synchronization Using Time Stamp Counters

Abstract: In this paper we show how to use a computer processor's time stamp counter register to provide a precise and stable time reference, via a high-precision relative clock synchronization protocol. Existing clock synchronization techniques, such as the network time protocol, were designed for wide-area networks with large propagation delays, but the millisecond-scale precision they offer is too coarse for local-area applications such as instrument monitoring systems, high-quality digital audio systems and sensor networks. Our new clock synchronization technique does not require specialized hardware but instead uses the Time stamp counter already available in the widely-used Intel Pentium processor. Experimental results show that we can achieve a synchronization precision in the order of 10 microseconds in a small-scale local area network using TSC registers, which is much higher than can be achieved by using a computer processor's time-of-day clock.

Continuous synchronization for multiple adcs

Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

Method and apparatus for main clock selecting

Abstract: The invention relates to a master clock selecting method and the device thereof. Each node has the own clock and keeps a second optimal clock. The method comprises the following steps: when each node determines that the own master clock fails, the node takes the own second optimal clock as the own current optimal clock. Each node determines the master clock according the current own optimal clock. By the invention, when the next selection of the master clock begins, the selection is carried out based on the second optimal clock learned by the node, instead of starting from the beginning, thereby reducing the transmission of broadcast messages and shortening the time used for master clock selection.

Memory controller with flexible data alignment to clock

Abstract: A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.

Frequency synchronization with compensation of phase error accumulation responsive to a detected discontinuity

Abstract: An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery module further comprises a discontinuity detector configured to detect a delay discontinuity in timing messages received in the slave device from the master device, and a loop controller operative to place the clock recovery loop in a particular state responsive to the detected discontinuity. The particular state comprises a state in which a normal operating mode of the loop is interrupted and a compensating drive signal is applied to a clock source of the slave device to at least partially offset phase error accumulation associated with the detected discontinuity.

Method and apparatus for wireless clock regeneration

Abstract: Methods and systems for operating a wireless clock system for multimedia datastream transmission and display Source clock frames are compared with a reference clock frames and the clock difference are transmitted to a wireless clock receiver which also receives the same reference clock frames Source clock frames are re-constructed using the reference clock frames, clock difference information and the receiver's local clock system

Clock synchronization system, its method and program

Abstract: It is possible to stably measure a clock synchronization accuracy between a master node and a slave node. A slave node receives a packet transmitted from a master node. By using the packet, the slave node synchronizes its clock with the clock of the master node. By using the packet, the slave node reproduces the clock of the slave node, accumulates information on the packet and the clock of the slave node obtained by the reproduction, and performs clock synchronization according to the accumulated information.

Multiphase clock for superconducting electronics

Abstract: A multiphase clock circuit in which bit errors are propagated only for the duration of the clock cycle in which a bit error occurs. The circuit recovers automatically from bit errors and is capable of operating at high frequency with high clock precision. The multiphase clock circuit can generate a plurality of clock pulse streams, each pulse stream at the same clock frequency, with fixed phase relationships among the streams. The multiphase clock circuit includes a master clock signal of frequency fc which is applied to a divide by N frequency divider circuit for producing a base clock signal of fc/N. The base clock signal is sequentially applied to the data input of a series chain of N clocked data flip-flops (DFFs) each of which is simultaneously clocked by a clock signal of frequency fc to produce N clock signals of base frequency fc/N separated from each other by a constant time delay T=1/fc.

Network element clocking accuracy and stability monitoring over a packet-switched network

Abstract: Various exemplary embodiments include a method and related system and monitoring entity including one or more of the following: generating timing information at a master node in a packet-switched network, the timing information specifying a value of a master clock; communicating the timing information from the master node to a plurality of slave nodes over a first plurality of time-division multiplexing (TDM) pseudowires; running a digital phase-locked loop on each slave node to synchronize each slave node to the master clock, wherein each digital phase-locked loop outputs a frequency at which the respective slave node is operating; sending the frequency outputted by each digital phase-locked loop to a monitoring entity over a second plurality of TDM pseudowires; utilizing the outputted frequencies at the monitoring entity to identify all slave nodes that are experiencing timing problems; and implementing a remedial measure for all slave nodes that are experiencing timing problems.

System and method for communicating timing to a remote node

Abstract: A system and method for synchronizing a clock for data transmissions. A data packet is received at a remote node. A timing characteristic of the data packet corresponds to a tick of a clock form a reference clock. A tick of the clock is determined based on the timing characteristic of the data packet. A secondary clock is disciplined with the reference clock by adjusting the secondary clock based on a difference between times measured by the reference clock and the secondary clock to generate a clock signal. The clock signal is communicated to one or more interfaces.