Showing papers on "Master clock published in 2009"

Daily rhythms of food-anticipatory behavioral activity do not require the known circadian clock

Abstract: When food availability is restricted to a particular time each day, mammals exhibit food-anticipatory activity (FAA), a daily increase in locomotor activity preceding the presentation of food. Considerable historical evidence suggests that FAA is driven by a food-entrainable circadian clock distinct from the master clock of the suprachiasmatic nucleus. Multiple food-entrainable circadian clocks have been discovered in the brain and periphery, raising strong expectations that one or more underlie FAA. We report here that mutant mice lacking known circadian clock function in all tissues exhibit normal FAA both in a light–dark cycle and in constant darkness, regardless of whether the mutation disables the positive or negative limb of the clock feedback mechanism. FAA is thus independent of the known circadian clock. Our results indicate either that FAA is not the output of an oscillator or that it is the output of a circadian oscillator different from known circadian clocks.

Clocks in the Green Lineage: Comparative Functional Analysis of the Circadian Architecture of the Picoeukaryote Ostreococcus

Abstract: Biological rhythms that allow organisms to adapt to the solar cycle are generated by endogenous circadian clocks. In higher plants, many clock components have been identified and cellular rhythmicity is thought to be driven by a complex transcriptional feedback circuitry. In the small genome of the green unicellular alga Ostreococcus tauri, two of the master clock genes Timing of Cab expression1 (TOC1) and Circadian Clock-Associated1 (CCA1) appear to be conserved, but others like Gigantea or Early-Flowering4 are lacking. Stably transformed luciferase reporter lines and tools for gene functional analysis were therefore developed to characterize clock gene function in this simple eukaryotic system. This approach revealed several features that are comparable to those in higher plants, including the circadian regulation of TOC1, CCA1, and the output gene Chlorophyll a/b Binding under constant light, the relative phases of TOC1/CCA1 expression under light/dark cycles, arrhythmic overexpression phenotypes under constant light, the binding of CCA1 to a conserved evening element in the TOC1 promoter, as well as the requirement of the evening element for circadian regulation of TOC1 promoter activity. Functional analysis supports TOC1 playing a central role in the clock, but repression of CCA1 had no effect on clock function in constant light, arguing against a simple TOC1 /CCA1 one-loop clock in Ostreococcus. The emergence of functional genomics in a simple green cell with a small genome may facilitate increased understanding of how complex cellular processes such as the circadian clock have evolved in plants.

Cell "circadian" cycle: new role for mammalian core clock genes.

Abstract: In mammals, 24 hours rhythms are organized as a biochemical network of molecular clocks that are operative in all tissues, with the master clock residing in the hypothalamic suprachiasmatic nucleus (SCN). The core pacemakers of these clocks consist of auto-regulatory transcriptional/post-transcriptional feedback loops. Several lines of evidence suggest the existence of a crosstalk between molecules that are responsible for the generation of circadian rhythms and molecules that control the cell cycle progression. In addition, highly specialized cell cycle checkpoints involved in DNA repair after damage seem also, at least in part, mediated by clock proteins. Recent studies have also highlighted a putative connection between clock protein dysfunction and cancer progression. This review discusses the intimate relation that exists between cell cycle progression and components of the circadian machinery.

Time synchronization method and device in passive optical network and passive optical network

Abstract: A time synchronization method and a time synchronization device in a passive optical network (PON), and a PON are provided. The method includes receiving a synchronization packet sent after time synchronization of an optical line terminal (OLT) with a master clock (MC) is achieved, wherein the synchronization packet carries a timestamp TMt1 i determined after the time synchronization of the OLT is achieved, adjusting a local clock according to the timestamp to achieve time synchronization of an optical network unit/optical network terminal (ONU/ONT) with the OLT, and after the time synchronization of the OLT is achieved, instructing an slave clock (SC) to perform time synchronization. A time synchronization device and a time synchronization system for implementing the method in a PON are further provided.

How nuclear receptors tell time

Abstract: Most organisms adapt their behavior and physiology to the daily changes in their environment through internal (∼24 h) circadian clocks. In mammals, this time-keeping system is organized hierarchically, with a master clock located in the suprachiasmatic nuclei of the hypothalamus that is reset by light, and that, in turn, coordinates the oscillation of local clocks found in all cells. Central and peripheral clocks control, in a highly tissue-specific manner, hundreds of target genes, resulting in the circadian regulation of most physiological processes. A great deal of knowledge has accumulated during the last decade regarding the molecular basis of mammalian circadian clocks. These studies have collectively demonstrated how a set of clock genes and their protein products interact together in complex feedback transcriptional/translational loops to generate 24-h oscillations at the molecular, cellular, and organism levels. In recent years, a number of nuclear receptors (NRs) have been implicated as important regulators of the mammalian clock mechanism. REV-ERB and retinoid-related orphan receptor NRs regulate directly the core feedback loop and increase its robustness. The glucocorticoid receptor mediates the synchronizing effect of glucocorticoid hormones on peripheral clocks. Other NR family members, including the orphan NR EAR2, peroxisome proliferator activated receptors-α/γ, estrogen receptor-α, and retinoic acid receptors, are also linked to the clockwork mechanism. These findings together establish nuclear hormone receptor signaling as an integral part of the circadian timing system.

Network devices, methods and/or systems for use in a media network

Abstract: In certain aspects, the present disclosure is related to devices, methods, systems and/or computer-readable media for use in an isochronous media network in which media devices connected to a network employ one or more synchronization signal to regulate or facilitate the transmission of media signals through the network. In certain aspects, the present disclosure is also related to devices, methods, systems and/or computer-readable media for use in a larger unified, or substantially unified, isochronous network created from aggregating local isochronous media networks in which media devices connected to a network employ a one or more synchronisation signal distributed from a local master clock to regulate or facilitate the transmission of media signals.

Differential time synchronization of intelligent electronic devices

Abstract: In a utility monitoring system, a network of intelligent electronic devices (IEDs), including a master IED that receives master clock information from a global positioning system, includes a differential time synchronization (DTS) algorithm for automatically adjusting the corresponding clocks of each of the IEDs to be synchronized with the master clock information. A controller coupled to the network communicates instructions to the IEDs to collect frequency variation data. A known data alignment algorithm determines a point of alignment between two sets of frequency variation data, and the controller determines based on the data alignment algorithm output a time differential representing a time offset between the IED's clock and the master clock information. The time differential is communicated to the target IED, which advances or retards its clock based on the time differential.

Two ~35 day clocks in Hercules X-1: evidence for neutron star free precession

Abstract: We present evidence for the existence of two ∼35 day clocks in the Her X-1/HZ Her binary system. ∼35 day modulations are observed 1) in the Turn-On cycles with two on- and two off-states and 2) in the changing shape of the pulse profiles which re-appears regularly. The two ways of counting the 35 day cycles are generally in synchronization. This synchronization did apparently break down temporarily during the long Anomalous Low (AL3), which Her X-1 experienced in 1999/2000, in the sense that there must have been one extra Turn-On cycle. Our working hypothesis is that there are two clocks in the system, both with a period of about ∼35 days: precession of the accretion disk (the less stable “Turn-On clock”) and free precession of the neutron star (the more stable “Pulse profile clock”). We suggest that free precession of the neutron star is the master clock and that the precession of the accretion disk is basically synchronized to that of the neutron star through a feedback mechanism in the binary system. However, the Turn-On clock can slip against its master when the accretion disk has a very low inclination, as is observed to be the case during AL3. We take the apparent correlation between the histories of the Turn-Ons ,o f theAnomalous Lows and of the pulse period evolution, with a 5 yr quasi-periodicity, as evidence for strong physical interaction and feedback between the major components in the system. We speculate that the 5 yr (10 yr) period is due either to a corresponding activity cycle of HZ Her or a natural ringing period of the physical system of coupled components. The question of whether free precession really exists in neutron stars is very important for understanding matter with supra-nuclear density.

Method and system for network synchronization via a femtocell

Abstract: Aspects of a method and system for communication are provided. In this regard, a femtocell may receive messages from a plurality of different sources comprising one or more other femtocells, one or more cellular enabled communication devices, and one or more non-cellular network nodes. The femtocell may select, based on the received messages, a master clock within one of the plurality of different sources as a master clock for synchronization of the plurality of different sources. A femtocell clock, a global navigational satellite signal (GNSS) clock, a cellular base station clock, or a cellular enabled communication device clock may be selected as the master clock. The femtocell may transmit and/or receive synchronization messages to and/or from the one or more cellular enabled communication devices and the one or more non-cellular network nodes.

Clock for a node of a packet-switched network, and associated synchronisation method

Abstract: A method for synchronising a plurality of clocks (1, 5, 6, 7, 8) arranged within a plurality of nodes (11, 15, 16, 17, 18) of a packet-switching network comprising the steps consisting in comparing parameters relating to the clocks in order to determine master-slave relationships between said clocks, and to exchange time-stamped messages over the packet-switching network each time between a master clock (5) and an associated slave clock (6) in order to make the slave clock subservient to the master clock. A node (15) of said network comprises a frequency source controlled by a synchronous physical layer technology. The parameters relating to a clock (5) of said node comprise a parameter relating to said frequency source, so as to determine said master-slave relationships based on one property of said frequency source controlled by a synchronous physical layer technology.

Three-dimensional chip-stack synchronization

Abstract: a central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.

Synchronising between clock domains

Abstract: An integrated circuit 2 is provided with multiple clock domains separated by a clock boundary 8 . Data values are passed across the clock boundary 8 using a first-in-first-out memory (FIFO), a read pointer and a write pointer for the FIFO are passed across the clock boundary 8 and must be synchronized to the receiving clock frequency. The clocks being used on either side of the clock boundary 8 may be switched and have a variable relationship therebetween. Multiple synchronization paths are provided within pointer synchronizing circuitry 32 which are used depending upon the particular relationship between the clocks on either side of the clock boundary 8 . A pre-switch pointer value is held in a transition register 44 until a post-switch pointer value is available from the new synchronizing path 36 when a switch in clock mode is made which requires an increase in synchronization delay.

Precise Clock Synchronization

Abstract: A method for clock synchronization includes computing an offset value between a local clock time of a real-time clock circuit and a reference clock time, and loading the offset value into a register that is associated with the real-time clock circuit. The local clock time is then summed with the value in the register so as to give an adjusted value of the local clock time that is synchronized with the reference clock.

IEEE 1588 clock synchronization using dual slave clocks in a slave

Abstract: IEEE 1588 is a standard used in the synchronization of independent clocks that run on separate nodes of a distributed measurement and control system. This work presents a method that employs dual slave clocks in a slave to measure the link propagation delay, clock skew and offset. By accurately deriving these parameters, the proposed approach can reduce the deviation from the master clock to several orders of magnitude better than the required specification. The proposed technique fully conforms to the IEEE 1588, and can be used in the environments of symmetric and asymmetric communication links, such as xDSL.

Time synchronization in units at different locations

Abstract: To synchronize units of a formation evaluation/drilling operation evaluation system, a time delay associated with a communications link between a master unit and a slave unit of the formation evaluation/drilling operation evaluation system is determined. The master unit has a master time clock that provides universal time. The time delay associated with the communications link is used to enable synchronization of time provided by a slave time clock in the slave unit to the universal time.

Data latch with structural hold

Abstract: A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latch (540) generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry (550) generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry (564) uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.

Method and system for realizing high precision time synchronization among SDH equipment

Abstract: A method for realizing high precision time synchronization among synchronous digital hierarchy (SDH) equipment includes the step: a piece of SDH equipment as a slave clock and a piece of SDH equipment as a master clock use the idle bytes in section overhead of an SDH frame to conduct the interaction of PTP messages, the time difference between the slave clock and the master clock is calculated and the time difference is utilized to calibrate the slave clock. And a system for realizing high precision time synchronization among SDH equipment includes: the SDH equipment as the slave clock and the SDH equipment as the master clock. The slave clock uses the idle bytes in section overhead of the SDH frame to conduct the interaction of PTP messages with the master clock and calculates the time difference with the master clock, and then the time difference is used to calibrate the slave cock. The master clock uses the idle bytes in section overhead of the SDH frame to conduct the interaction of PTP messages with the slave clock. The adoption of the method and the system can ensure that the high precision time synchronization among the SDH equipment is realized and satisfy the requirements of all mobile communication systems at the present stage.

High availability clock synchronization and distribution for mobile backhaul networks

Abstract: Fully redundant clock systems are provided on network nodes coupled by redundant multisegment psuedowires (MSPWs) within an internet-protocol (IP)-based mobile backhaul network. The primary clock system includes a primary master clock on a first node and a primary slave clock on a second node coupled via a primary MSPW, while the secondary clock system includes a secondary master clock on the first node and a secondary slave clock on the second node coupled via a secondary MSPW. The primary and secondary slave clocks synchronize with their respective primary and secondary master clocks via their respective MSPWs. A clock controller maintains the secondary clock system in a hot-stand-by mode, and upon determining that a switch-over is needed, automatically switches from the primary clock system to the secondary clock system.

Automatic management of timestamp-based synchronisation protocols

Abstract: A method for automatic management of a timestamp-based synchronization protocol within a packet-based network to synchronize a slave within a synchronization topology including a plurality of masters, the slave clock being locked to a master clock at an initialization time, said method comprising an assessment step of end-to-end packet delay variation on the basis of the slave clock accuracy, over a plurality of (slave, path, master) combinations, each path linking the slave to a master.

Linear unbiased prediction of clock errors

Abstract: In this paper, we propose a new formula for linear unbiased prediction of the local clock timescales. To predict future errors over all the measurement data, a new gain is derived for the p-step ramp unbiased finite impulse response (FIR) predictor. We then show that this gain gives the best linear unbiased fit suitable for forming the prediction vector. The predictor proposed is consistent with linear regression and best linear unbiased estimator. Applications are given for a crystal clock and the USNO Master Clock.

A 4096-pixel MAPS device with on-chip data sparsification

Abstract: A prototype of a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensor (MAPS) was fabricated via STM 130 nm CMOS technology. Groups of 4×4 pixels form a macro-pixel (MP). The readout architecture is parallel and could overcome the readout speed limit of big matrices. As the output port can only accept one-hit information at a time, an internal queuing system has been provided to face high hit-rate conditions. The ASIC can work in two different manners as it can be connected to an actual full-custom matrix of MAPS or to a digital matrix emulator composed of standard cells, for testing facilities. For both operating modes a slow-control phase is required to load the chip configuration. Previous versions of similar ASICs were designed and tested. The work is aimed at improving the design of MAPS detectors with an on-chip fast sparsification system, for particle tracking, to match the requirements of future high-energy physics experiments. The readout architecture implemented is data driven extending the flexibility of the system to be also used in first level triggers on tracks in vertex detectors. Preliminary simulations and tests indicate that the readout system can cope with an average hit-rate up to 100 MHz/cm 2 if a master clock of 80 MHz is used, while maintaining an overall efficiency over 99%.

Time Synchronization Method and System for Multicore System

Abstract: A time synchronization method and system for a multi-core system are provided. The time synchronization method comprises: establishing at least one clock synchronization domain, and respectively allocating each core to each clock synchronization domain; selecting a core with a lowest load in each clock synchronization domain as a master clock synchronization source in the clock synchronization domain, and selecting the clock synchronization domain having the master clock synchronization source with a lowest load as a master clock synchronization domain, while other clock synchronization domains as slave clock synchronization domains; the master clock synchronization domain sending a synchronization deviation detection message to each slave clock synchronization domain, and calculating a time deviation value; when the time deviation value is greater than a permitted deviation value, the master clock synchronization domain calculating a time adjustment quantity and releasing to each slave clock synchronization domain, making adjustment based on its time adjustment quantity.

A flexible communication scheme for rationally-related clock frequencies

Abstract: As a replacement for the fast-fading Globally-Synchronous model, we have defined a flexible design style for SoCs, called GRLS, for Globally-Ratiochronous, Locally-Synchronous, which does not rely on global synchronization and is based on using rationally-related clock frequencies derived from the same source. In this paper, using the special periodical properties of rationally-related systems, we build a latency-insensitive, maximal-throughput, low-overhead communication method, based on the idea of using both clock edges to sample data at the Receiver. The validity of the method and its resistance to non-idealities such as jitter, misalignments and clock drifts are formally proven while experimental results including overhead are presented for 90 nm technology. Despite allowing much greater flexibility, the overhead of our method is comparable to that of state-of-the-art mesochronous communication techniques. We also show performances, complexity and overhead improvements over all other approaches that have so far been proposed for rationally-related clock frequencies.

Apparatus and method for time synchronization and reception apparatus of OFDM system

Abstract: An apparatus for time synchronization of an orthogonal frequency division multiplexing (OFDM) system oversamples a received signal using a master clock having a frequency at least four times higher than a minimum sampling frequency in a transmission apparatus, sets one of a plurality of oversampled signals to an on-time signal, and shifts each of the remaining oversampled signals by a predetermined time on the basis of the on-time signal. The apparatus for time synchronization calculates a correlation value by correlating each of the shifted signals and the on-time signal with a previously known signal, detects a maximum energy value among the calculated correlation values, and detects a start point of a frame by comparing the maximum energy value with a predetermined threshold value.

System clock synchronization apparatus and method for mobile communication system

Abstract: A system clock synchronization apparatus, for use in a mobile communication system, supplies a GPS clock received from a GPS reception module to a Radio Frequency clock generation module and selects a candidate system clock. The candidate system clock is selected from among plural candidate system clocks having different phases, which can be most stably synchronized with a reference synchronization time signal as the final system clock. The apparatus includes a Global Positioning System reception module; a Radio Frequency clock generation module that generates a system reference clock and outputs an RF clock generated by synchronizing the system reference clock to the GPS clock in phase; and a system clock generation module that generates multiple candidate system clocks having different phases using the RF clock and selects one of the candidate system clocks which generates in a range of an enable duration of the reference synchronization time signal.

Feeding the Clock

Abstract: In mammals, sleeping, feeding, and most other physiological processes are influenced by a circadian system and therefore display daily oscillations. These rhythms are generated by self-sustained and cell-autonomous molecular clocks that exist in virtually all cell types. A “master clock” located in the brain's suprachiasmatic nucleus (SCN) can synchronize these peripheral clocks, but for many organs, feeding-fasting rhythms are the dominant zeitgebers (timing cues) ( 1 , 2 ). On page 437 of this issue, Lamia et al. propose a molecular mechanism through which metabolic cycles may interact with the circadian clockwork circuitry. They show that an enzyme that responds to nutrient availability—adenosine monophosphate–activated protein kinase (AMPK)—directly phosphorylates the core clock protein cryptochrome 1 (CRY1), thereby marking it for degradation ( 3 ).

Dynamic drift compensation for the Distributed clock in EtherCAT

Abstract: This paper focuses on the synchronization between master clock and slave clock in the Distributed clock of EtherCAT. It supports very accurate synchronization function which let local slaves follow reference time under the degree of few nano second differences. However, there exists the propagation delay between reference clock and slave clock. To remove the delay, EtherCAT uses the static compensation method but it wastes a lot of control frames and leads each slave to be delayed. To solve this problem, we design the dynamic compensation model for the local source drift. This method is beneficial to the Embedded system because it efficiently manages the system resource of the target system by trade off cyclic time and accuracy of synchronizing the time.

Communication system, station-side communication device, and slave clock correction device

Abstract: PROBLEM TO BE SOLVED: To perform time synchronization of a station-side communication device and a subscriber-side communication device by a simple method. SOLUTION: The station-side communication device 1 includes: a measurement unit 11 which measures an RTT value between the own device and a subscriber-side communication device 2; a time synchronization frame generation unit 12 which generates a time synchronization frame by inserting the measured RTT value into a frame; and a time stamp insertion unit 15 which inserts the time stamp of a master clock 14 into the time synchronization frame thus generated and transmits the time stamp to the subscriber-side communication device 2. A slave clock correction device 4 includes: a time synchronization frame extraction unit 41 which extracts a time synchronization frame transmitted to the subscriber-side communication device 2; and a time stamp correction unit 42 which corrects the time stamp of a slave clock 43 based on the RTT value and the time stamp contained in the time synchronization frame thus extracted. COPYRIGHT: (C)2011,JPO&INPIT

Probabilistic model for clock synchronization of cascaded network elements

Abstract: Precision Time Protocol (PTP) synchronizes clocks of networked elements by exchanging messages containing precise time-stamps. A master clock is carefully chosen to provide the reference clock to the rest elements in the network, called slaves. Using the time-stamps, slave element learns the relation between its own clock and the master clock so that it can synchronize its time to the reference time. Uncertainties, e.g., random stamping and quantization errors, affect the synchronization precision. This paper presents a probabilistic state-space model which quantifies the uncertainties and represents the relation between system variables. Estimation of hidden variables, i.e. the system states, is carried out by using Kalman filter. The performance of this approach is verified by numerical results.