Showing papers on "Master clock published in 2011"

Method and apparatus for synchronizing measurements taken by multiple metrology devices

Abstract: Apparatus includes at least two devices that communicate with each other, wherein a first one of the at least two devices having an IEEE 1588 precision time protocol interface, the interface including one or more components configured for communications in both a wired manner and a wireless manner with a second one of the at least two devices. The second one of the at least two devices having an IEEE 1588 precision time protocol interface, the interface including one or more components configured for communications in both a wired manner and a wireless manner with the first one of the at least two devices. Wherein one of the at least two devices includes a master clock and the other one of the at least two devices includes a slave clock, wherein the master clock communicates a time to the slave clock and the slave clock is responsive to the communicated time from the master clock to adjust a time of the slave clock if necessary to substantially correspond to the time of the master clock, thereby time synchronizing the at least two devices together.

Distributed digital reference clock

Abstract: A communication system includes master host unit, hybrid expansion unit, and remote antenna unit. Master host unit communicates analog signals with service provider interfaces. Master host unit and hybrid expansion unit communicate N-bit words of digitized spectrum over communication link. Hybrid expansion unit converts between N-bit words and analog spectrum. Hybrid expansion unit and remote antenna unit communicate analog spectrum over analog communication medium. Remote antenna unit transmits and receives wireless signals over air interfaces. Master host unit includes master clock distribution unit that generates digital master reference clock signal. Master host unit communicates digital master reference clock signal over communication link. Hybrid expansion unit receives digital master reference clock signal from master host unit over communication link and generates analog reference clock signal based on digital master reference clock signal. Hybrid expansion unit sends, and remote antenna unit receives, analog reference clock signal across analog communication medium.

Method and system for frequency synchronization

Abstract: The present invention provides a method of synchronising the frequency of a slave clock to that of a master, preferably using a packet network. An aspects of the invention provide a method of synchronizing the frequency of a slave clock in a slave device to a master clock in a master device, the method including the steps of: a) receiving in the slave device a first message from said master device having a first time-stamp which is a time-stamp of said master clock indicating the time of sending of said first message; b) extracting said time-stamp from said message and initializing a counter in the slave device which counts an output of said slave clock; c) receiving in the slave device a further message from said master device and reading the value of said counter at the time of receipt of said further message; d) extracting a further time-stamp which is the precise time of sending of the further message according to said master clock; e) determining an error signal which is representative of the difference between said value of the counter and the difference between said first and further time-stamps; and f) adjusting the frequency of said slave clock based on said error signal. An apparatus for synchronizing the frequency of a clock in a slave device which is communicatively coupled to a master device is also provided.

Secure clock synchronization

Abstract: The present disclosure provides a secure one-step IEEE 1588 clock using either a symmetric or asymmetric protection scheme Clocks of mission-critical or highly-available devices in industrial automation systems connected to a communication network are synchronized by sending, by a master clock, a synchronization message, eg, a single message of the one-step-clock type according to IEEE 1588, including a time stamp, and by receiving and evaluating, by a slave clock, the synchronization message A synchronization component or module of the master clock prepares, or composes, prior to a projected send time, a synchronization message including a time stamp of the projected send time, and secures the synchronization message in advance of the projected send time Securing the synchronization message occurs by suitable cryptographic means allowing for authentication of the time stamp at a receiving slave clock At the projected send time, the secured synchronization message is transmitted

Master/slave control of touch sensing

Abstract: Touch sensing can be accomplished using master/slave touch controllers that transmit drive signals to a touch surface and process sense signals including superpositions resulting from master/slave drive signals. The master/slave can drive and sense different sets of lines, respectively, of the touch surface. A communication link between master/slave can be established by transmitting a clock signal between master/slave, transmitting a command including sequence information to the slave, and initiating a communication sequence from the clock signal and sequence information. The slave can receive/transmit communications from/to the master during first/second portions of the communication sequence, respectively. Touch sensing operations can be synchronized between master/slave by transmitting a command including phase alignment information from master to slave, and generating slave clock signals based on the clock signal and the phase alignment information, such that sense signal processing by master clock signals are in-phase with sense signal processing by slave clock signals.

Method And System For Synchronizing Shutter Glasses To A Display Device Refresh Rate

Abstract: A video viewing shutter device, which is wirelessly coupled to a multi-view video display device, generates a slave clock based on a master clock in the display device. The slave and master clocks may be Bluetooth clocks and maintain synchronization. The video viewing shutter device receives display information regarding display of independent video frames and time information referenced to the master clock. Time information corresponds to display time of independent frames. Both shutters open and/or close together, during frame display time, based on the slave clock, display information and/or master clock information. Display information may concern a pattern of independent frames and/or blank frames, pattern display time, refresh rate and/or a time offset. Master clock time information corresponds to frame display time. Shutter open and close times may be maintained when display and/or time information is not received. Information may be transmitted to the multi-view video display device.

Rotating harmonic rejection mixer

Abstract: In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.

Method for synchronizing master and slave clocks of packet-switched network with aggregated connections between nodes, and associated synchronization devices

Abstract: A method is dedicated to synchronizing master (HM) and slave clocks (HE) of a packet-switched network comprising at least two equipments (E1, E2) that are connected to one another via an aggregated connection made up of at least two links (L1-L3) and that are located between said master (HM) and slave clocks (HE) in order to enable them to transmit synchronization packets to one another using a timestamp protocol. This method comprises the following steps: (a) obtaining a distribution of the synchronization packets in at least one subset of the links that transport these synchronization packets, and (b) transmitting to the slave clock (HE) first information representative of that distribution, second information representative of timestamps associated with the synchronization packets, and third information representative of packet transmission times over the links (L1-L3), in order to synchronize the slave clock (HE) to the master clock (HM) as a function of at least this first, second, and third information transmitted.

Synchronization of computer system clock using a local gateway

Abstract: Methods and apparatuses for synchronizing a system clock of a computer via a local gateway are described herein. In one embodiment, a local clock of a gateway device is periodically synchronized with a remote time service facility over an external network. The synchronized local clock of the gateway device is then used to synchronize a system clock of one or more clients over a local network without having the clients individually to access the remote time service facility. Other methods and apparatuses are also described.

Methods of time synchronisation in communications networks

Abstract: A method 10 of providing a path delay asymmetry for time synchronization between a master clock at a first client node and a slave clock at a second client node across a server communications network. The method comprises: mapping a first time protocol signal (TPS) carrying master clock time protocol data onto a first transmission signal, determining a forward mapping delay, dmf, and providing dmf to a path delay asymmetry calculation element 12; mapping a second TPS carrying slave clock time protocol data onto a second transmission signal, determining a reverse mapping delay, dmr, and providing the dmr to the path delay asymmetry calculation element 14; applying FEC to the first transmission signal, determining a forward FEC delay, dfecf, and providing the dfecf to the path delay asymmetry calculation element 16; applying FEC to the second transmission signal, determining a reverse FEC delay, dfecr, and providing dfecr to the path delay asymmetry calculation element 18; calculating a path delay asymmetry in dependence on dmf, dmr, dfecf and dfecr 20; and providing the path delay asymmetry to a time protocol client at the second client node 22.

Systems and methods for transporting time-of-day information in a communication system

Abstract: Systems and methods for synchronizing a clock at a customer premises equipment (CPE) location with a master clock at a central office (CO) location are described. One embodiment is a method that comprises receiving, by a time-of-day transmission convergence (ToD-TC) module in the CPE, ToD information relating to the master clock. Based on the received information, time stamps are applied to reference data samples. The method further comprises transporting the ToD information by transporting the reference data samples with applied time stamps and utilizing time stamps of the reference data samples to synchronize the CPE clock with the master clock.

Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network

Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.

Method for correcting a delay asymmetry

Abstract: Exemplary methods and apparatuses are provided for a method for correcting for a delay asymmetry of synchronization messages transmitted within a packet-switched network between a master clock and a slave clock, in which the delay asymmetry of the path connecting the master clock to the slave clock is determined and corrected locally within at least one link of said path. One or more signals are transmitted on one or more wavelengths over at least one optical fiber. The one or more signals are received and detected on the one or more wavelengths over the at least one optical fiber. The technique determines an arrival time difference between the received and detected one or more signals, and calculates a delay asymmetry of an adjacent link based on the time difference.

Institute of electrical and electronic engineers (IEEE)-1588-protocol-based frequency regulation method and network device

Abstract: The invention provides an institute of electrical and electronic engineers (IEEE)-1588-protocol-based frequency regulation method and a network device. The method comprises that: transparent clock equipment calculates a frequency difference of the transparent clock equipment relative to master clock equipment according to master clock information carried in a received IEEE 1588 protocol message and the time information of local stamping; and if judging the frequency difference meets preset conditions, the transparent clock equipment regulates the frequency of the local stamping to be the same as that of the master clock information carried in the IEEE 1588 protocol message by utilizing the frequency difference. By the method and the device, the frequency accuracy of the transparent clock (TC) equipment is effectively improved, and simultaneously, the cost is reduced.

Smart clocks have a hand in the smart grid

Abstract: Clock synchronization is becoming an increasingly important characteristic of modern wide area monitoring and control systems such as the power grid. It provides an opportunity to coordinate control actions and measurement instants across hundreds of miles and numerous network topologies. Devices and networks have advanced to a point where synchronization across a wide area can be achieved within 1 μs of UTC (Coordinated Universal Time). Along with these advances in clock synchronization must come a shift in the way analysis is performed. Modeling techniques must incorporate the effects of a clock synchronized device, and control techniques can leverage the knowledge of ”time” to achieve unique results. This paper discusses various ways in which clock synchronization affects analysis and performance of the power grid, and presents a few projects related to the technology. Preliminary work has demonstrated the ability of various commercially available devices to provide reliable 1 μs synchronization of clocks, and large variation across devices in terms of clock performance under transient events.

A master CLOCK hard at work brings rhythm to the transcriptome.

Abstract: In this issue of Genes & Development, Abruzzi et al. (pp. 2374-2386) use chromatin immunoprecipitation (ChIP) tiling array assays (ChIP-chip) to show that physical interactions between circadian (≅24-h) clock machineries and genomes are more widespread than previously thought and provide novel insights into how clocks drive daily rhythms in global gene expression.

Simulations of a chain of Telecom Boundary Clocks combined with Synchronous Ethernet for phase/time transfer

Abstract: This paper describes the use of Boundary Clocks for clock distribution (phase/time transfer) in telecom networks. The technology is primarily used to meet synchronization requirements of mobile systems such as TD-SCDMA and LTE, and to reduce the use of and dependency on GPS systems deployed in base stations. We describe the most important functions of a Telecom Boundary Clock, which are under discussion at ITU-T. We then present a network reference model and simulation model based on IEEE1588 and Synchronous Ethernet. The results indicate that it is possible to transfer phase/time in a telecom network for meeting the microsecond-level requirement of various mobile systems. The paper also discusses some of the ongoing activities in standardization bodies so that IEEE1588 can be used as a technology in telecom networks.

Clock synchronization device and method

Abstract: The invention discloses a clock synchronization device and method The device realizes a precision clock synchronization protocol PTP 1588 by adopting hardware and comprises a time processing module, a recognizing module, a separating module, a protocol processor and a CPU (Central Processing Unit) processing module, wherein the time processing module is used for sampling and generating and/or correcting a timestamp of a message of PTP1588 according to sampled time information; the recognizing module is connected to the time processing module and used for correcting the message received by the time processing module by using an asymmetric compensation value and a path delay value; the separating module is connected to the recognizing module and used for carrying out path processing on the received message according to a working mode of a time synchronization device; the protocol processor is connected to the separating module and used for obtaining the type of the received message and processing the received message in a type corresponding way; and the CPU processing module is used for selecting a master clock by using an optimal master clock algorithm and/or calculating a master-slave time difference and carrying out time synchronization By adopting the invention, the time and frequency restoring precision is improved

System and method to overcome wander accumulation to achieve precision clock distribution over large networks

Abstract: A system and method for synchronizing clocks across a packet-switched network eliminates wander accumulation to enable precision clock distribution across a large network. In addition to standard Precision Time Protocol (PTP) synchronization messages or similar time synchronization messages, each clock regenerator stage receives a grand clock error message from the previous stage, updates this error message with its own stage clock error, and then transmits the updated grand clock error to the next stage. This enables the synchronization algorithm to compensate for the error of the previous stage, effectively locking each clock regenerator stage to the grand master clock directly.

Spectrum analyzer using multiple intermediate frequencies and multiple clock configurations for residual, spurious and image signal reduction

Abstract: A spectrum analyzer for measuring an RF signal over a selected frequency span configured to use multiple Intermediate Frequencies (IFs) for residual, spurious and image signal reduction. The spectrum analyzer has both a primary IF path and a secondary IF path configured to provide band pass filtering of the IF signals. A master clock synthesizer is configured to reduce residual noise by providing from a single Voltage Controlled Oscillator, a master clock signal and a Local Oscillator (LO) signal. The spectrum analyzer has a microcontroller configured to change the frequency of the master clock signal and the LO signal if the center frequency of the selected span is sufficiently close to a known spurious signal.

The DAQ readout chain of the DSSC detector at the European XFEL

Abstract: The DSSC collaboration is developing an instrument to detect synchrotron X-rays (E > 05 keV) at the European XFEL The DEPFET based sensors with integrated signal compression will be read out by 16 dedicated readout ASICs per sensor main board Data are acquired during the XFEL burst (≈ 600 µs) at a rate of up to 45 MHz, and subsequently read out by the DAQ readout chain during the approximately 994 ms long burst gaps The DAQ readout chain comprises two FPGA-based detector specific modules (I/O Board and Patch Panel Transceiver), which will be described in detail A concentrator stage (Trainbuilder), which is common to all 2D detectors and part of the general XFEL DAQ, receives the data, and forwards them to the back-end storage facility Each sensor main board has an I/O Board Its purpose is to concentrate the data of the 16 low-speed channels of the ASICs into four high-speed serial links The I/O Board also controls the shutdown of the analog sections during the readout phase to minimize the power consumption of the DSSC detector The accumulated data will be sent to the Patch Panel Transceivers residing on the head of the detector A Patch Panel Transceiver receives the XFEL front-end electronics (FEE) clock (≈ 99 MHz) and commands from the master Clock & Control unit In addition, it provides the ASICs with control telegrams generated by the FPGA An on-board PLL generates the ADC sampling clock of approximately 700 MHz, which is derived from, and in phase with the XFEL FEE clock

Clock synchronization method, equipment and system

Abstract: The invention provides a clock synchronization method, clock synchronization equipment and a clock synchronization system. The method comprises the following steps of: in a first transmission mode, generating a first receiving timestamp by using a first link and acquiring a first transmitting timestamp of master clock equipment; in a second transmission mode, generating a second transmitting timestamp by using the first link and acquiring a second receiving timestamp of the master clock equipment; and according to the first receiving timestamp, the first transmitting timestamp, the second transmitting timestamp and the second receiving timestamp, acquiring a time deviation with the master clock equipment; and realizing clock synchronization with the master clock equipment through the time deviation. The embodiment of the invention provides slave clock equipment and the master clock equipment. The embodiment of the invention also provides the clock synchronization system. The method, the equipment and the system realize the uniformity of message round trip links between the master clock equipment and the slave clock equipment, and ensure the symmetry of uplink delay and downlink delay.

Preventing the Collision of Requests From Slave Clocks in the Precision Time Protocol (PTP)

Abstract: The Precision Time Protocol (PTP) distributes a time reference across a network. It specifically addresses demanding environments, where it can reach sub microsecond precision using appropriate technologies. Its scalability is primarily limited by packet delay variations induced by packet collisions. While it is possible to avoid collisions with non-PTP packets using traffic management technologies, collision between PTP packets is an open problem in large systems with critical clock precision requirements. We propose a coordination algorithm that avoids the occurrence of such collisions. It assumes that the master clock, which is the timing reference source, can send a packet in multicast to the slaves: this is not a restrictive hypothesis, since PTP itself takes advantage of this kind of connectivity, and it is also compatible with typical wireless environments. The algorithm operates without introducing additional traffic, it ensures an upper bound to the time between two successive synchronizations of any given slave, it does not alter the structure of the standard PTP messages, it envisions a dynamic number of slaves, it tolerates the replacement of the master with a hot spare in case of failure, and does not rely on specialized hardware. The algorithm has a footprint that does not insist on activities that are already time sensitive, and its operation is mostly concentrated on the master. The algorithm inherits security and fault tolerance limits from PTP: in particular this refers to malicious nodes, and to broken devices that may jam the network.

Non-intrusive method for synchronizing master and slave clocks of a packet-switched network, and associated synchronization devices

Abstract: A method for synchronizing master (HM) and slave (HE) clocks of a packet - switched network, capable of exchanging synchronization packet flows with one another via intermediary equipments (E1-E9) of that network that are connected to one another, said method comprising the following steps: i) determining within each intermediary equipment (E1-E9) instant transit times of packets belonging to a first group of packets of at least one chosen flow of synchronization packets, determining a maximum transit time of the packets based on said instant transit times, then acting on packets of a second group of said chosen flow so that their instant transit times within each intermediary equipment (E1-E9) is roughly equal to a said corresponding maximum transit time, and ii) filtering the packets of said chosen flow at least within said slave clock (HE) in order to synchronize it to said master clock (HM) by means of the processed packets of said second group of that chosen flow.

Systems and methods for providing a dual-master mode in a synchronous ethernet environment

Abstract: Embodiments of a dual-master mode Ethernet node are provided herein. The dual-master mode Ethernet node includes a first multiplexer configured to select between a local oscillator signal and a primary reference source (PRS) signal to provide a reference clock signal, a digital phase-locked loop (DPLL) configured to generate a master clock signal based on the reference clock signal, a phase rotator configured to rotate a phase of the master clock signal based on a frequency error between the master clock signal and an extracted clock signal to generate a slave clock signal, and a second multiplexer configured to select between the master clock signal and the slave clock signal to provide a transmit clock signal. The dual-master mode Ethernet node can dynamically generate the transmit clock based on either the extracted clock or the PRS without re-performing the auto-negotiation process.

Circuits and methods for fault testing

Abstract: An integrated circuit sensor includes circuitry and methods for generating a high speed delay fault test clock signal. A trimmable oscillator generates a master clock signal for use by an output protocol processor to provide the sensor output signal. A fault test clock signal generator is responsive to the master clock signal and to a test trigger signal for generating the test clock signal having a launch pulse and a capture pulse, each having edges substantially coincident with like edges of pulses of the master clock signal and a spacing between launch and capture pulses established by the trimmable master clock signal.

Asynchronous master-slave serial communication system, data transmission method, and control module using the same thereof

Abstract: An asynchronous master-slave serial communication system, a data transmission method, and a control module using the same are disclosed. The asynchronous master-slave serial communication system comprises a master control module and a slave control module. The master control module generates a check code according to an address information and a data information, and generates a data package according to the address information, the data information, the check code and the master clock signal. The slave control module generates a decoding data according to the data package and a slave clock signal, and generates the address information, the data information and the check code according to the decoding data.

Method for implementing main clock phase alignment and device thereof

Abstract: This invention discloses a method and a device for aligning phases of master and standby clocks, in which, the method includes: 1, setting a first master phase-locked loop and a first sub-phase-locked loop for the master clock and setting a second master phase-locked loop and a sub-phase-locked loop for the standby clock unit, 2, the master one controls a first clock signal to follow and lock theprimary clock signal by opening the first sub-phase-locked loop and closing the first master loop, 3, the standby clock unit aligns the phases of the first and second clock signals by opening the second master loop and closing the second sub-loop and 4, the standby one reads the control value of the second-sub-loop following the first clock signal and controls that the phase of signals is the same when switching the master and sub-phase-locked loops according to the control value.

Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge

Abstract: An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.

Full horizon optimal FIR estimator of clock state employing measurement of time errors

Abstract: This paper addresses a p-shift full horizon optimal finite impulse response (FIR) estimator of clock state employing all the measurement data available of the time interval error (TIE). A solution proposed is general for filtering (p=0), prediction ( p > 0 ) , and smoothing ( p 0 ) of discrete time clock models in state space. The optimal estimator self-determines the clock initial mean square state by solving the discrete algebraic Riccati equation on a measurement interval of N points. Noise is allowed to be zero-mean with arbitrary distribution and covariance functions. The unbiased FIR estimator is proposed in the batch form producing near optimal estimates when N ⪢ 1 or the clock initial mean square state dominates noise in the order of magnitudes. An application is given to a master clock.