Showing papers on "Master clock published in 2012"

Systematic identification of rhythmic genes reveals camk1gb as a new element in the circadian clockwork.

Abstract: A wide variety of biochemical, physiological, and molecular processes are known to have daily rhythms driven by an endogenous circadian clock. While extensive research has greatly improved our understanding of the molecular mechanisms that constitute the circadian clock, the links between this clock and dependent processes have remained elusive. To address this gap in our knowledge, we have used RNA sequencing (RNA–seq) and DNA microarrays to systematically identify clock-controlled genes in the zebrafish pineal gland. In addition to a comprehensive view of the expression pattern of known clock components within this master clock tissue, this approach has revealed novel potential elements of the circadian timing system. We have implicated one rhythmically expressed gene, camk1gb, in connecting the clock with downstream physiology of the pineal gland. Remarkably, knockdown of camk1gb disrupts locomotor activity in the whole larva, even though it is predominantly expressed within the pineal gland. Therefore, it appears that camk1gb plays a role in linking the pineal master clock with the periphery.

Does the circadian system regulate lactation

Abstract: Environmental variables such as photoperiod, heat, stress, nutrition and other external factors have profound effects on quality and quantity of a dairy cow's milk. The way in which the environment interacts with genotype to impact milk production is unknown; however, evidence from our laboratory suggests that circadian clocks play a role. Daily and seasonal endocrine rhythms are coordinated in mammals by the master circadian clock in the hypothalamus. Peripheral clocks are distributed in every organ and coordinated by signals from the master clock. We and others have shown that there is a circadian clock in the mammary gland. Approximately 7% of the genes expressed during lactation had circadian patterns including core clock and metabolic genes. Amplitude changes occurred in the core mammary clock genes during the transition from pregnancy to lactation and were coordinated with changes in molecular clocks among multiple tissues. In vitro studies using a bovine mammary cell line showed that external stimulation synchronized mammary clocks, and expression of the core clock gene, BMAL1, was induced by lactogens. Female clock/clock mutant mice, which have disrupted circadian rhythms, have impaired mammary development and their offspring failed to thrive suggesting that the dam's milk production was not adequate enough to nourish their young. We envision that, in mammals, during the transition from pregnancy to lactation the master clock is modified by environmental and physiological cues that it receives, including photoperiod length. In turn, the master clock coordinates changes in endocrine milieu that signals peripheral tissues. In dairy cows, it is clear that changes in photoperiod during the dry period and/or during lactation influences milk production. We believe that the photoperiod effect on milk production is mediated, in part by the ‘setting’ of the master clock with light, which modifies peripheral circadian clocks including the mammary core clock and subsequently impacts milk yield and may impact milk composition.

Systems and methods of network synchronization

Abstract: An exemplary method of synchronizing a master clock and a slave clock comprises transmitting a plurality of packets between a master device and a slave device, calculating a first skew between a first pair of the plurality of packets at the slave device and a second skew between the first pair at the master device, calculating a ratio between the first skew and the second skew, providing a slave clock frequency correction to the slave device, calculating a first packet trip delay using a time that the master device initiates sending a packet to the slave device, a time the master device receives a response from the slave device, a corrected time the slave device receives the packet, and a corrected time the slave device initiates sending the response, calculating a first offset based on the first packet trip delay, and providing the first offset to the slave device.

Methods and devices for clock synchronization

Abstract: This invention relates to methods and devices for clock synchronization. The invention makes particular use of IEEE 1588 with offset and skew correction. In embodiments of the invention, the IEEE 1588 Precision Time Protocol is used to exchange time stamps between a time server and a client from which the client can estimate the clock offset and skew. In embodiments of the invention a free running clock at the client is provided with an estimation technique based on the time stamps from the IEEE 1588 PTP message exchange between the server and client clocks. The offset and skew from the estimation process can be combined with the local free running clock to give a synchronized local clock which is an accurate image of the master clock.

Method for realizing accurate time synchronization by utilizing IEEE1588 protocol

Abstract: The invention discloses a method for realizing accurate time synchronization by utilizing an IEEE1588 protocol, comprising the following steps: a) a Sync message is transmitted to a slave clock by a master clock, a transmission timestamp TM1 and a receiving timestamp TS1 of the message are acquired by the slave clock; b) a Delay_Req message is transmitted to the master clock by the slave clock, and a transmission timestamp TM2 and a receiving timestamp TS2 of the message are acquired by the slave clock; c) transmission delay and time offset are calculated by the slave clock according to the timestamp; and d) the calculated Offset is corrected in a fixed adjustment frequency in the correction time by the slave clock. The invention realizes accurate time synchronization, calculates time offset and self-compensate through the slave time clock in a packet based network, and leads the slave clock to lock the master clock whether in clock frequency or on the clock time in a shorter time, and occupies little hardware resources.

The space optical clocks project: Development of high-performance transportable and breadboard optical clocks and advanced subsystems

Abstract: The use of ultra-precise optical clocks in space (“master clocks”) will allow for a range of new applications in the fields of fundamental physics (tests of Einstein's theory of General Relativity, time and frequency metrology by means of the comparison of distant terrestrial clocks), geophysics (mapping of the gravitational potential of Earth), and astronomy (providing local oscillators for radio ranging and interferometry in space). Within the ELIPS-3 program of ESA, the “Space Optical Clocks” (SOC) project aims to install and to operate an optical lattice clock on the ISS towards the end of this decade, as a natural follow-on to the ACES mission, improving its performance by at least one order of magnitude. The payload is planned to include an optical lattice clock, as well as a frequency comb, a microwave link, and an optical link for comparisons of the ISS clock with ground clocks located in several countries and continents. Undertaking a necessary step towards optical clocks in space, the EU-FP7-SPACE-2010-1 project no. 263500 (SOC2) (2011–2015) aims at two “engineering confidence“, accurate transportable lattice optical clock demonstrators having relative frequency instability below 1×10−15 at 1 s integration time and relative inaccuracy below 5×10−17. This goal performance is about 2 and 1 orders better in instability and inaccuracy, respectively, than today's best transportable clocks. The devices will be based on trapped neutral ytterbium and strontium atoms. One device will be a breadboard. The two systems will be validated in laboratory environments and their performance will be established by comparison with laboratory optical clocks and primary frequency standards. In order to achieve the goals, SOC2 will develop the necessary laser systems - adapted in terms of power, linewidth, frequency stability, long-term reliability, and accuracy. Novel solutions with reduced space, power and mass requirements will be implemented. Some of the laser systems will be developed towards particularly high compactness and robustness levels. Also, the project will validate crucial laser components in relevant environments. In this paper we present the project and the results achieved during the first year.

Distributed robust clock synchronization

Abstract: Technology is provided for synchronization of clock information between networked devices. One or more of the devices may include one or more applications needed access to data and a common time reference between devices. In one embodiment, the devices have applications utilizing data shared in a network environment with other devices, as well as having a reference to a local clock signal on each device. A device may have a layer of code between the operating system and software applications that processes the data and maintains a remote clock reference for one or more of the other devices on the network.

Network and method for implementing a high-availability grand master clock

Abstract: In a network based on IEEE 1588, comprising a plurality of nodes (201, 501) and a plurality of connections where each connection connects at least two nodes to allow communication between nodes including the exchange of messages according to a network protocol, the the synchronization of IEEE 1588 is improved by allowing multiple grandmaster clocks (701) to operate simultaneously in the system. Thus, the re-election protocol of IEEE 1588 is made obsolete. For this, a multitude of nodes form a subsystem implementing a high-availability grand master clock (301) according to the IEEE 1588 Standard, wherein the subsystem is configured to tolerate the failure of at least one of said nodes forming said subsystem. Bi-directional communication link (401) are configured for physically connecting a IEEE 1588 Master clocks (201) and/or IEEE 1588 Slave clocks (201) to the subsystem implementing a high-availability grand master clock (301).

Synchronization in computer network

Abstract: A method, apparatus, and computer program product for operating a network node of a computer network is provided. According to an embodiment, the network node of a first synchronization island detects that at least one communication port of the network node is connected to a network node of a second synchronization island, wherein the first synchronization island and the second synchronization island are synchronized to different master clocks; acquires an announce message from the communication port connected to the second synchronization island, the announce message comprising operational parameters of a master clock of the second synchronization island, wherein the operational parameters comprise a priority parameter representing priority of the master clock of the second synchronization island; and overwrites automatically the priority parameter of the acquired announce message by a new priority parameter that indicates that the priority of the master clock of the second synchronization island is lower than the priority of the at least one master clock of the first synchronization island.

Precision timing in ocean sensor systems

Abstract: This paper discusses the use of the IEEE 1588 standard in ocean observatories. The performance result of prototype implementations of this standard in an Ethernet Marine Sensor Network (MSN) is presented. The performance tests emulate an underwater-cabled observatory with a Master Clock synchronized with GPS, located in an on-shore station, and with underwater instruments requiring high-precision PPS (pulse s−1) signals for synchronization purposes. These signals will be provided to the underwater station by an IEEE 1588 GPS Emulator connected to the observatory's Local Area Network (LAN). The experimental setup emulates the underwater-cabled observatory OBSEA where this technology will be installed due to synchronization requirements of marine instruments such as ocean bottom seismometers.

Method and system for clock offset and skew estimation

Abstract: This invention relates to methods and devices for clock offset and skew estimation. The invention has particular application in the alignment of slave clocks to a master clock. In embodiments of the invention, the slave clock employs an independent free running clock and a recursive estimation technique to estimate the clock offset and clock skew between the slave and master clocks. The slave can then use the offset and skew to correct the free running clock to reflect an accurate image of the master clock.

Time synchronization method and system for synchronous messages of IEEE1588 (Precision Time Protocol) master-slave clocks of intelligent transformer substation

Abstract: The invention discloses a time synchronization method and a time synchronization system for synchronous messages of IEEE1588 master-slave clocks of an intelligent transformer substation. The method comprises the following steps of: establishing a master clock synchronous message, and sending the timestamp t1 of the sending moment of the message to the clock in a broadcasting manner; recording a receiving moment t2 of the master clock synchronous message; recording an absolute receiving moment TT2 when the master clock synchronous message is received by a slave clock; establishing a slave clock responding message, sending the slave clock responding message to the master clock in a peer-to-peer manner, and recording the timestamp t3 of the sending moment of the message; recording an absolute sending moment TT3 when the slave clock sends the clock responding message; recording an acquiring moment t4 when the master clock acquires the message; calculating a time deviation, and calculating asymmetry errors according to the timestamp t1, the absolute receiving moment TT2, the absolute sending moment TT3 and the acquiring moment t4; and carrying out time correction on the slave clock by the time deviation and the asymmetry errors. According to the time synchronization method and the time synchronization system for synchronous messages of IEEE1588 master-slave clocks of the intelligent transformer substation, the influences of the asymmetry errors can be eliminated, and the time synchronization precision of the master-slave clocks is improved.

Method and apparatus for synchronizing hearing instruments via wireless communication

Abstract: A hearing assistance system including a hearing instrument designated as a master device and at least another hearing instrument designated as a slave device. The master device is communicatively coupled to the slave device via a wireless link. The master device has a master clock and generates master time stamps for specified events timed by the master clock. The master time stamps are sent to the slave device via the wireless link. The slave device has a slave clock and generates slave time stamps for specified events timed by the slave clock. The slave clock is adjusted for synchronization to the master clock using the master time stamps and the slave time stamps.

Method, apparatus and system for time distribution in a telecommunications network

Abstract: The invention is directed to a clock module and method for distributing a time reference to at least one clock in a packet-switched network. The clock module includes a slave port, a master port and a local clock. The method comprises the steps of receiving a first synchronization packet at the slave port, the first synchronization packet comprising a first master clock timestamp and generating at least one internal signal comprising the first master clock timestamp. The method also includes the steps of transmitting the at least one internal signal to the master port and receiving the at least one internal signal at the master port. Then a method includes determining the internal propagation time of the signal through the clock module and generating a second synchronization packet at the master port comprising a second master clock timestamp, the second master clock timestamp comprising the sum of the first master clock timestamp and the internal propagation time. Finally, the second synchronization packet is sent to at least one other clock in the packet-switched network.

Ring based precise time data network clock phase adjustments

Abstract: Clock phase errors are detected and adjusted in a network with loop back connections for clock signals. In one embodiment, a method is performed in a ring network with slave clock nodes. A timing packet is sent from the master clock node to a first slave clock node of the ring. A timing packet is received from a last slave clock node of the ring. A phase alignment offset is determined by comparing a recovered time from the received timing packet with the time of the master clock node local clock and a phase correction value is determined for the slave clock nodes based on the determined phase alignment offset. A phase correction packet including the phase correction value is then sent from the master clock node to at least one of the slave clock nodes.

Performance evaluation of PTPd, a IEEE 1588 implementation, on the x86 Linux platform for typical application scenarios

Abstract: The paper introduces the results of performance evaluation of IEEE 1588 Clock Synchronization technology implementation on the x86 (Intel) Linux platform. First, the typical application scenarios of IEEE 1588 in modern distributed measurement systems are listed, and based on that test systems are derived for testing with different configurations. These test systems are 1) a full software implementation in which no hardware elements support IEEE 1588, 2) a partial IEEE 1588 aware system in which end nodes synchronizing clocks support hardware time stamping but network elements do not, and 3) a full IEEE 1588 aware solution in which both end nodes and network elements support the standard. The hardware assisted PTP implementation utilized for evaluation has been developed by the authors of the paper, and available from http://home.mit.bme.hu/~khazy/ptpd/. The hardware assisted implementation is based on the Linux operating kernel infrastructure specifically developed for high precision network time keeping available from the kernel version of 2.6.30, and uses Network Interface Cards with IEEE 1588 hardware time stamping available on the market. The initial results show that clock accuracy (master-slave clock difference) less than one microsecond is achievable with using a full IEEE 1588 implementation even in the case of high network traffic and slave node (a node that synchronizes its clock to a master clock) load in standard Linux. The paper also details how the implementation of the clock servo realized by fixed point arithmetic computations (quantization) effect the achievable clock accuracy and proposes enhancements to the current solution.

Method, device and system for clock synchronization

Abstract: A method, a device and a system for clock synchronization are provided. The method includes: under a first transfer mode, generating a first receiving timestamp by using a first link, and acquiring a first transmitting timestamp of a master clock device; under a second transfer mode, generating a second transmitting timestamp by using the first link, and acquiring a second receiving timestamp of the master clock device; and acquiring a time difference to the master clock device according to the first receiving timestamp, the first transmitting timestamp, the second transmitting timestamp and the second receiving timestamp, and realizing a clock synchronization with the master clock device by using the time difference. A slave clock device and a master clock device are provided in the embodiments of the present invention, as well as a system for clock synchronization.

Method and device for synchronizing clocks

Abstract: The invention discloses a method and a device for synchronizing clocks. The method comprises the following steps of: calculating frequency drift and time migration between a local clock and a master clock; calibrating the local clock by using the frequency drift, and calibrating second pulse signals by using the time migration; and synchronizing the time of work clocks and time stamp modules in physical layer chips by using TOD (time of date) of the calibrated local clock, the calibrated second pulse signals and the rising edge of the calibrated second pulse signals. According to the method and the device, the problem of low synchronization accuracy caused by nondeterminacy of network link delay introduced by the physical layer chips and asymmetry of duplex paths in the prior art is solved, and the time of a plurality of physical layer chips and the master clock is synchronized.

Method for synchronizing clocks in nodes of a vehicle network and node designed to perform the method

Abstract: A method for synchronizing clocks in nodes of a vehicle network of a motor vehicle corrects a time difference between a master clock and a slave clock, taking into account transmission delay for a message between a master node and a slave node At least for a first synchronization of the master clock to a slave clock after the nodes of the vehicle network are started up, a default transmission delay in the slave node is used to correct the time difference, and/or the slave node sending out a Delay Request message, and recording in the master node the time at which Delay Request message is received and the master node sending the time, as a Delay Response message, back to the slave node In the slave node, the transmission delay for a message between the master node and the slave node is determined

Time and frequency transfer in optical fibers

Abstract: The development towards more services in the digital domain, based on computers and server logs at different locations and in different networks, increases the need for high precision time indication. Even though GPS can support this with sufficient precision, many users do not have access to outdoor antennas. Furthermore, there is vulnerability in the weak radio-transmission from the satellites (NSTAC) as well as the dependence on the continuous replacement of old and outdated satellites (Chaplain). Therefore, alternative systems to support precise time are needed. Standardization of time transfer of a master clock is done for example in the IRIG system, but this one-way time transfer system do not take variations in transfer time into account, mainly because it is supposed to work on short distances (IRIG). In additional efforts to meet this request, several time and frequency transfer methods using optical fibers have been developed or are under development, using dedicated fibers (Kihara; Jefferts; Ebenhag2008; Kefelian), dedicated capacity in existing fiber networks (Calhoun) or already existing synchronization in active fiber networks (Emardson, Ebenhag2010a). A similarity of all these techniques is the need for two-way communication to compensate for the inevitable variations of propagation time, such as variation of temperature and mechanical stress along the transmission path. A two-way connection may however be undesirable when many users are connected in one network, or when user privacy is requested. As an alternative, a one-way transmission over fiber optic wavelength division multiplexing network with detection of variation in propagation time has been presented (Ebenhag2010b, Hanssen). The general conception of fiber optic communication is the transmission of digital data from one user to another, and through recovery of the phase variation of the bit-slots after reception, the exact time it has taken to transfer the data is of low importance. The individual packets of the data may even follow different paths with different propagation time, and still be interpreted correctly at the user end. Physical effects such as noise, dispersion and polarization dependence are important, but as long as each bit can be detected correctly, slow variations in propagation time do not affect the communication. When the fiber is used to transmit time or frequency however, the physical properties of the transmission link become very important. Even though time and frequency may appear as two faces of the same parameter, there are differences in the requirement of a transmission link. For time transfer, any variations in the delay through the link must be compensated for, either in a real time compensator or through post processing. For frequency transfer, the frequency shift caused by the rapidity of a change in the fiber delay must be handled.

Methods and systems for high frequency clock distribution

Abstract: In accordance with some embodiments, a method for high frequency clock distribution in a VLSI system includes splitting an original master clock signal into one or more pairs of lower-frequency sub-clocks for a destination in the VLSI system, distributing each lower-frequency sub-clock of the one or more pairs of lower-frequency sub-clocks to a corresponding channel coupled to the destination, and reconstructing a reference master clock signal at the destination from the one or more pairs of lower-frequency sub-clocks, wherein the reconstructed reference master clock signal replicates the original master clock signal.

Time synchronization method and system for multi-core system

Abstract: The invention discloses a multi-core system time synchronization method and a system thereof; the time synchronization method comprises the following steps: A, establishing at least a clock synchronization domain, and distributing the cores respectively into each lock synchronization domain; B, selecting the core with the minimum load as the master clock synchronization source in each clock synchronous domain, and taking the clock synchronization domain having the master clock synchronization source with the minimum load among all the master clock synchronization sources as the master clock synchronization domain, and taking the other clock synchronization domains as the slave clock synchronization domains; C, after the master clock synchronization domain sends synchronization error detection information to each slave clock synchronization domain, calculating the time deviation value between each slave clock synchronization domain and the master clock synchronization domain; D, when the time deviation value is greater than the permitted deviation value, the master clock synchronization domain calculates the time adjustment quantity of each slave clock synchronization domain and releases the time adjustment quantity to each slave clock synchronization domain, then each slave clock synchronization domain makes adjustment based on the corresponding time adjustment quantity. The invention effectively solves the time synchronization problem of the multi-core system.

Deterministic synchronization for transmitting signals between different clock domains

Abstract: One embodiment sets forth a technique for deterministic synchronization of signals that are transmitted between different clock domains. The relative phase difference between a source clock domain and a destination clock domain is characterized and the source clock and/or the destination clock are delayed as needed to generate phase-shifted versions of the source and destination clocks for use during a deterministic operating mode. The phase-shifted versions of the source and destination clocks are non-overlapping, meaning that the rising edge of the destination clock does not occur when the source clock is asserted. The non-overlapping source and destination clocks are used by a deterministic synchronization unit to ensure that signals being transmitting from the source clock domain to the destination clock domain are not sampled within a metastability window.

System for adaptive sampled medical signal interpolative reconstruction for use in patient monitoring

Abstract: A patient medical signal processing system adaptively reconstructs a medical signal sampled using a varying sampling rate The system includes an input processor and a signal processor The input processor receives first data and second data The first data represents a first portion of a medical signal derived by sampling at a first sampling rate and the second data represents a second portion of the medical signal derived by sampling at a second sampling rate The first and the second sampling rates are different and comprise a master clock rate or an integer division of the master clock rate A signal processor provides a reconstructed sampled medical signal by, interpolating the second data to provide third data at the first sampling rate and combining the first data and the third data to provide the reconstructed sampled medical signal

Data communication with interventional instruments

Abstract: The invention relates to a data communication system (100) and a method that can particularly be applied for communicating data from a medical instrument like a catheter or a guide-wire via a high-speedlink (101). The system (100) comprises (in-vivo) a slave component (150) with a controllable slave clock (153) and a transmitter (151) for transmitting a data signal (ds) that is clocked by the slave clock signal (clk). Moreover, it comprises (ex-vivo) a master component (110) with a clock controller (114,115,116) that receives a master clock signal (ref_clk) and the data signal (ds) and that generates a clock control signal (ccs) for adjusting the slave clock (153) to the master clock (113). The slave clock (153) may thus be realized with low space and energy requirements, e.g. by a voltage controlled oscillator (VCO). Moreover, the link (101) via which the data signal (ds) and the clock control signal (ccs) are exchanged may be realized by just two signal wires.

Method of catv cable same-frequency time division duplex data transmission

Abstract: Method of bidirectional Time Division Duplex (TDD) data transmission over the same RF frequency ranges of a CATV cable system. The system's slave modem clocks are time synchronized to the master clock of a master modem. The master-to-slave signal propagation times are determined and used to precisely schedule transmissions with de-minimis guard times. The frequency range may be chosen to be in the high frequency CATV range around 1 GHz to maximize backward compatibility with legacy systems, and this frequency may in turn be subdivided into multiple frequencies. In some embodiments, the CATV cable tree may be further partitioned into multiple TDD domains, and multiple local master modems, connected by a special-use optical fiber, may communicate with multiple local slave modems. The system may use MAP allocation schemes that may frequently reallocate TDD time slots and frequencies according to current or projected slave modem data needs.

Baseband signal processing SOC chip of multi-protocol UHF RFID reader

Abstract: The invention discloses a baseband signal processing SOC chip of a multi-protocol UHF RFID reader, comprising a CPU module, a bus in a chip, a storage interface, a DAC output channel, an ADC input channel, a multi-protocol processing unit of an UHF RFID hardware, a man-machine interface, a high-speed communication interface, a low-speed communication interface, a timer module, a JTAG interface module and a master clock module; a high-speed system bus and a low-speed peripheral bus are connected together through a DMA controller and a bus bridge, and each bus is provided with an address decoder and a bus arbitrator; the CPU module, the storage interface, the man-machine interface, the multi-protocol processing unit, the JTAG interface module and the high-speed communication interface are connected with the high-speed system bus; and the low-speed communication interface, the timer module and the master clock module are connected with the low speed peripheral bus. The invention can conveniently realize a handheld UHF RFID reader with high integrated level, low cost, low power consumption and high generality.

Method and device for time synchronization convergence based on precision time protocol

Abstract: The invention discloses a method and a device for time synchronization convergence based on the precision time protocol. The method comprises the followings steps of: interacting a synchronization message with a grandmaster clock node at each passive port by a slave clock node, performing time synchronization calculation, and establishing and maintaining the alternative time information corresponding to the passive port according to a result of the time synchronization calculation; when the slave clock node detects that an upstream clock synchronization network of a slave port or any passive port undergoes topology change, triggering BMC (Best Master Clock) computation, determining a port with the optimal clock priority information according to a BMC computation result, if the port with the optimal clock priority information is a passive port, switching the passive port into a slave port, and performing time synchronization processing on a local clock according to the alternative time information corresponding to the passive port. With the method and the device, the out-of-step time of the slave clock node can be reduced during the topology change of the network.

Method for improving clock accuracy based on seamless redundancy ring network and node

Abstract: The invention relates to a method for improving clock accuracy based on a seamless redundancy ring network and a node. The method comprises the following steps of: receiving synchronous clock information sent by an adjacent node or a master clock by the node in the seamless redundant looped network, determining lingering time of the received synchronous clock information in the node, wherein the lingering time is time length of the synchronous clock information between a time point from input to an inlet port and a time point from output to an outlet port; correcting the received synchronous clock information according to the determined lingering time; forwarding the corrected synchronous clock information to the adjacent node by a ring port if the output port is the ring port; and forwarding the corrected synchronous clock information to the clock by an external port if the output port is the external port, so that a slave clock performs clock synchronization according to the synchronous clock information. By the technical scheme provided by the invention, the problem of large synchronous error between the master clock and the slave clock is solved.