Showing papers on "Master clock published in 2013"

Peripheral Circadian Oscillators in Mammals

Abstract: Although circadian rhythms in mammalian physiology and behavior are dependent upon a biological clock in the suprachiasmatic nuclei (SCN) of the hypothalamus, the molecular mechanism of this clock is in fact cell autonomous and conserved in nearly all cells of the body. Thus, the SCN serves in part as a "master clock," synchronizing "slave" clocks in peripheral tissues, and in part directly orchestrates circadian physiology. In this chapter, we first consider the detailed mechanism of peripheral clocks as compared to clocks in the SCN and how mechanistic differences facilitate their functions. Next, we discuss the different mechanisms by which peripheral tissues can be entrained to the SCN and to the environment. Finally, we look directly at how peripheral oscillators control circadian physiology in cells and tissues.

Circadian Clocks, Food Intake, and Metabolism

Abstract: Circadian rhythmicity that has been shaped by evolution over millions of years generates an internal timing controlling the sleep-wake and metabolism cycles. The daily variations between sleep/fasting/catabolism and wakefulness/feeding/anabolism are coordinated by a master hypothalamic clock, mainly reset by ambient light. Secondary clocks, including liver and adipose tissue, are normally synchronized by the master clock, but they are also sensitive to feeding time, especially when meals take place during the usual resting period. Cellular metabolism and circadian clocks are tightly interconnected at the molecular levels. Although the suprachiasmatic clock is not shifted by mealtime under light-dark conditions, nutritional cues can feedback onto it and modulate its function under hypo- and hypercaloric (high-fat) conditions. Food-related reward cues are other modulators of the master clock. Circadian disturbances (e.g., desynchronization induced by shift work or chronic jet lag) are frequently associated with metabolic dysfunctions (chronobesity) and vice versa. Pharmacological tools and natural synchronizers (i.e., light and mealtime) can be useful as chronotherapeutic treatments to limit the occurrence of metabolic risk factors.

Clock synchronization using multiple network paths

Abstract: In a network device communicatively coupled to a master clock via a plurality of different communication paths, a clock synchronization module is configured to determine a plurality of path time data sets corresponding to the plurality of different communication paths based on signals received from the master clock via the plurality of different communication paths between the network device and the master clock. A clock module is configured to determine a time of day as a function of the plurality of path time data sets.

Method and devices for frequency distribution

Abstract: This invention relates to methods and devices for frequency distribution based on, for example, the IEEE 1588 Precision Time Protocol (PTP). Packet delay variation (PDV) is a direct contributor to the noise in the recovered clock and various techniques have been proposed to mitigate its effects. Embodiments of the invention provide a mechanism to directly measure and remove PDV effects in the clock recovery mechanism at a slave clock. One particular embodiment provides a clock recovery mechanism including a phase-locked loop (PLL) with a PDV compensation feature built-in. An aim of the invention is to enable a slave clock to recover the master clock to a higher quality as if the communication path between master and slave is free of PDV. This technique may allow a packet network to provide clock synchronization services to the same level as time division multiplexing (TDM) networks and Global Positioning System (GPS).

Multi-path Time Protocols

Abstract: Over the last few years, packet based networks have become the common transport for applications requiring clock synchronization. Classical time distribution protocols are run between a master clock and a slave clock using a single network path between the two clocks. A recently introduced approach called Slave Diversity uses multiple paths between a master-slave pair to reduce the effect of temporal congestion or errors in a specific path. The current paper applies the multi-path approach to the most widely-used packet based time protocols, PTP and NTP. We introduce extensions to the PTP and NTP standards called Multi-Path PTP (MPPTP) and Multi-Path NTP (MPNTP), respectively, and describe their application over various transport protocols. Our experimental evaluation shows that a large number of paths can be utilized when running the multi-path protocols over the internet, and thus that our multi-path approach can be effectively deployed over existing IP networks.

A data processing apparatus and method for communicating between a master device and an asynchronous slave device via an interface

Abstract: A data processing apparatus and method are provided for communicating between a master device operating from a master clock signal and a slave device operating from a slave clock signal asynchronous to the master clock signal. An interface provides a communication path for the transfer of packets between the master device and the slave device, with the master device initiating transactions where each transaction comprises a plurality of transfers including a master transfer from the master device to the slave device and a slave transfer from the slave device to the master device. A slave clock replica generator associated with the master device generates a slave clock replica that controls timing of transmission of packets by the master device over the interface and timing of reception by the master device of packets sent by the slave device over the interface. In response to a predetermined trigger event, a sync request transfer is issued over the interface from the master device to the slave device, the sync request transfer having a property identifiable by the slave device irrespective of whether the sync request transfer is synchronised with the slave clock signal. In response to a detection of the sync request transfer, the slave device issues over the interface a sync response transfer indicative of at least a frequency of the slave clock signal, and the slave clock replica generator determines at least the frequency of the slave clock replica from that sync response transfer. In addition, the slave clock replica generator references at least a portion of the packet of selected slave transfers in order to determine a phase of the slave clock replica, said at least a portion of the packet containing at least one transition between a first value and a second, different, value. By this approach, determination of the phase of the slave clock replica is decoupled from determination of the frequency of the slave clock replica.

Precision timing using a modified synchronization operation

Abstract: A master node is configured to receive, from a slave node, a request to perform a modified two-step synchronization (sync) operation in a manner that precludes transmitting a follow-up packet; generate a sync packet in a manner that includes information associated with a previous time that a prior sync packet was transmitted to the slave node; transmit the sync packet to the slave node; receive, from the slave node, a delay request packet; transmit, to the slave node, a delay response packet, where the delay response packet stores information associated with another time at which the delay request packet was received, and where transmitting the delay response packet enables the slave node to calibrate a clock, hosted by the slave node, to a master clock, hosted by the master node, based on the previous time and the other time.

Hardware Assisted Clock Synchronization for Real-Time Sensor Networks

Abstract: Time synchronization in wireless sensor networks is important for event ordering and efficient communication scheduling. In this paper, we introduce an external hardwarebased clock tuning circuit that can be used to improve synchronization and significantly reduce clock drift over long periods of time without waking up the host MCU. This is accomplished through two main hardware sub-systems. First, we improve upon the circuit presented in [1] that synchronizes clocks using the ambient magnetic fields emitted from power lines. The new circuit uses an electric field front-end as opposed to the original magnetic-field sensor, which makes the design more compact, lower-power, lower-cost, exhibit less jitter and improves robustness to noise generated by nearby appliances. Second, we present a low-cost hardware tuning circuit that can be used to continuously trim a micro-controller's low-power clock at runtime. Most time synchronization approaches require a CPU to periodically adjust internal counters to accommodate for clock drift. Periodic discrete updates can introduce interpolation errors as compared to continuous update approaches and they require the CPU to expend energy during these wake up periods. Our hardware-based external clock tuning circuit allows the main CPU to remain in a deep-sleep mode for extended periods while an external circuit compensates for clock drift. We show that our new synchronization circuit consumes 60% less power than the original design and is able to correct clock drift rates to within 0.01 ppm without power hungry and expensive precision clocks.

Oscillatory activity, phase differences, and phase resetting in the inferior olivary nucleus

Abstract: The generation of temporal patterns is one of the most fascinating functions of the brain. Unlike the response to external stimuli, temporal patterns are generated within the system and recalled for a specific use. To generate temporal patterns one needs a timing machine, a 'master clock' that determines the temporal framework within which temporal patterns can be generated and implemented. Here we present the concept that in this putative 'master clock', phase and frequency interact to generate temporal patterns. We define the requirements for a neuronal ‘master clock’ to be both reliable and versatile. We introduce this concept within the inferior olive nucleus, which, at least by some scientists, is regarded as the source of timing for cerebellar function. We review the basic properties of the subthreshold oscillation recorded from olivary neurons, analyze the phase relationships between neurons, and demonstrate that the phase and onset of oscillation is tightly controlled by synaptic input. These properties endowed the olivary nucleus with the ability to act as a 'master clock'.

Methods and apparatus for precision time stamping

Abstract: In a network device, apparatus and methods perform precision time stamping. A time agent receives a master pace signal corresponding to a time representation based on a master real time clock in a master clock domain. A time accumulator accumulates time units one fill quantum at a time based on the master pace signal. The time accumulator decreases the accumulated time units by a leak quantum according to a local clock signal running at a higher frequency than the master pace signal. Correction logic periodically generates, at a granularity corresponding to the frequency of the local clock signal, an updated time representation in a target clock domain based on a residual number of time units in the time accumulator before depositing an additional fill quantum of time units in the time accumulator.

Clock synchronization in the presence of security threats

Abstract: In a network device communicatively coupled to a master clock via a plurality of different communication paths, a clock synchronization module is configured to determine a plurality of path time data sets corresponding to the plurality of different communication paths based on signals received from the master clock via the plurality of different communication paths between the network device and the master clock. A clock module is configured to determine that at least one of the plurality of path time data sets is inaccurate based on accuracy metrics corresponding to the plurality of path time data sets, and determine a time of day as a function of a remainder of one or more path time data sets, in the plurality of path time data sets, not determined to be inaccurate. The device may detect and/or mitigate “man-in-the-middle” attacks aimed at a clock synchronization protocol.

Distributed clock generator for synchronous SoC using ADPLL network

Abstract: This paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation offers flexibility and efficient synchronization control suitable for use in synchronous SoCs.

Analysis of the molecular pathophysiology of sleep disorders relevant to a disturbed biological clock

Abstract: Genetic studies have revealed several clock gene variations/mutations involved in the manifestation of sleep disorders or interindividual differences in sleep-wake patterns, but only part of the genetic risk can be explained by the gene variations/mutations identified to date. Recent progress in research into circadian rhythm generation has provided efficient tools for eliciting the molecular basis of clock-relevant sleep disorders, complementing traditional genetic analysis. While the human master clock resides in the suprachiasmatic nucleus of the hypothalamus (central clock), peripheral tissue cells also generate self-sustained circadian oscillations of clock gene expression (peripheral clock), enabling estimation of individual human clock properties through a single collection of skin fibroblasts or venous blood cells. Some of the established cell lines exhibit autonomous circadian oscillations of clock gene expression, and introduction of clock gene variations into these cell lines by gene targeting makes it possible to investigate changes in the circadian phenotype induced by these variations/mutations without the need for generating transgenic animals. Estimation of human clock properties using peripheral tissue cells, in addition to genetic analysis, will facilitate comprehensive explication of the genetic risk of a variety of disorders relevant to biological clock disturbances, including sleep disorders, mood disorders, and metabolic diseases.

Hardware assisted COTS IEEE 1588 solution for x86 Linux and its performance evaluation

Abstract: There exist large number of professional IEEE 1588 compatible components on the embedded system market from various suppliers. However, it is an open question if it is possible to build sub 1 microsecond precision, low cost IEEE 1588v2 compatible master clock and client solution using commercial off-the shelf (COTS) components, like standard x86 architecture PCs, regular network interface cards, and GPS receivers. In the paper we present our COTS solution using such hardware components. The software running on the COTS hardware is based on standard, non real-time Linux, the linuxptp IEEE 1588 implementation, and some other software developed for the project by us. We also present the performance evaluation of the developed solution, in which we compare the performance of the solution to professional equipment. The outcome of the evaluation shows that the developed solution is capable of providing sub 1 microsecond precision from the reference clock to the client.

Method for precisely synchronizing time of industrial wireless network on basis of prediction and compensation

Abstract: The invention relates to technologies for industrial wireless networks, in particular to a method for precisely synchronizing time of an industrial wireless network on the basis of prediction and compensation. The method includes constructing the factory-automation-oriented industrial wireless network into a star network on the basis of an IEEE (institute of electrical and electronics engineers) 802.11 single-hop basic service set (BBS) structure; setting a master clock and slave clocks according to types and functions of nodes in the industrial wireless network; enabling a master clock side and slave clock sides to interact with one another via two-way timestamp information and computing a time deviation value of a current synchronizing cycle; predicting a time deviation value of a next synchronizing cycle by the aid of the time deviation value of the current synchronizing cycle; compensating clock drift by the aid of the predicted time deviation value of the next synchronizing cycle and correcting the clocks. The method has the advantages that the method is implemented on the premise that application requirements of factory automation are sufficiently considered, so that high time synchronization precision can be realized by the aid of few wireless communication resources, and purposes of high precision, high efficiency, low expenditure and easiness in implementation can be achieved.

Apparatus and method for enabling a passive optical network on supporting time synchronization

Abstract: An apparatus for enabling a passive optical network (PON) having an OLT and at least one ONU on supporting time synchronization is disclosed. The apparatus comprises a timestamp correction module configured to make at least one network delay between the OLT and the at least one ONU of the PON equivalent to an equivalent path delay, wherein the timestamp correction module, through the PON, makes the at least one ONU responsible for modifying the timestamp in at least one PTP packet from the OLT, so that a slave clock at the backend of the at least one ONU is equivalent to synchronizing with a virtual master clock. The disclosure computes and corrects PTP commands so that the PTP clock at an ONU's backend may synchronize precisely with the master clock at an OLT's front end.

Pluggable packet master clock

Abstract: Apparatus for providing timing information, the apparatus comprising: a primary reference time clock (PRTC) that provides a reference time of day (ToD) and a reference frequency; a packet master clock that receives the ToD and reference frequency and is configured to distribute timing to a slave clock in accordance with a timing over packet procedure responsive to the ToD and the reference frequency; and a housing that houses the PRTC and packet master clock which may be plugged into a conventional small form factor (SFP) compliant cage to connect the packet master clock to a packet switched network (PSN).

Quantitative Assessment of Fault Tolerant Precision Timing for Electricity Substations

Abstract: Advanced substation applications, such as synchrophasors and IEC 61850-9-2 sampled value process buses, depend upon highly accurate synchronizing signals for correct operation. The IEEE 1588 Precision Timing Protocol (PTP) is the recommended means of providing precise timing for future substations. This paper presents a quantitative assessment of PTP reliability using fault tree analysis. Two network topologies are proposed that use grandmaster clocks with dual network connections and take advantage of the best master clock algorithm (BMCA) from IEEE 1588. The cross-connected grandmaster topology doubles reliability, and the addition of a shared third grandmaster gives a nine-fold improvement over duplicated grandmasters. The performance of BMCA mediated handover of the grandmaster role during contingencies in the timing system was evaluated experimentally. The 1 μs performance requirement of sampled values and synchrophasors are met, even during network or GPS antenna outages. Slave clocks are shown to synchronize to the backup grandmaster in response to degraded performance or loss of the main grandmaster. Slave disturbances are less than 350 ns provided the grandmaster reference clocks are not offset from one another. A clear understanding of PTP reliability and the factors that affect availability will encourage the adoption of PTP for substation time synchronization.

Quantitative assessment of fault tolerant precision timing for electricity substations

Abstract: Advanced substation applications, such as synchrophasors and IEC 61850-9-2 sampled value process buses, depend upon highly accurate synchronizing signals for correct operation. The IEEE 1588 Precision Timing Protocol (PTP) is the recommended means of providing precise timing for future substations. This paper presents a quantitative assessment of PTP reliability using Fault Tree Analysis. Two network topologies are proposed that use grandmaster clocks with dual network connections and take advantage of the Best Master Clock Algorithm (BMCA) from IEEE 1588. The cross-connected grandmaster topology doubles reliability, and the addition of a shared third grandmaster gives a nine-fold improvement over duplicated grandmasters. The performance of BMCA mediated handover of the grandmaster role during contingencies in the timing system was evaluated experimentally. The 1 µs performance requirement of sampled values and synchrophasors are met, even during network or GPS antenna outages. Slave clocks are shown to synchronize to the backup grandmaster in response to degraded performance or loss of the main grandmaster. Slave disturbances are less than 350 ns provided the grandmaster reference clocks are not offset from one another. A clear understanding of PTP reliability and the factors that affect availability will encourage the adoption of PTP for substation time synchronization.

A method for detecting timing references affected by a change in path delay asymmetry between nodes in a communications network

Abstract: A method for detecting a timing reference affected by a change in path delay asymmetry in a communications network comprising a master node having a master clock and a plurality of slave nodes each having a respective slave clock is provided. The method comprises: determining that a first timing reference received by a first slave node indicates a time correction to its slave clock greater than a time correction threshold; determining whether one or more other slave nodes have received a timing reference indicating a time correction to their slave clock greater than a time correction threshold; and determining whether the first timing reference is affected by a change in path delay asymmetry based on the determining of whether one or more other slave nodes have received a timing reference indicating a time correction to their slave clock greater than a time correction threshold. Apparatus and a computer program for detecting a timing reference affected by a change in path delay asymmetry in a communications network are also provided.

Method and apparatus for controlling a harmonic rejection mixer

Abstract: In one embodiment, the present invention includes a method for receiving a radio frequency (RF) signal and mixing the RF signal with a master clock to obtain a mixed signal, cyclically rotating the mixed signal to each of N gain stages for at least one cycle of the master clock, and summing the outputs of the N gain stages to provide an output signal.

Method and devices for packet selection

Abstract: This invention relates to packet selection techniques that can be used in conjunction with a clock recovery mechanism to mitigate the effects of packet delay variation on timing messages exchanged over a packet network, particularly when seeking to synchronize the time of a clock in a slave device to that of a master clock. The packet selection techniques can assist in reducing the noise in the recovered clock signal at the slave device, allowing recovery to a higher quality. Embodiments of the invention provide techniques based on extracting timing packets that create a constant interval between the arrival of selected packets at the slave device and on extracting timing packets which are closest to making the interval between arrival of the selected packets equal to the interval between the departure of the packets.

Clock recovery in a packet based network

Abstract: A technique for facilitating clock recovery in a node of a packet-based network is disclosed. The node is synchronized with other nodes based on a master-slave clock mechanism. A list of backup master clock node is maintained for the node, which includes at least one backup master clock node for the node, and in response to occurrence of a synchronization related event, a master clock node of the node is switched from the current master clock node to a backup master clock node selected from the list. A master clock node reselection message is generated and transmitted to the switched backup master clock node for the switched backup master clock node to reselect its master clock node.

Implementation method, system and device for multi-clock synchronization technology hybrid networking

Abstract: The invention discloses an implementation method, system and device for multi-clock synchronization technology hybrid networking. A master clock and one or a plurality of slave clocks are arranged for a synchronization device which serves as a clock synchronization service provider and a clock synchronization service receiver simultaneously. The synchronization device sends clock source information to slave clocks on adjacent synchronization devices through the master clock, and receives the clock source information from master clocks on the adjacent synchronization devices through the slave clocks, wherein the adjacency of the synchronization devices means direct connection or connection of bridging networks which do not support the clock synchronization technology. The implementation method, system and device for the multi-clock synchronization technology hybrid networking can enable the precision time protocol (PTP) synchronization devices to switch and lock other clock sources normally when clock source failure occurs under the situation of physical clock technology and grouping clock technology hybrid networking, and the problem of the clock source switching failure under the situation of the hybrid networking is solved.

Synchronous on-chip clock controllers

Abstract: A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses.

Low Jitter Clock Generator for Multiple Lanes High Speed Data Transmitter

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

New algorithm for IEEE 1588 time synchronization under the presence of significant delay variation

Abstract: Time synchronization is one of the basic services in a distributed network as it enables a lot of services, for example synchronized measurements or timeslot-based access to shared communication media. The IEEE 1588 defines the precision time protocol (PTP) that aims to synchronize multiple slave clocks to a master clock by means of synchronization event messages. Unfortunately, the accuracy of time synchronization strongly depends on delay variations produced by the underlying telecom network. Such behavior represents a strong issue, particularly considering the network consisting of devices that are not IEEE 1588 capable. A conventional clock servo will not provide enough accurate level of synchronization in the case of considerable delay variation. We develop a novel time synchronization algorithm that is based on a generic statistical approach and explicitly takes into account the stochastic properties of delay of PTP messages. Numerical simulations show that this algorithm is effective for estimation of the time offset between master and slave reliably, even under significant delay variations.

Ultra-short term clock offset prediction for two-way satellite time synchronization

Abstract: Based on the principle of two way satellite time transfer, a time synchronization system with master-slave sturcture is established. In the system, slave sites compare their clock time with the master clock in turn. After one comparison, the slave clock offset is estimated and predicted until the next comparison period. In the paper, three clock offset prediction algorithms are discussed in detail. Their performance is evaluated and validated using measured clock offset data. The results show the linear fitting algorithm has an obvious good performance in ultra-short term prediction than quadratic polynomial method. And it's quite simple than grey system model prediction algorithm. The time synchronization system use the linear fitting algorithm for clock offset prediction in practice and has a good practical effect.

Electronic type transformer verifying unit based on IEEE1588 clock calibration mode

Abstract: The invention discloses an electronic type transformer verifying unit based on an IEEE1588 clock calibration mode and relates to calibration and detection of electric equipment. The device consists of an IEEE1588 Ethernet switch (1), an IEEE1588 clock (2), a standard voltage/current converter (3), a standard channel data acquisition unit (4), a synchronous pulse transmitting module (5), a detected channel data acquisition unit (6), a data processing unit (7) and a GPS (global positioning system) (8). The IEEE1588 clock (2) of the device not only can be used as a master clock, but also can be used as a slave clock in a calibration measurement and can also support two time calibration modes including ETE (end to end) and PTP (peer to peer); and the device is small in size and capable of meeting the on-site verifying demands.