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Showing papers on "Master clock published in 2014"


Journal Article
TL;DR: In this paper, a network of atomic clocks using non-local entangled states is proposed to achieve unprecedented stability and accuracy in time-keeping, as well as being secure against internal or external attack.
Abstract: A proposed network of atomic clocks—using non-local entangled states—could achieve unprecedented stability and accuracy in time-keeping, as well as being secure against internal or external attack.

247 citations


Journal ArticleDOI
TL;DR: It is shown that insulin-phosphatidylinositol 3-kinase (PI3K)-Forkhead box class O3 (FOXO3) signaling is required for circadian rhythmicity in the liver via regulation of Clock, and insulin, a major regulator of FOXO activity, regulates Clock levels in a PI3K- and FOXO3-dependent manner.

80 citations


Journal ArticleDOI
TL;DR: It is proposed that ubiquitination is a key element in a clock protein modification code that orchestrates clock mechanisms and circadian behavior over the daily cycle.
Abstract: Circadian rhythms, endogenous cycles of about 24 h in physiology, are generated by a master clock located in the suprachiasmatic nucleus of the hypothalamus and other clocks located in the brain and peripheral tissues. Circadian disruption is known to increase the incidence of various illnesses, such as mental disorders, metabolic syndrome and cancer. At the molecular level, periodicity is established by a set of clock genes via autoregulatory translation-transcription feedback loops. This clock mechanism is regulated by post-translational modifications such as phosphorylation and ubiquitination, which set the pace of the clock. Ubiquitination in particular has been found to regulate the stability of core clock components, but also other clock protein functions. Mutation of genes encoding ubiquitin ligases can cause either elongation or shortening of the endogenous circadian period. Recent research has also started to uncover roles for deubiquitination in the molecular clockwork. Here we review the role of the ubiquitin pathway in regulating the circadian clock and we propose that ubiquitination is a key element in a clock protein modification code that orchestrates clock mechanisms and circadian behavior over the daily cycle.

77 citations


Journal ArticleDOI
TL;DR: An ensemble of rubidium atomic fountain clocks has been put into operation at the US Naval Observatory (USNO) for more than two years and are included in the ensemble used to generate the USNO master clock as discussed by the authors.
Abstract: An ensemble of rubidium atomic fountain clocks has been put into operation at the US Naval Observatory (USNO). These fountains are used as continuous clocks in the manner of commercial caesium beams and hydrogen masers for the purpose of improved timing applications. Four fountains have been in operation for more than two years and are included in the ensemble used to generate the USNO master clock. Individual fountain performance is characterized by a white-frequency noise level below 2 × 10−13 and fractional-frequency stability routinely reaching the low 10−16 s. The highest performing pair of fountains exhibits stability consistent with each fountain integrating as white frequency noise, with Allan deviation surpassing 6 × 10−17 at 107 s, and with no relative drift between the fountains at the level of 7.5 × 10−19/day. As an ensemble, the fountains generate a timescale with white-frequency noise level of 1 × 10−13 and long-term frequency stability consistent with zero drift relative to the world's primary standards at 1 × 10−18/day. The rubidium fountains are reported to the BIPM as continuously running clocks, as opposed to secondary standards, the only cold-atom clocks so reported. Here we further characterize the performance of the individual fountains and the ensemble during the first two years in an operational environment, presenting the first look at long-term continuous behavior of fountain clocks.

39 citations


Patent
Eric John Spada1, Yongbum Kim1
05 Mar 2014
TL;DR: In this paper, a fault tolerant and redundant grand master clock scheme was proposed to reduce or eliminate precision time transition caused by a network link or device failure, where the primary and backup clocks may be concurrently operated.
Abstract: Fault tolerant and redundant grand master clock scheme may reduce or eliminate precision time transition caused by a network link or device failure. A primary synchronization message may be sent by a primary grandmaster clock and one or more backup synchronization message may be sent by respective backup grandmaster clocks. The primary and backup grandmaster clocks may be concurrently operated. The primary and backup synchronization messages may be sent to an end station over a network. The end station may derive a local clock based on one, some, or all of the received messages. The end station may or may not distinguish between the messages based on the clock source. The end station may validate messages received from a particular clock source.

37 citations


Proceedings ArticleDOI
23 Oct 2014
TL;DR: GFDM, a candidate waveform for the 5G PHY layer, is shown to be able to use the LTE master clock and the same time-frequency structure as employed in today's generation of cellular systems.
Abstract: The soft transition between generations of mobile communication systems is a desirable feature for telecommunication operators and device manufacturers. Looking to the past, clock compatibility between WCDMA and LTE allowed manufacturers to build inexpensive multi-standard devices. In this paper it is shown that GFDM, a candidate waveform for the 5G PHY layer, is able to use the LTE master clock and the same time-frequency structure as employed in today's generation of cellular systems. Two approaches for coexistence of 4G/5G waveforms are presented in the paper. The first GFDM setting is aligned with the LTE grid; in the other one GFDM acts as a secondary system to the primary LTE. The second approach introduces a new way of positioning subcarriers that further enhances the flexibility of GFDM. In addition, the paper also considers low latency aspects for autonomous and human controlled device communication in future application scenarios.

30 citations


Patent
James Aweya1
11 Dec 2014
TL;DR: In this paper, the authors proposed a simple linear approximation technique and a Kalman filter-based technique for estimating offset and skew of the slave clock, which has particular application in the alignment of slave clocks to a master clock and dealing with packet delay variations.
Abstract: This invention relates to methods and devices for time transfer. The invention has particular application in the alignment of slave clocks to a master clock and dealing with packet delay variations. In embodiments of the invention, the slave clock uses the residence times measured by end-to-end transparent clocks to compensate for clock synchronization errors that arise due to variability in message transfer delays. Embodiments provide a simple linear approximation technique and a Kalman filter-based technique for estimating offset and skew of the slave clock.

28 citations


Patent
04 Aug 2014
TL;DR: In this paper, a multicast video stream is forwarded to an array of a plurality of display modules movably attached to a modular display, and a video display of the first display module is updated according to the video display data that is extracted from the stream, wherein the updating is synchronized to a master clock of the modular display.
Abstract: Aspects of the subject disclosure may include, for example, a method including receiving, by a system comprising a processor, a multicast video stream directed to an array of a plurality of display modules movably attached to a modular display, extracting, by the system, video display data from the multicast video stream according to a location within the array of a first display module of the plurality of display modules, and updating, by the system, a video display of the first display module according to the video display data that is extracted from the multicast video stream, wherein the updating is synchronized to a master clock of the modular display. Other embodiments are disclosed.

24 citations


Patent
06 Oct 2014
TL;DR: In this article, a signal interface unit in a radio system includes an external device interface configured to receive a downlink asynchronous radio carrier signal for a radio frequency carrier from a external device; a clock conversion unit communicatively coupled to the external device interfaces and configured to re-clock the downlink ASR carrier signal to a master clock of the radio system from the clock of an external devices.
Abstract: A signal interface unit in a radio system includes an external device interface configured to receive a downlink asynchronous radio carrier signal for a radio frequency carrier from an external device; a clock conversion unit communicatively coupled to the external device interface and configured to re-clock the downlink asynchronous radio carrier signal to a master clock of the radio system from the clock of the external device; and an antenna side interface configured to communicate at least one of the re-clocked downlink asynchronous radio carrier signal and a downlink digitized radio frequency signal based on the re-clocked downlink asynchronous radio carrier signal to an antenna unit.

24 citations


Patent
Jai Jin Lim1, Woo Jae Kim1
04 Mar 2014
TL;DR: In this paper, an enhanced base station and clock synchronization method is presented, which allows the base station to switch between the master and slave modes dynamically according to variation of the communication environment, resulting in efficient clock synchronization.
Abstract: An enhanced base station and clock synchronization method are provided. The method includes scanning to discover a satellite transmitting a satellite signal and a master base station providing clock synchronization signal, entering, when a satellite having a signal that fulfills predetermined conditions is found, a master mode for receiving the satellite signal to acquire clock synchronization and transmitting a clock synchronization signal to at least one slave base station, and entering, when no satellite having a signal that fulfills the predetermined conditions is found, a slave mode for receiving the clock synchronization signal from the master base station to acquire clock synchronization. The method allows the base station to switch between the master and slave modes dynamically according to variation of the communication environment, resulting in efficient clock synchronization.

21 citations


Journal ArticleDOI
TL;DR: In this paper, neutral mercury is proposed as an ideal atomic system for an optical clock based on two-photon $E$1-$M$1 transitions, which is the same as the one proposed in this paper.
Abstract: Neutral mercury is proposed to be an ideal atomic system for an optical clock based on two-photon $E$1-$M$1 transitions.

Patent
15 Oct 2014
TL;DR: In this paper, the authors present a scheme to synchronize the master/slave clocks of virtual machine (VM) host systems using PTP (Precision Time Protocol) timing messages and/or timing messages based upon some other timing protocol.
Abstract: Network timing synchronization for virtual machine (VM) host systems and related methods are disclosed that provide synchronization of master/slave clocks within VM host hardware systems. Master timing messages are sent from the master clocks to slave clocks within VM guest platforms hosted by the VM host hardware system within a virtualization layer, and return slave timing messages are communicated from the VM guest platforms to the master clock. Virtual switches within the virtualization layer use virtual transparent clocks to determine intra-switch delay times for the timing packets traversing the virtual switch. These intra-switch delay times are then communicated to target destinations and used to account for variations in packet transit times through the virtual switch. The VM guest platforms synchronize their timing using the timing messages. The master/slave timing messages can be PTP (Precision Time Protocol) timing messages and/or timing messages based upon some other timing protocol.

Patent
14 Mar 2014
TL;DR: In this paper, a master device may be placed closer to a slave device using a Remote Time-Stamp Generator, located in the network between the master and the slave, whose time reference serves as a proxy for the time reference of the master.
Abstract: The present invention generally relates to methods and apparatus for precision time transfer wherein the inherent packet delay variation and possible asymmetry introduced in networks is avoided or mitigated. In one embodiment, the timing functions of a master device may be placed closer to a slave device using a Remote Time-Stamp Generator, located in the network between the master and the slave, and whose time reference serves as a proxy for the time reference of the master. Time-of-traversal of packets at the remote time-stamp generator may be used as proxies for the time-of-departure and the time-of-arrival of certain messages at the master. Such proxy times may be used to synchronize the slave with the master, particularly if the master and the Remote Time-Stamp Generator are both synchronized with a Global Navigation Satellite System (GNSS) source.

Proceedings ArticleDOI
04 May 2014
TL;DR: An approach for synchronizing the sampling clocks of distributed microphones over a wireless network using a two stage procedure that employs a two-way message exchange algorithm and a gossiping algorithm to estimate a virtual master clock, to which all sensor nodes synchronize.
Abstract: "In this paper we present an approach for synchronizing the sampling clocks of distributed microphones over a wireless network. The proposed system uses a two stage procedure. It first employs a two-way message exchange algorithm to estimate the clock phase and frequency difference between two nodes and then uses a gossiping algorithmto estimate a virtual master clock, to which all sensor nodes synchronize. Simulation results are presented for networks of different topology and size, showing the effectiveness of our approach."

Journal ArticleDOI
26 May 2014
TL;DR: The developed system described in this paper allows timestamping image frames in a real-time acquisition and processing system using 1588 clock distribution and uses two PXI trigger lines that provide the capacity to assign timestamps to every frame acquired and register events by hardware in a deterministic way.
Abstract: Current fusion devices consist of multiple diagnostics and hundreds or even thousands of signals. This situation forces on multiple occasions to use distributed data acquisition systems as the best approach. In this type of distributed systems, one of the most important issues is the synchronization between signals, so that it is possible to have a temporal correlation as accurate as possible between the acquired samples of all channels. In last decades, many fusion devices use different types of video cameras to provide inside views of the vessel during operations and to monitor plasma behavior. The synchronization between each video frame and the rest of the different signals acquired from any other diagnostics is essential in order to know correctly the plasma evolution, since it is possible to analyze jointly all the information having accurate knowledge of their temporal correlation. The developed system described in this paper allows timestamping image frames in a real-time acquisition and processing system using 1588 clock distribution. The system has been implemented using FPGA based devices together with a 1588 synchronized timing card (see Fig.1). The solution is based on a previous system [1] that allows image acquisition and real-time image processing based on PXIe technology. This architecture is fully compatible with the ITER Fast Controllers [2] and offers integration with EPICS to control and monitor the entire system. However, this set-up is not able to timestamp the frames acquired since the frame grabber module does not present any type of timing input (IRIG-B, GPS, PTP). To solve this lack, an IEEE1588 PXI timing device its used to provide an accurate way to synchronize distributed data acquisition systems using the Precision Time Protocol (PTP) IEEE 1588 2008 standard. This local timing device can be connected to a master clock device for global synchronization. The timing device has a buffer timestamp for each PXI trigger line and requires that a software application assigns each frame the corresponding timestamp. The previous action is critical and cannot be achieved if the frame rate is high. To solve this problem, it has been designed a solution that distributes the clock from the IEEE 1588 timing card to all FlexRIO devices [3]. This solution uses two PXI trigger lines that provide the capacity to assign timestamps to every frame acquired and register events by hardware in a deterministic way. The system provides a solution for timestamping frames to synchronize them with the rest of the different signals.

Patent
22 Oct 2014
TL;DR: In this paper, the authors presented a method and device for monitoring Ethernet clock synchronization, where a slave clock device returns a delay request message to a master clock device, and the delay request messages carries link delay information between the master clock devices and the slave clock devices.
Abstract: The embodiment of the invention provides a method and device for monitoring Ethernet clock synchronization. In the method, a slave clock device returns a delay request message to a master clock device, and the delay request message carries link delay information between the master clock device and the slave clock device of a last time hack cycle, determined by the slave clock device, so that the master clock device is enabled to determine a time deviation between the master clock device and the slave clock device and according to whether the time deviation is smaller than a set time deviation threshold, whether to send alarm information is determined. Because in the method, the slave clock device returns the determined link delay information between the slave clock device and the master clock device to the master clock device from the master clock device so that the master clock device is enabled to determine a time hack condition of the slave clock device so as to achieve an objective of monitoring of the slave clock device and thus precision demands of time synchronization are ensured and loss caused by inaccuracy of time hack is reduced.

Journal ArticleDOI
TL;DR: This review highlights the progress made recently in the understanding of circadian clock architecture and function in Ostreococcus in the context of the marine environment.

Patent
16 Jan 2014
TL;DR: In this article, helper STAs synched to the master clock are used to determine discovery periods in which to transmit synch frames between synch frame transmissions by a master clock STA.
Abstract: Logic to manage synch frame transmissions in a synch network via helper stations (STAs) synched to the network. Logic may coordinate actions of helper STAs via a transmission window (TW) provided by a master clock STA. Logic may distribute synch frame transmissions within a TW via synch logic in the helper STAs. Logic in helper STAs of a synch network may determine discovery periods in which to transmit synch frames between synch frame transmissions by the master clock STA. Logic in helper STAs to determine a discovery period in which to transmit synch frames to share workload with the master clock STA and to extend the coverage area of the synch network. Logic of the master clock STA may establish a fixed TW based upon the number of helper STAs and a time constraint for discovering the synch network. Or logic of the master clock STA may establish a dynamic TW in which the master clock STA can adjust the TW based upon a number of synch frame transmissions during a TW.

Patent
James Aweya1
11 Dec 2014
TL;DR: In this paper, the authors proposed a clock synchronization method for small cell backhaul solutions for 4G/LTE deployments, where the master clock uses link rate information to estimate the transmission delay asymmetry and thus estimate the offset and skew of the slave clock.
Abstract: This invention relates to methods and devices for clock synchronization. The invention has particular application in the alignment of slave clocks to a master clock and in dealing with transmission delay asymmetries where the forward and reverse communication paths between the master and slave clocks have asymmetric transmission rates. Such methods and devices have particular application in small cell backhaul solutions for 4G/LTE deployments. In embodiments of the invention, the slave clock uses link rate information to estimate the transmission delay asymmetry and thus estimate the offset and skew of the slave clock. Embodiments provide a simple linear approximation technique and a Kalman filter-based technique for estimating offset and skew of the slave clock.

Journal ArticleDOI
TL;DR: Setting up the normal rhythm of the circadian cycle also involves oscillating changes in the chromatin structure, allowing differential activation of various chromatin domains within the 24-h cycle.
Abstract: Many physiological processes occur in a rhythmic fashion, consistent with a 24-h cycle. The central timing of the day/night rhythm is set by a master clock, located in the suprachiasmatic nucleus (a tiny region in the hypothalamus), but peripheral clocks exist in different tissues, adjustable by cues other than light (temperature, food, hormone stimulation, etc.), functioning autonomously to the master clock. Presence of unrepaired DNA damage may adjust the circadian clock so that the phase in which checking for damage and DNA repair normally occurs is advanced or extended. The expression of many of the genes coding for proteins functioning in DNA damage-associated response pathways and DNA repair is directly or indirectly regulated by the core clock proteins. Setting up the normal rhythm of the circadian cycle also involves oscillating changes in the chromatin structure, allowing differential activation of various chromatin domains within the 24-h cycle.

Patent
08 Jan 2014
TL;DR: In this article, a method of aligning clock signals in multiple transceiver channels on an integrated circuit may include adjusting a slave clock signal at a slave transceiver channel based on a master clock signal received from a master transceiver.
Abstract: A method of aligning clock signals in multiple transceiver channels on an integrated circuit may include adjusting a slave clock signal at a slave transceiver channel based on a master clock signal received from a master transceiver channel. A clock generation circuit and/or a delay circuit in the slave transceiver channel may be used to adjust the slave clock signal to produce an intermediate slave clock signal. The master clock signal may be adjusted based on the intermediate slave clock signal received at the master transceiver channel to obtain a total adjustment value. The phase of the intermediate slave clock signal may further be adjusted at the slave transceiver channel based on the total adjustment made at the master transceiver channel.

Patent
17 Jan 2014
TL;DR: In this paper, the authors propose a method for synchronizing packet timestamps generated by a network probe with a free running clock to a master clock connected at a different location of the network.
Abstract: The invention relates to time synchronization between network testing elements in distributed network monitoring and testing systems, and provides a method for synchronizing packet timestamps generated by a network probe with a free running clock to a master clock connected at a different location of the network. In one implementation, the probe eavesdrops on a PTP message exchange between the master and a remote slave device, recording message reception times according to it free running clock and transmitting relevant timing information to a rest server for determining the probe clock offset and updating the probe packet timestamps.

Patent
15 Jan 2014
TL;DR: In this article, a system for synchronizing the redundant time of an intelligent substation is presented, which is of the redundant configuration with double master clocks and two sets of extension clocks, and the time source signals are synchronized in a mode of carrying out regulation step by step with the fixed step length.
Abstract: The invention discloses a method for synchronizing redundant time of an intelligent substation. A system for synchronizing the redundant time of the intelligent substation is of the redundant configuration with double master clocks and two sets of extension clocks. The double master clocks receive and synchronize double time source signals, the extension clocks receive and synchronize double master clock time source signals, a time service device receives and synchronizes the time source signals coming from the extension clocks, the time service device having high requirements for time synchronization and accuracy transmits the time source signals through IRIG-B and IEC61588, the effectiveness of the time source signals is judged before synchronization of the double master clocks and double time sources, synchronization of the extension clocks and the double master clocks and synchronization of the time service device and the extension clocks, and the time source signals are synchronized in a mode of carrying out regulation step by step with the fixed step length. The method meets the requirement for reliability, stability and high accuracy of time synchronization of the intelligent substation.

Patent
11 Sep 2014
TL;DR: In this article, a mobile device consisting of a slave clock, a master clock, and a clock error correction unit (400) is configured to maintain clock synchronization between the slave clock and the master system clock.
Abstract: Embodiments of the present invention provide a mobile device (12) comprising a slave clock (13), a receiver unit (19) for receiving one or more frames from a remote device (11) including a master system clock (14), a transmitter unit (18) for transmitting one or more frames to the remote device (11), and a clock error correction unit (400). The clock error correction unit (400) is configured to maintain clock synchronization between the slave clock (13) and the master system clock (14), and maintain frame alignment for frames transmitted from the transmitter unit (18).

Journal ArticleDOI
TL;DR: This steady remote two-color optical-to-optical synchronization is an important step toward an integrated femtosecond fiber timing distribution system for free-electron lasers (FELs); it does not require x-ray pulses, and it makes sub-10-fs optical/x-ray pump-probe experiments feasible.
Abstract: Using balanced detection in both the radio frequency (RF) and the optical domain, we remotely synchronize the repetition rate of a Ti:sapphire oscillator to an Er-doped fiber oscillator through a 360 m length-stabilized dispersion compensated fiber link. The drift between these two optical oscillators is 3.3 fs root mean square (rms) over 24 hours. The 68 MHz Er-doped fiber oscillator is locked to a 476 MHz local RF reference clock, and serves as a master clock to distribute 10 fs-level timing signals through stabilized fiber links. This steady remote two-color optical-to-optical synchronization is an important step toward an integrated femtosecond fiber timing distribution system for free-electron lasers (FELs); it does not require x-ray pulses, and it makes sub-10-fs optical/x-ray pump-probe experiments feasible.

Patent
25 Jun 2014
TL;DR: In this article, a method and device for clock time synchronization is presented, which relates to the Ethernet technology. The method comprises the steps of estimating the clock jitter and the clock frequency deviation with the difference of sending and receiving timestamp of a synchronous message packet and the time difference of a response message packet in a precision time protocol (PTP) message packet as observed values respectively to obtain the phase difference of the master clock and a slave clock.
Abstract: The invention discloses a method and device for achieving clock time synchronization, and relates to the Ethernet technology. The method comprises the steps of estimating the clock jitter and the clock frequency deviation with the difference of sending and receiving timestamp of a synchronous message packet and the difference of sending and receiving timestamp of a response message packet in a precision time protocol (PTP) message packet as observed values respectively to obtain the phase difference of a master clock and a slave clock, and carrying out the synchronization adjustment on the slave clock according to the estimated phase difference. The invention further discloses the device for achieving the clock time synchronization. According to the technical scheme, the state quantity is obtained by calculating measuring values respectively based on the kalman filtering algorithm and the combination (O+D and O-D) of the phase difference and the path delay, the estimated value for the clock synchronization phase difference is obviously far more superior to the estimated value, worked out through the single measuring value of the phase difference serving as the state value, for the clock synchronization phase difference , the phase difference can be reflected better and the synchronous precision between the master clock and the slave clock is greatly improved.

Patent
29 Sep 2014
TL;DR: In this article, an intermediate clock, either a boundary or a transparent clock, may have to adjust its local clock to match that of a grandmaster clock, and the intermediate clock may not have much confidence in the reliability of the timing information it passes to a downstream clock in an IEEE 1588 Announce message.
Abstract: An intermediate clock, either a boundary or a transparent clock, may have to adjust its local clock to match that of a grandmaster clock. If such adjustment is frequent or large, then the intermediate clock may not have much confidence in the reliability of the timing information it passes to a downstream clock in an IEEE 1588 Announce message even if the quality of its local clock is high. The intermediate clock determines a measure of the reliability of its timing information. The intermediate clock inserts an indication of the reliability of the timing information in a transmitted IEEE 1588 Announce message. The intermediate clock may consider an indication of reliability found in an Announce message it receives when inserting an indication of the reliability of timing information into an Announce message which it transmits.

Journal ArticleDOI
TL;DR: The theoretical analysis and experimental results show that the proposed RTE solution can achieve good real-time performance with low process latency and high time-synchronization accuracy, which satisfies the real- time communication requirements of RTE-based NC systems in an economical way.
Abstract: This paper proposes a complete real-time Ethernet (RTE) solution including master and slave controllers for numerical control (NC) systems. To meet the development tendency of NC systems moving toward multi-axis coordination, high speed and high precision, one type of RTE architecture is built up with a dual ring topology. The function blocks of master/slave nodes are designed to realize the real-time communication capabilities using embedded CPU and field programmable gate array (FPGA) technologies. To reduce the minimum achievable cycle time, a cut-through transmission mechanism is employed to decrease the process latency at slave nodes, and the synchronization frame is optimized to shorten the frame duration. In order to synchronize the nodes of RTE-based NC systems accurately, a time synchronization strategy is scheduled and a proportion-integration (PI)-based phase-locked loop (PLL) is designed to keep the master clock and the slave clocks in step stably. The theoretical analysis and experimental results show that the proposed RTE solution can achieve good real-time performance with low process latency and high time-synchronization accuracy, which satisfies the real-time communication requirements of RTE-based NC systems in an economical way.

Patent
08 Jan 2014
TL;DR: In this paper, a master device sends synchronization packets to one or more slave devices, and does so periodically based on a master clock signal having a clock frequency, and each of the slave devices can update the frequency of their respective slave clock signal (e.g., using a frequency offset) to match that of the estimated master clock frequency.
Abstract: According to some embodiments, a master device sends synchronization packets to one or more slave devices, and does so periodically based on a master clock signal having a master clock frequency. At each of the slave devices, an algorithm estimates the master clock frequency based on the timing of synchronization packet arrivals the slave device. The algorithm may estimate the master clock frequency using both the currently-observed timing of synchronization packet arrivals and the history of previous synchronization packet arrivals (e.g., previously-observed timing of synchronization packet arrivals). Based on the estimated master clock frequency, each of the one or more slave devices can update the frequency of their respective slave clock signal (e.g., using a frequency offset) to match that of the estimated master clock frequency.

Patent
18 Nov 2014
TL;DR: In this article, a communication system is described in which consists of a master device that includes a master clock and is connected to a host through a communication network, and a plurality of nodes connected to the master device.
Abstract: A communication system is disclosed herein. The communication system includes a master device that includes a master clock and is connected to a host through a communication network, and a plurality of nodes connected to the master device. The master device transmits one or more periodic beams that include a radio frequency. Each of the nodes includes a node clock that is configured and in synchronization with the master clock based on the one or more periodic beams. The communication system establishes a connection for communication between the master device and at least one node when the node clock of the at least one node is in synchronization with the master clock. The communication system further includes at least one repeater 104 A operatively connected between the master device and at least one node.