Showing papers on "Master clock published in 2015"

Keeping circadian time with hormones.

Abstract: Daily variations of metabolism, physiology and behaviour are controlled by a network of coupled circadian clocks, comprising a master clock in the suprachiasmatic nuclei of the hypothalamus and a multitude of secondary clocks in the brain and peripheral organs. Light cues synchronize the master clock that conveys temporal cues to other body clocks via neuronal and hormonal signals. Feeding at unusual times can reset the phase of most peripheral clocks. While the neuroendocrine aspect of circadian regulation has been underappreciated, this review aims at showing that the role of hormonal rhythms as internal time-givers is the rule rather than the exception. Adrenal glucocorticoids, pineal melatonin and adipocyte-derived leptin participate in internal synchronization (coupling) within the multi-oscillatory network. Furthermore, pancreatic insulin is involved in food synchronization of peripheral clocks, while stomach ghrelin provides temporal signals modulating behavioural anticipation of mealtime. Circadian desynchronization induced by shift work or chronic jet lag has harmful effects on metabolic regulation, thus favouring diabetes and obesity. Circadian deregulation of hormonal rhythms may participate in internal desynchronization and associated increase in metabolic risks. Conversely, adequate timing of endocrine therapies can promote phase-adjustment of the master clock (e.g. via melatonin agonists) and peripheral clocks (e.g. via glucocorticoid agonists).

EGR1 regulates hepatic clock gene amplitude by activating Per1 transcription.

Abstract: The mammalian clock system is composed of a master clock and peripheral clocks. At the molecular level, the rhythm-generating mechanism is controlled by a molecular clock composed of positive and negative feedback loops. However, the underlying mechanisms for molecular clock regulation that affect circadian clock function remain unclear. Here, we show that Egr1 (early growth response 1), an early growth response gene, is expressed in mouse liver in a circadian manner. Consistently, Egr1 is transactivated by the CLOCK/BMAL1 heterodimer through a conserved E-box response element. In hepatocytes, EGR1 regulates the transcription of several core clock genes, including Bmal1, Per1, Per2, Rev-erbα and Rev-erbβ, and the rhythm amplitude of their expression is dependent on EGR1's transcriptional function. Further mechanistic studies indicated that EGR1 binds to the proximal region of the Per1 promoter to activate its transcription directly. When the peripheral clock is altered by light or feeding behavior transposition in Egr1-deficient mice, the expression phase of hepatic clock genes shifts normally, but the amplitude is also altered. Our data reveal a critical role for EGR1 in the regulation of hepatic clock circuitry, which may contribute to the rhythm stability of peripheral clock oscillators.

Timing over packet demarcation entity

Abstract: Apparatus for synchronizing a local clock to a master clock, the apparatus comprising: at least one port for receiving and transmitting packets; a local clock; and a packet inspector that uses time from the local clock to timestamp packets received at a port of the at least one port, copies timing information from the received packets if the packets are timing distribution packets that are transmitted between a master clock and a slave clock in order to synchronize the slave clock to the master clock, and forwards the received packets for transmission from a port of the at least one port towards a packet destination that is not a packet source from where the packets originate, wherein the local clock uses the copied timing information and timestamps to synchronize the local clock to the master clock.

A method for robust ptp synchronization with default 1588v2 profile

Abstract: Exemplary methods for reducing sync time in a precision time protocol (PTP) network include receiving, by a first PTP slave port of a first network device, timing messages from a second PTP master port of a second network device. The methods include maintaining a PTP master clock based on timing information included in the timing messages received from the second network device via the first PTP port. The methods further include receiving, by a third PTP passive port of the first network device, timing messages from a fourth PTP master port of a third network device. The methods include determining the third PTP passive port is a protective passive port based on a stepsRemoved value of the third network device, and maintaining an auxiliary clock based on the timing information included in the timing messages received from the third network device via the third PTP port.

A Method for Compression of Intra-Cortically-Recorded Neural Signals Dedicated to Implantable Brain–Machine Interfaces

Abstract: This paper proposes an efficient data compression technique dedicated to implantable intra-cortical neural recording devices. The proposed technique benefits from processing neural signals in the Discrete Haar Wavelet Transform space, a new spike extraction approach, and a novel data framing scheme to telemeter the recorded neural information to the outside world. Based on the proposed technique, a 64-channel neural signal processor was designed and prototyped as a part of a wireless implantable extra-cellular neural recording microsystem. Designed in a 0.13- $\mu$ m standard CMOS process, the 64-channel neural signal processor reported in this paper occupies ${\sim} 0.206$ mm $^{2}$ of silicon area, and consumes 94.18 $\mu$ W when operating under a 1.2-V supply voltage at a master clock frequency of 1.28 MHz.

Circadian Tick-Talking Across the Neuroendocrine System and Suprachiasmatic Nuclei Circuits: The Enigmatic Communication Between the Molecular and Electrical Membrane Clocks.

Abstract: As with many processes in nature, appropriate timing in biological systems is of paramount importance. In the neuroendocrine system, the efficacy of hormonal influence on major bodily functions, such as reproduction, metabolism and growth, relies on timely communication within and across many of the brain's homeostatic systems. The activity of these circuits is tightly orchestrated with the animal's internal physiological demands and external solar cycle by a master circadian clock. In mammals, this master clock is located in the hypothalamic suprachiasmatic nucleus (SCN), where the ensemble activity of thousands of clock neurones generates and communicates circadian time cues to the rest of the brain and body. Many regions of the brain, including areas with neuroendocrine function, also contain local daily clocks that can provide feedback signals to the SCN. Although much is known about the molecular processes underpinning endogenous circadian rhythm generation in SCN neurones and, to a lesser extent, extra-SCN cells, the electrical membrane clock that acts in partnership with the molecular clockwork to communicate circadian timing across the brain is poorly understood. The present review focuses on some circadian aspects of reproductive neuroendocrinology and processes involved in circadian rhythm communication in the SCN, aiming to identify key gaps in our knowledge of cross-talk between our daily master clock and neuroendocrine function. The intention is to highlight our surprisingly limited understanding of their interaction in the hope that this will stimulate future work in these areas.

Multilane serdes clock and data skew alignment for multi-standard support

Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Synchronizing Clocks in a Communications Network

Abstract: A User Equipment comprises a master clock, for example a Precision Time Protocol, PTP, or Precision Time Control Protocol, PTCP, network clock. The User Equipment further comprises circuitry configured to set the master clock based on signals from a wireless communications network node and a time offset, wherein the time offset is based on the propagation delay between the wireless network node and the User Equipment. The circuitry is further configured to send timing information to a network device in a communications network having a slave clock, whereby the network device can synchronize its slave clock with respect to the master clock comprised within the User Equipment.

Seafloor observation network time synchronization method under large traffic background

Abstract: The invention discloses a seafloor observation network time synchronization method under a large traffic background. The time synchronization method is based on IEEE1588V2 protocol and T-MPLS configuration. A shore-based station PTP master clock receives global position system (GPS) or Beidou satellite signals to be synchronized with a local clock of the shore-based station PTP master clock and serves as a time synchronization system clock source to provide time service for a seafloor observation network. The shore-based station PTP master clock is connected with an underwater PTP slave clock through network transmission devices such as a shore-based station PTN, an underwater main junction box PTN and an underwater auxiliary junction box exchanger to be synchronized with time of the underwater PTP slave clock through interaction of PTP time synchronization messages, and the PTP slave clock provides multi-mode time signal time services for the observation network. Virtual private channels of the PTP time synchronization messages and data packets are arranged respectively through T-MPLS, thereby, timely response transmission of the PTP time synchronization messages can be achieved, and the time synchronization accuracy of the seafloor observation network can be greatly improved.

Method and apparatus for synchronizing clocks underwater using light and sound

Abstract: Methods and systems for synchronizing clocks used in underwater devices is described. All clocks have some drift due to frequency accuracy and this disclosure provides a method for periodically synchronizing clocks to an accurate master clock to remove long term drift. A synchronization device can use an accurate clock and hardware to transmit both a sound wave and light pulse at the same point in time. Remote slave clocks can detect the light first, and later the sound, allowing them to calculate the distance the pulse had to travel. The clocks can then synchronize their time to the master clock canceling out any drift. The synchronization device can be packaged in a waterproof housing and can be moved around on a periodic basis between the clock on an underwater robot or any other means.

Robust clock ensemble for time and frequency reference system

Abstract: A robust clock ensemble is proposed for the time and frequency reference system to improve the robustness and performance of the system Studies on the feasibility of hardware and algorithm approaches have been conducted All clocks in the ensemble are locked in phase and frequency via the steering loop The system performs corrections on the master clock in function of weighted averaging of clocks to generate one ensemble output, and the clock fault detection and compensation is implemented in real time with minimum three clocks powered As the design has been demonstrated on an elegant breadboard of the Robust Onboard Frequency Reference Subsystem, this concept is proposed for the next-generation of Precise Timing Facility Simulation results have demonstrated its capability and simplicity to provide a smooth and reliable timing or frequency output even in presence of clock feared events

System and method for clock synchronization in a wireless backhaul network using IEEE 1588 precision time protocol

Abstract: A method and system is disclosed for clock synchronization in a wireless backhaul network, based on the IEEE1588 Precision Time Protocol (PTP) The network comprises a plurality of hubs, each hub serving one or more remote backhaul modules Each hub comprises a slave clock, which communicates with a master clock through forward and reverse links The method comprises, for each hub, estimating the frequency drift {circumflex over (α)} and offset {circumflex over (β)} from the forward and reverse links between the master and slave clock, estimating the accuracy of {circumflex over (α)} and {circumflex over (β)}, determining the least congested link, and adjusting the frequency of the slave clock based on {circumflex over (α)} and {circumflex over (β)} from the least congested link A fixed or variable time window size is selected to achieve a desired accuracy of {circumflex over (α)} and {circumflex over (β)} The method may comprise estimating a maximum holdover time for maintaining synchronization with a desired confidence level

Synchronized measurement device using local area network with ethernet messaging

Abstract: A plurality of measurement devices have analog sensors that measure the dynamic signals of physical events, sample the data into digital format with time synchronized clocks and generate time stamped Ethernet messages that are sent to a remote host. The remote host has a master clock that evaluates decoded time stamped messages from the measurement devices and sends back a message with a time correction error signal relative to the master clock. This feedback signal is used by the measurement devices to correct a local clock for data sampling and new message generation. Eight wire cable and associated connectors are used to handle three channels of traffic, with four wires dedicated to Ethernet messages as one channel, another two wires dedicated to reset and other commands as a second channel and another two wires to transmit power from the host to the measurement devices as a third channel.

Electrical equipment local discharge positioning method and system

Abstract: The invention relates to an electrical equipment local discharge positioning method and system. The method comprises the following steps of selecting one of a plurality of wireless sensors as a master clock and the other wireless sensors as slave clocks, and synchronizing the time of the master clock and the slave clocks; controlling the master clock to transmit a synchronous measurement instruction, and enabling the slave clocks to synchronously collecting ultrasonic signals generated in an electrical equipment measuring position at the same time with the master clock after receiving the synchronous measurement instruction; obtaining the head wave time of the ultrasonic signals in a wireless mode, which is recorded by a local discharge pulse time extracting module in every wireless sensor, selecting the shortest four head wave times, and according to the four head wave times and the positions of the corresponding wireless sensors determining the local discharge position of electrical equipment. By achieving ultrasonic collection and positioning through the wireless sensors, the electrical equipment local discharge positioning method is low in workload and high in safety.

Approximate Synchrony: An Abstraction for Distributed Almost-Synchronous Systems

Abstract: Forms of synchrony can greatly simplify modeling, design, and verification of distributed systems. Thus, recent advances in clock synchronization protocols and their adoption hold promise for system design. However, these protocols synchronize the distributed clocks only within a certain tolerance, and there are transient phases while synchronization is still being achieved. Abstractions used for modeling and verification of such systems should accurately capture these imperfections that cause the system to only be “almost synchronized.” In this paper, we present approximate synchrony, a sound and tunable abstraction for verification of almost-synchronous systems. We show how approximate synchrony can be used for verification of both time synchronization protocols and applications running on top of them. We provide an algorithmic approach for constructing this abstraction for symmetric, almost-synchronous systems, a subclass of almost-synchronous systems. Moreover, we show how approximate synchrony also provides a useful strategy to guide state-space exploration. We have implemented approximate synchrony as a part of a model checker and used it to verify models of the Best Master Clock (BMC) algorithm, the core component of the IEEE 1588 precision time protocol, as well as the time-synchronized channel hopping protocol that is part of the IEEE 802.15.4e standard.

Clock synchronization method of network sampling intelligent substation

Abstract: The invention discloses a clock synchronization method of network sampling intelligent substation, wherein double master clock redundancy backups are used; the master clock is composed of a master clock A and a master clock B; an extended clock is composed of clock 1 to clock n; all extended clocks uniformly select the master clock A as the default time source, and then are uniformly switched to the standby master clock B when the master clock A becomes invalid. The invention solves the problems of intelligent substation synchronization system, puts forward a comprehensive solution for the clock synchronization system of network sampling intelligent substation, puts forward a combination mode of clock sources of the intelligent substation time synchronization system, and puts forward a way to track the satellite time and a seamless switching strategy between a GPS time source and a Beidou time source, greatly optimizes an abnormal fault tree structure of the intelligent substation time synchronization and protection malfunction fault tree structure caused by abnormal time synchronization, and can effectively improve the stability and reliability of the time synchronization system of intelligent substation.

Sub-nanosecond distributed clock synchronization using alignment marker in ethernet ieee 1588 protocol

Abstract: A method for determining a slave clock to master clock time difference with an alignment marker. The method selects and transmits a first alignment marker at a first time by a transmitter that has a master clock in a first message to a receiver that has a slave clock. Subsequent to transmitting the first message, the method further transmits a second message that contains the first time and an identity of the first alignment marker. The method further receives the first message and records a second time that the first message is received. The method further receives the second message and the first time and the identity of the first alignment marker. The method further determines a transmission delay and generates a time difference from the slave clock to the master clock.

Synchronization precision monitoring system of time synchronization device of power equipment

Abstract: The invention discloses a synchronization precision monitoring system of a time synchronization device of power equipment. The synchronization precision monitoring system comprises a center monitoring system, a network management system and a measurement device. The measurement device is arranged in a transformer substation and is connected with master clock equipment, expanded clock equipment and equipment with time service which are in the transformer substation. The measurement device acquires a time signal of the master clock equipment in the transformer substation, converts the time signal into a precision time protocol (PTP) message packaged by E1, and then transmits to the center monitoring system through an E1 channel of an interstation synchronous digital hierarchy (SDH); the center monitoring system restores according to the PTP message so as to acquire the time signal of a master clock of the transformer substation, compares the time of the master clock of the transformer substation with current time so as to acquire a first time difference, and transmits the first time difference to the network management system; and the measurement device confirms a second time difference between the time of the master clock equipment and the time of the expanded clock equipment and the equipment with time service in the transformer substation, and transmits the second time difference to the network management system. The synchronization precision monitoring system can acquire the output accuracy of the time synchronization device in time.

Method, system and device for clock synchronization over time-varying and lossy networks

Abstract: The present invention is directed towards a method, a system, and a device which allow an improved synchronization of a system-wide timing information over a network Hence, slave clocks can be synchronized to a high quality clock, such as a master clock

Providing precision timing protocol (ptp) timing and clock synchronization for wireless multimedia devices

Abstract: Providing Precision Timing Protocol (PTP) timing and clock synchronization for wireless multimedia devices is disclosed. In one aspect, a primary wireless multimedia device comprising a timing synchronization control system is provided. The timing synchronization control system is configured to apply a PTP Best-Master-Clock (BMC) algorithm logic to select a master clock from among a system clock of the primary wireless multimedia device, one of one or more connected wireless multimedia devices, or one of one or more external nodes. If the timing synchronization control system selects the system clock of the primary wireless multimedia device, a clock signal of the system clock is provided to the connected wireless multimedia devices as the master clock. If the timing synchronization control system selects a connected wireless multimedia device or an external node as the master clock, the timing synchronization control system synchronizes the system clock with the master clock.

Systems and methods for chip to chip communication

Abstract: Systems and methods for chip to chip communication are disclosed. In an exemplary aspect, a chip to chip link comprises a master device having a data transmitter, a clock, a clock transmitter, a phase locked loop (PLL) associated with the clock, and a receiver. The chip to chip link also comprises a slave device that has a data transmitter, a clock receiver, and a data receiver. Noticeably absent from the slave device is a clock or a PLL. By removing the clock from the slave device, the slave device does not have the power consuming element of a slave PLL. Further, because the slave device does not have a clock which would normally have to acquire a new frequency and settle, the master clock may change frequency relatively quickly and vary the frequency across many frequencies, not just one or two predefined frequencies.

Method and apparatus for synchronization of slave clock to master clock

Abstract: Existing synchronization methods can be inefficient in hardware-assisted implementations because of the effects of various jittery events. Thus, a method and an apparatus are provided to synchronize a slave device's clock to a master device's clock for a hardware-assisted implementation. The method can include the receipt of three messages. Time differences are determined based on a time extracted from two of the messages and a time of receipt of a different one of the messages. The slave device's clock can be adjusted based on these time differences. Thus, this method, which can include a dynamic weighted average to compute and implement the synchronization, can synchronize the clock of the slave device to the clock of the master device in a faster time interval.

A servo design for slave clock in IEEE 1588 synchronization networks

Abstract: Summary Clock synchronization is critical for a variety of applications in communication networks. In this paper, we design a clock servo named VI_PID-K, which consists of a variable integral PID controller and a Kalman filter. It is a pre-correction mechanism for the skew based on feedback principle to compensate for the poor stability of local clocks in IEEE 1588 networks. Our contribution is establishing discrete differential equation models, bringing in a variable integral PID controller to adjust the skew error and a Kalman filter to act as a skew estimator to predict the skew during one synchronization interval. Simulation results demonstrate that VI_PID-K provides a more stable disciplined clock, improves the speed of skew convergence, and reduces Allan variance in a large time scale when compared to PI method or Fixed_Integral method.VI_PID-K can improve the stability of slave clock and reduce the frequency that master clock sends Sync messages, so the network overhead for clock synchronization can be reduced. Copyright © 2013 John Wiley & Sons, Ltd.

Method for improving time synchronization precision under complex network environment

Abstract: The invention discloses a method for improving time synchronization precision under a complex network environment. The method mainly solves the problems that synchronization precision of an existing network time synchronization method can not meet requirements of engineering projects and in a serious case, master equipment and slave equipment can not be synchronized normally. The method includes the first step that that a master clock and a slave clock extract timestamps of multiple moments respectively; the second step that unlink delay and downlink delay are measured, and an uplink time delay threshold value and a downlink time delay threshold value are obtained through a time delay detection algorithm; the third step that the timestamps corresponding to the moments beyond the time delay threshold values are removed; the fourth step that precise network time delay is figured out through a time synchronization algorithm and an asymmetrical time delay compensation algorithm; the fifth step that the time of the master clock and the time of the slave clock are synchronized by the utilization of the time synchronization algorithm. The method is suitable for any network time synchronization algorithm, and by the adoption of the method, the time synchronization precision and stability can be greatly improved.

SDN (software definition network) technology applicable to power communication

Abstract: The invention relates to an SDN (software definition network) technology applicable to power communication. The technology can provide an IEEE1588B network optimization scheme and meet the requirement of a power system for synchronization time. Announce messages are directly received and sent through a controller, a BMC (best master clock) algorithm is operated, time priority of each device is analyzed and judged, and the master-slave hierarchy state is determined at a time; flow tables are issued by the controller, paths between master and slave clocks are designated, and communication paths in two directions are forced to be symmetrical. The service flow direction multi-attribute design is provided, data security visits among departments are guaranteed, and data sharing among the departments is realized through bottom layer terminal sharing on the basis of a communication network platform.

Analog to digital converter compatible with image sensor readout

Abstract: A time to digital converter (TDC) includes a synchronizer configured to receive a stop signal and a master clock signal, wherein the synchronizer is configured to generate a clock stop signal and a counter enable signal. The TDC further includes a coarse counter configured to receive the master clock signal and the counter enable signal, wherein the coarse counter is configured to generate a most significant bits (MSB) signal based on the counter enable signal and the master clock signal. The TDC further includes a delay line counter configured to receive the stop signal and the clock stop signal, wherein the delay line counter is configured to generate a least significant bits (LSB) signal based on the stop signal and the clock stop signal, and the delay line counter is further configured to perform correlated double sampling (CDS).

Power reduction through clock management

Abstract: Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.

The Clock System in Readout Electronics System for the External Target Experiment in CSR of HIRFL

Abstract: A high precision clock system is required in the external target experiment of the Cooling Storage Ring (CSR) project in the Heavy Ion Research Facility in Lanzhou (HIRFL) Considering that the detectorsare located in different places of the experimental hall, a high quality clock signal is required to be generated and distributed to multiple measurement modules over long distances The clock system is based on a master-slave structure: the slave clock module (SCM) receives the clock signal from the master clock module (MCM) through fiber, and then distributes it to the measurement modules within the same PXI crate Laboratory test results indicate that the period jitter and cycle-to-cycle jitter of this clock system is better than 5 ps and 85 ps respectively We also conducted tests on the TOF (time of flight) readout modules (with the highest time measurement resolution in the readout electronics) combined with this clock system, and a time resolution better than 25 ps is achieved, beyond the requirement Keywords-cycle to cycle jitter; period jitter; clock skew; LVDS; clock system

Clock domain crossing AHB (advanced high-performance bus) bridging method and device

Abstract: The invention discloses a clock domain crossing AHB (advanced high-performance bus) bridging method and device. The device comprises a master control logic module, a slave control logic module, a master clock and slave clock data latching module and an asynchronous pulse and synchronous circuit module. The master control logic module generates a bus control signal of a master clock domain according to a bus signal of a master device; the master control logic module generates a response signal fed back to the master device according to a slave device bus signal sampled in the master clock domain and latched by a slave clock domain; the slave control logic module generates a bus control signal of the slave clock domain according to a response signal of a slave device and a master device bus signal sampled in the slave clock domain and latched by the master clock domain; when the bus control signal is effectively enabled, the master clock and slave clock data latching module latches and samples synchronous data; the asynchronous pulse and synchronous circuit module synchronizes clock domain crossing signals to an opposite-party clock domain. The clock domain crossing AHB bridging method and device have the advantage that the master and slave devices can implement the AHB protocol under any frequency.