Showing papers on "Master clock published in 2017"

Miniaturized calcium beam optical frequency standard using fully-sealed vacuum tube with 10-15 instability.

Abstract: We implement a miniaturized calcium beam optical frequency standard using specially-designed fully-sealed vacuum tube, and realize the comparison with another calcium beam optical clock whose vacuum tube is sealed by flanges. The electron shelving detection method is adopted to improve the signal-to-noise ratio of the clock transition spectroscopy, and the readout laser is locked by modulation-free frequency locking technology based on Doppler effect. Injection locking is carried out to boost the power of the 657 nm master clock transition laser, thus ensuring the comparison. The fractional instability of the miniaturized calcium beam optical frequency standard using fully-sealed vacuum tube is 1.8×10-15 after 1600 s of averaging. Total volume of the system except for electronics is about 0.3 m3. To our knowledge, it's the first time to realize the optical frequency standard using fully-sealed vacuum tube. This work will promote the miniaturization and transportability of the optical clock based on atomic beam.

Clock Technology: The Next Frontier

Abstract: Clocking of electrical circuit is a crucial issue since clock signal is used to establish the flow-of-time inside electronic world Before, during and after the "Moore's law", flow-of-time is an eternal issue Alongside processor, memory/storage and analog/ RF technologies, IC clocking could be regarded as the 4th major IC design technology In the past several decades, clock is mostly used in the form of fixed-frequency with high frequency stability For future system, however, this type of clock signal is not sufficient because its usage environment is not expected to be stationary but dynamic To meet this challenge, innovation in IC clocking is required This paper first discusses the difficulties in creating flow-of-time; then the two long-lasting problems in clock generation are identified, and then new challenges in the design of future system are summarized Afterwards, the Time-Average-Frequency based flexible clock generator is introduced and its potential to confront these challenges is addressed Several major issues in modern design are discussed The paper concludes with a vision that, for electronic system to improve its information processing efficiency to next level, clock technology is the next frontier to be explored

Synchronization Improvement of Distributed Clocks in EtherCAT Networks

Abstract: The aim of this letter is to improve the performance of clock synchronization in EtherCAT networks. Although EtherCAT synchronizes the slave clocks to the reference clock using a distributed clock synchronization mechanism, a synchronization error still exists between them. We propose a method to estimate and significantly reduce this error. In addition, we implement the method within the existing synchronization mechanism without adding an excessive computational load. The experimental results for synchronization performance verify that the proposed method improves the accuracy of clock synchronization in EtherCAT networks.

Scalable and Passive Wireless Network Clock Synchronization in LOS Environments

Abstract: Clock synchronization is ubiquitous in wireless systems for communication, sensing, and control. In this paper, we design a scalable system in which an indefinite number of passively receiving wireless units can synchronize to a single master clock at the level of discrete clock ticks. Accurate synchronization requires an estimate of the node positions to compensate the time-of-flight transmission delay in line-of-sight environments. If such information is available, the framework developed here takes position uncertainties into account. In the absence of such information, as in indoor scenarios, we propose an auxiliary localization mechanism. Furthermore, we derive the Cramer–Rao bounds for the system, which show that it enables synchronization accuracy at sub-nanosecond levels. Finally, we develop and evaluate an online estimation method, which is statistically efficient.

Remote quantum clock synchronization without synchronized clocks

Abstract: A major outstanding problem for many quantum clock synchronization protocols is the hidden assumption of the availability of synchronized clocks within the protocol. In general, quantum operations between two parties do not have consistent phase definitions of quantum states, which introduce an unknown systematic phase error. We show that despite prior arguments to the contrary, it is possible to remove this unknown phase via entanglement purification. This closes the loophole for entanglement based quantum clock synchronization protocols, which are most compatible with current photon based long-distance entanglement distribution schemes. Starting with noisy Bell pairs, we show that the scheme produces a singlet state for any combination of (i) differing basis conventions for Alice and Bob; (ii) an overall time offset in the execution of the purification algorithm; and (iii) the presence of a noisy channel. Error estimates reveal that better performance than existing classical Einstein synchronization protocols should be achievable using current technology.

A Robust Molecular Network Motif for Period-Doubling Devices.

Abstract: Life is sustained by a variety of cyclic processes such as cell division, muscle contraction, and neuron firing. The periodic signals powering these processes often direct a variety of other downstream systems, which operate at different time scales and must have the capacity to divide or multiply the period of the master clock. Period modulation is also an important challenge in synthetic molecular systems, where slow and fast components may have to be coordinated simultaneously by a single oscillator whose frequency is often difficult to tune. Circuits that can multiply the period of a clock signal (frequency dividers), such as binary counters and flip-flops, are commonly encountered in electronic systems, but design principles to obtain similar devices in biological systems are still unclear. We take inspiration from the architecture of electronic flip-flops, and we propose to build biomolecular period-doubling networks by combining a bistable switch with negative feedback modules that preprocess the c...

Circadian rhythm in mammals: time to eat & time to sleep

Abstract: Circadian rhythm is defined as rhythmic fluctuations in physiological processes which enable living organisms to make necessary arrangements for upcoming changes in the environment thereby optimizing their metabolism. Mammalian circadian clock consists of feedback(negative) and feedforward (positive) loops consisting of transcription, translation and posttranslational events. It is believed that there are two kinds of clock functioning in the body.The master clock residing in hypothalamus oscillating in conjunction with light/dark cycle whereas peripheral clocks occur in peripheral tissues and influenced by other environmental factors such as feeding. The rhythmic alterations in activities of metabolic pathways are provided by the coordinated expressions of clock genes and consequently by clock-controlled genes. The current studies indicate that consumption of food at inappropriate times as well as sleep restrictions lead to metabolic dysfunctions due to disruption of circadian rhythm which result...

Frequency-Tracking Clock Servo for Time Synchronization in Networked Motion Control Systems

Abstract: With the application of internet in manufacturing, motion control system is tend to networking. Clock synchronization is a basic requirement to guarantee capability of coordination in networked motion control systems. In this paper, we propose a frequency-tracking clock servo (FTCS) to adjust the local clock to synchronize with the reference clock. The frequency of FTCS can rapidly lock onto the reference frequency and the offset can be fully compensated within a single synchronizing cycle. Simulations and experiments are performed to validate the feasibility and superiority of FTCS. Compared with the proportional-integral clock servo, FTCS can achieve the rapid synchronized speed and better precision with low frequency of sending synchronization messages.

The space optical clocks project

Abstract: The Space Optical Clocks project aims at operating lattice clocks on the ISS for tests of fundamental physics and for providing high-accuracy comparisons of future terrestrial optical clocks. A pre-phase-A study (2007- 10), funded partially by ESA and DLR, included the implementation of several optical lattice clock systems using Strontium and Ytterbium as atomic species and their characterization. Subcomponents of clock demonstrators with the added specification of transportability and using techniques suitable for later space use, such as all-solid-state lasers, low power consumption, and compact dimensions, have been developed and have been validated. This included demonstration of laser-cooling and magneto-optical trapping of Sr atoms in a compact breadboard apparatus and demonstration of a transportable clock laser with 1 Hz linewidth. With two laboratory Sr lattice clock systems a number of fundamental results were obtained, such as observing atomic resonances with linewidths as low as 3 Hz, non-destructive detection of atom excitation, determination of decoherence effects and reaching a frequency instability of 1×10-16.

Ultrastable Multiclock Frequency Injection and Dissemination in a Ring Fiber Network

Abstract: Owing to the characteristics of ultralow loss and antielectromagnetic interference, using optical fiber to deliver time and frequency signals has been a preferred choice for high-precision clock dissemination and comparison. As a brilliant idea, one has been able to reproduce ultrastable signals from one local station to multiple users. In this paper, we take a step further and propose a concept of multiclock (in different locations) dissemination for multiterminals. By injecting frequency signals into one stabilized ring-like fiber network, the relative stabilities of 3.4 × 10−14@1 s for a master clock dissemination and 5.1 × 10−14 @1 s for a slave clock dissemination have been achieved. The proposed scheme can greatly simplify the future “N” to “N” radio-frequency dissemination network, especially in the situation of multiclock comparison.

SD-OPTS: Software-Defined On-Path Time Synchronization for Information-Centric Smart Grid

Abstract: Information-centric networking (ICN) and software defined networking (SDN) has been perceived as a promising paradigm for integrating distributed generation (DG) into smart grid networks for flexibility and dynamic features. However, flexible, controllable and reliable time synchronization still remains an open issue for supervisory control and data sensing in smart grid. Firstly, for information-centric smart grid, smart grid entities may obtain available data from caching routers, and data delivery between caching routers with edge devices results in time synchronization requirements of on-path caching routers. Without on-path time synchronization of caching routers, it may lead to maliciously fluctuations if energy data for monitoring the energy supplying and consumption are collected and traversed at an inappropriate time. Secondly, as scale expanding and network environment of smart grid becomes complex and changeable, on-path time synchronization needs a unified and dynamic management and control. To address these issues, in this paper we propose a novel scheme of software- defined on-path time synchronization (SD-OPTS) scheme for information-centric smart grid. In proposed scheme, all on-path caching routers share the time stamps from master clock and synchronize the time of local clock during one-time synchronization process. Besides, SDN controller estimates on-path caching routers' sync error, before choosing the nearest nodes to implement accurate time synchronization. The simulation results demonstrate the efficiency of software-defined on-path time synchronization scheme. The SD-OPTS scheme supports the flexibility, controllability and reliability of time synchronization.

Clock sustain in the absence of a reference clock in a communication system

Abstract: Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

A sub-microsecond clock synchronization protocol for wireless industrial monitoring and control networks

Abstract: Wireless networks are getting more and more important to industrial process monitoring in control. One of the key challenges in these domains is clock synchronization. Needed to be able to link data gathered on different devices in the network. More recently the idea of wireless closed loop controllers rose. With that even more precise clock synchronization is needed. In this paper we propose a protocol capable of sub-microsecond synchronization and clock drift compensation. The proposed protocol is inspired by the widely used PTP but was optimized for wireless networks. Our real world evaluation indicates, that clock drift is a serious challenge in networks utilizing modern microcontrollers. We also show that our approach is capable of mitigating that drift to reach a competitive degree of synchronicity.

High-precision multi-node clock network distribution

Abstract: A high precision multi-node clock network for multiple users was built following the precise frequency transmission and time synchronization of 120 km fiber. The network topology adopts a simple star-shaped network structure. The clock signal of a hydrogen maser (synchronized with UTC) was recovered from a 120 km telecommunication fiber link and then was distributed to 4 sub-stations. The fractional frequency instability of all substations is in the level of 10-15 in a second and the clock offset instability is in sub-ps in root-mean-square average.

Securing time between nodes

Abstract: Systems and methods are provided for validating time between a local clock included in the slave node of a network with a master clock included in the master node of the network. The master node determines a propagation delay between the master node and the slave node, sends a synchronization message to the slave node at a first time, determines an expected receipt time of the synchronization message at the slave node based on the first time, the determined propagation delay between the master node and the slave node, and a rate ratio of the master clock to the local clock, and sends a follow up message to the slave node, the follow up message including the first time and the expected receipt time.

Integrated circuit design method reducing clock power and integrated clock gater merged with flip-flops

Abstract: A method of generating a design for an integrated circuit includes replacing a first clock network with a second clock network in the design, wherein the second clock network is defined by a standard cell stored in a storage device. The first clock network includes a first clock gater connected to first clock sinks via intervening inverters, and the second clock network includes a second clock gater directly connected to second clock sinks without intervening inverters.

Kalman filter approaches for a mixed clock ensemble

Abstract: Clock ensembling is a promising concept for future time scale generation as robustness and stability can be considerably improved compared to master clock approaches. While ensembles consisting of the same clock types were already demonstrated to improve robustness of the generated time scale, ensembles using different clock types can clearly benefit from the advantages of the individual single clocks contributing to the time generation process. In particular, the performance of the ensemble time can be improved over a wide range of averaging times by combining clocks exhibiting superior stabilities for distinct time scales. In future, this approach could be used to integrate newly developed clock types such as e.g. optical clocks into a clock ensemble.

Robust control system and method for electric time synchronization system

Abstract: The invention relates to a robust control system and a robust control method for an electric time synchronization system. The time synchronization system comprises at least two master clock devices and a slave clock device, wherein the master clock devices are interconnected via an optical fiber; the master clock devices are interconnected with the slave clock device via the optical fiber; the time synchronization system receives an external time source signal via the master clock devices, so that safety and reliability of time source selection of the master clock devices can be ensured by ensuring the safety and reliability of the external time source signal; each master clock device is composed of a clock receiving unit, a clock unit and an output unit connected in sequence; and the time synchronization system is provided with a reliability judging module on the clock receiving unit and the clock unit.According to the system and the method provided by the invention, beginning with signal sources of the time synchronization system, signal security of the input time source is judged by introducing the plurality of external time sources, interference of the external instable signal and malicious tampering of the input time source signal are completely eradicated, and thus the most reliable time source is selected to serve as the synchronization time source of the master clock devices, and reliability of the time source signal of the master clock devices is ensured.

Clock Synchronization in IoT Network Using Cloud Computing

Abstract: The Internet of Things is a trending future technological revolution that emerging distributed computing and real-time based application and its development depends on dynamic technical innovation in a number of important fields from wireless sensors to nanotechnology. Cloud integration with IoT made things more convenient and easy. Clock synchronization between systems in a distributed network is the complex and tedious job. It is mandatory to get sync with other and source as well. There are many proposed ways of data synchronization protocols like NTP, global position system to maintain sync process between Systems or IoT devices network. In this paper, we are proposing a clock synchronization approach to sync clocks between IoTs and Cloud which are connected with each other in distributed network. Here we have used cloud service Software as a Service to collect the information to analysis and trigger the results action to IoTs. In this paper, we present the Clock Synchronization based on precision time protocol between IoTs simulation model for Omnet++ with INET framework, which allows us to check clock sync accuracy with a different network configured topologies. We have tried to minimize the clock drift with clock offset updating and with master–slave phenomena also minimize the master–slave delay. To show our simulation results we have used chunks nodes of IoTs in distributed manner placed in different places with different clock values. The simulation result shows that proposed approach works in the desired manner within ideal and network delay symmetry.

Master-salve clock synchronization method suitable for multi-synchronization domain time -triggered Ethernet

Abstract: The invention discloses a master-salve clock synchronization method suitable for the multi-synchronization domain time-triggered Ethernet. The method comprises the following steps: a cluster closest to the high-precision external clock hop count in a synchronization domain cluster receives an external PCF frame; a CM belonging to this cluster broadcasts the external PCF frame to each synchronization equipment in this cluster; the synchronization equipment belonging to this cluster receives the external PCF frame, and computes a time accuracy factor; the synchronization equipment belonging to this cluster performs time accuracy correction when the next clock synchronization time is started; and meanwhile, a clock synchronization factor is modified in a clock correction moment point of the synchronization period; an output end SM belonging to this cluster takes the curing moment of the received external PCF frame as the distribution moment so as to distribute the internal PCF frame to the next level cluster belonging to the same synchronization domain cluster; traversing other clusters in the synchronization domain clusters, and guaranteeing that the master clock and the salve clock between the clusters in the synchronization domain clusters are synchronized. By use of the method disclosed by the invention, the time accuracy calibration service is provided, and multilevel time accuracy calibration mechanism is established, the method can be extended to the multi-synchronization domain network so as to provide the clock calibration service for the large-scale time-triggered network.

Method and clock for time synchronization

Abstract: The application provides a method and clock for time synchronization. The method comprises the following steps: a first clock receives first information and second information sent by a second clock, wherein the first information is used to indicate the time level of the second clock, and the second information is used to indicate the frequency level of the second clock; after determining that the time level of the first clock is equal to the time level of the second clock, the first clock compares the frequency level of the first clock with the frequency level of the second clock to obtain a first comparison result; and the first clock determines whether the second clock is taken as a master clock of the first clock according to the first comparison result. According to the scheme, the frequency level factor is considered before determining the master clock; thereby, the above technical scheme helps to select the master clock with better quality; or, the above technical scheme helps to avoid the selection of the master clock with poorer quality.

Centralized method for realizing 1588 time synchronization on distributed system

Abstract: The invention provides a centralized method for realizing 1588 time synchronization on a distributed system, and relates to the field of 1588 time synchronization The method comprises: a master clock node sending a synchronization message, carrying t1 and t1'-t1, t1' being time when a same node wire board sends the synchronization message, a slave clock node receiving the synchronization message, marking t2' and t2, calculating a synchronization message correction time delay value; the slave clock node sending a delay request message, carrying t3 and t3'-t3, t3' being the time when the same node wire board sends the delay request message, receiving the delay request message by the master clock node, marking t4' and t4, calculating a delay request message corrected delay value, inserting the delay request message corrected delay value and the t4 into a delay response message, sending to the slave clock node, the slave clock node obtaining all timestamps and two corrected delay values, through a time synchronization algorithm, completing time synchronization The method can reduce development and debugging workload, simplifies backboard wiring, reduces synchronizing signal interference, and shows for the external by integrated time source information

Controlling system clocks in virtual machines

Abstract: Managing system clocks of virtual machines. A host system clock value of a host system clock of a host system is obtained, and a virtual machine system clock value of a system clock of a virtual machine managed by the host system is determined. The determining of the virtual machine system clock value includes using the host system clock value and a system clock adjustment value. The system clock of the virtual machine is adjusted using the virtual machine system clock value.

A method of timing loop prevention for the precision time protocol (ptp) with g.8275.1 profile

Abstract: Methods and apparatuses in a PTP network are described. A network node receives, at a first port, an Announce message from a second port of a second network node, where the Announce message includes an identifier and characteristics of a grandmaster clock, and where the grandmaster clock is a source of time for clock synchronization for a second local clock of the second network node. The network node determines whether the identifier of the grandmaster is identical to a local identifier of the local clock of the first network node. In response to determining that the identifier of the grandmaster clock is identical to the identifier of the local clock, the network node discards the Announce message received at the first port causing the characteristics of the grandmaster clock to be ignored when determining a best master clock for the first local clock.

Clock synchronization method, mobile network system, network controller and network switch

Abstract: A clock synchronization method, a mobile network system, a network controller and a network switch are provided. The method computes a round-trip delay ratio between the network controller and the network switch according to a first delay, of which the network controller transmits a packet to the network switch, and a second delay, of which the network switch transmits another packet to the network controller. The method also locks a first clock based on a time-transfer protocol with the round-trip delay ratio, wherein the first clock is synchronized with a master clock of the network controller. The method further sets the first clock being locked as a runtime clock of the network switch.

Method for clock synchronization of an industrial internet field broadband bus

Abstract: Disclosed is a method for clock synchronization of an industrial internet field broadband bus, wherein the method is applicable to an industrial internet field broadband bus architecture system including a bus controller and at least one bus terminal, the bus controller is connected with the bus terminal over a two-wire data transfer network, and the method includes steps of: electing one of the bus controller and the bus terminal as a best master clock; determining whether an IP address of the device of the best master clock is the same as an IP address of the bus controller; if so, then determining the bus controller as a master device of clock synchronization, and transmitting by the bus controller a synchronization message to the bus terminal for clock synchronization; and otherwise, returning to the step of electing one of the bus controller and the bus terminal as the best master clock.

An enhanced end-to-end transparent clock mechanism for the kernel-based virtual machines

Abstract: Keeping a high-precision time base in cloud clusters is still a big challenge, even using the Precision Time Protocol version 2 (PTPv2) specified in IEEE 1588. One of the main factors on this issue is that too many uncertainties in the network path from the master clock to the slave one, which is likely residing on the Kernel-based Virtual Machine (KVM). The Transparent Clock (TC) of PTPv2 may be useful to solve this issue. However, at present the network I/O path in the virtual machine environment has not been considered in such works, which seriously affect the performance of the synchronization accuracy. In this work, we make improvements in the kernel network stack to manipulate the PTP frames to record the residence time for the path from the physical machine to the virtual machine, making its network I/O architecture an End-to-End Transparent Clock (E2E TC). Although the idea of E2E TC for more accurate synchronization is not new, there is no such implementation publicized for the virtualized environment, as far as we know. The proposed mechanism is specifically tailored to make latency corrections for the neglected routing path between the physical Network Interface Card (NIC) and the virtual machines. Extensive experiments and tests show that this approach makes quite significant improvement of about 50%.