Showing papers on "Master clock published in 2018"

GET: A generic electronics system for TPCs and nuclear physics instrumentation

Abstract: General Electronics for TPCs (GET) is a generic, reconfigurable and comprehensive electronics and data-acquisition system for nuclear physics instrumentation of up to 33792 channels. The system consists of a custom-designed ASIC for signal processing, front-end cards that each house 4 ASIC chips and digitize the data in parallel through 12-bit ADCs, concentration boards to read and process the digital data from up to 16 ASICs, a 3-level trigger and master clock module to trigger the system and synchronize the data, as well as all of the associated firmware, communication and data-acquisition software. An overview of the system including its specifications and measured performances are presented.

Requirements for Secure Clock Synchronization

Abstract: This paper establishes a fundamental theory of secure clock synchronization. Accurate clock synchronization is the backbone of systems managing power distribution, financial transactions, telecommunication operations, database services, etc. Some clock synchronization (time transfer) systems, such as the global navigation satellite systems, are based on one-way communication from a master to a slave clock. Others, such as the network transport protocol, and the IEEE 1588 precision time protocol (PTP), involve two-way communication between the master and slave. This paper shows that all one-way time transfer protocols are vulnerable to replay attacks that can potentially compromise timing information. A set of conditions for secure two-way clock synchronization is proposed and proved to be necessary and sufficient. It is shown that IEEE 1588 PTP, although a two-way synchronization protocol, is not compliant with these conditions, and is therefore insecure. Requirements for secure IEEE 1588 PTP are proposed, and a second example protocol is offered to illustrate the range of compliant systems.

Extracellular Vesicles: Potential Participants in Circadian Rhythm Synchronization.

Abstract: The circadian rhythm (CR) is a set of autonomous endogenous oscillators. Exposure to the 24-hour day-night cycle synchronizes our CR system, maintaining homeostasis and human health. Several mechanisms for the CR system have been proposed, including those underlying the function (transcriptional-translational negative-feedback loops, or TTFLs), mechanisms regulating the TTFLs, and the mechanism by which the "server clock" is synchronized to environmental time. Several pathways downstream of the "server clock" perform well-characterized biological functions. However, the synchronization between the "server clock" (the endogenous master clock seated in the suprachiasmatic nucleus within the hypothalamus) and the "client clock" (imbedded in nearly every cell in the form of interlocking TTFLs) is difficult to explain with current theories. Extracellular vesicles (EVs), which are involved in intercellular communication and have recently been found to participate in regulation of the "client clock", might be the answer to this question. In this review, we summarize the current knowledge of CRs, TTFLs, and EVs, examine research findings about the functions of EVs in the CR system, and discuss the issues requiring attention in future research.

Time synchronization system

Abstract: A time synchronization system includes master nodes and slave nodes configured to correct a local slave clock by synchronizing time with time in a local master clock. A first master node corrects a first local master clock at predetermined periodic intervals by synchronizing with a timing synchronization signal from a source clock node having a source clock. If a second local master clock has a greater error from the source clock than the error in the first local master clock, the second master node performs first correction by synchronizing time with time in the first local master clock and performs second correction by synchronizing with the timing synchronization signal from the source clock node on condition that an error in the second local master clock is within a predetermined range after the first correction has been performed.

Optical time distributor and process for optical two-way time-frequency transfer

Abstract: An optical time distributor includes: a master clock including: a master comb; a transfer comb; and a free-space optical terminal; and a remote clock in optical communication with the master clock via a free space link and including: a remote comb that produces: a remote clock coherent optical pulse train output; a remote coherent optical pulse train; a free-space optical terminal in optical communication: with the remote comb; and with the free-space optical terminal of the master clock via the free space link, and that: receives the remote coherent optical pulse train from the remote comb; receives the master optical signal from the free-space optical terminal of the master clock; produces the remote optical signal in response to receipt of the remote coherent optical pulse train; and communicates the remote optical signal to the free-space optical terminal of the master clock.

System and method of clock management in a packet data network

Abstract: There is provided a method of clock management in a packet data network (PDN) implementing a time-transfer protocol and a clock controller configured to operate therein. The clock controller is configured to: obtain topology data informative of a master clock node and a slave clock node constituting end points of a PTP path in the PDN and further informative of at least part of transit nodes of said PTP path; periodically obtain data informative of queue size and link rate characterizing, during a collection period, the at least part of transit nodes in master-slave (MS) and slave-master (SM) directions; for each collection period, use the obtained queue-related data to estimate queue-induced delay asymmetry of the PTP path; and send the estimated value of queue-induced delay asymmetry to the slave node, the estimated value to be used by a clock residing on the slave node as delay asymmetry correction parameter.

Distributed network clock synchronization method

Abstract: The invention relates to a distributed network clock synchronization method. The distributed network clock synchronization method is applied to a distributed network, and comprises the steps of: determining a master device and a slave device through a clock selection algorithm; measuring the link delay of the master device and the slave device; obtaining the time difference of the master device and the slave device through the link delay; and completing clock synchronization of the slave device through the master device and the time difference. According to the embodiment of the invention, thelink delay is measured; furthermore, the time difference is calculated through the link delay; then, clock synchronization is realized; therefore, the clock synchronization precision of the distributed network is up to the nanosecond level; furthermore, the distributed network has relatively high stability; namely, when the equipment in the distributed network is abnormal, the distributed networkcan adaptively adjust the network structure within a short time; a proper master clock is re-selected; and furthermore, clock synchronization is completed.

NavIC receiver clock offsets estimation with common view master clock method

Abstract: The current manuscript proposes a new methodology for receiver clock offset estimation in IRNSS (Indian Regional Navigation Satellite System) which is also known as NavIC (Navigation Indian Constellation). This new methodology has been designed by clubbing the master clock concept with the traditional common view time transfer method and therefore it has been named as Common View Master Clock Method (CVMCM). The proposed methodology is intended to share the reference time uniformly and precisely across all the receiver clocks of IRNSS. The IRNSS receivers equipped at IRIMS (IRNSS Range and Integrity Monitoring Stations) acquire IRNSS satellite signals and generate code and carrier phase measurements on L5 and S frequencies. For ease of convenience, this range measurements and broadcast navigation messages are converted to standard RINEX (Receiver Independent Exchange) format in the form of RINEX observation files and RINEX navigation files respectively. As IRNWT1 (IRNSS Network Time Facility Banga...

Time synchronization and scheduling method for vehicular Ethernet

Abstract: The invention relates to a time synchronization and scheduling method for a vehicular Ethernet. The time synchronization and scheduling method for the vehicular Ethernet comprises the steps of: S1, time synchronization starting optimization: performing local clock deviation correction by calling locally stored link delay, simultaneously, shortening a node synchronization message period, and accelerating a synchronization process; S2, static master clock selection: determining synchronous messages of all nodes, and determining a clock having the highest priority as a master clock; S3, synchronous redundant path selection: performing redundant path selection by adopting a clock correction message section in the synchronous messages, and filtering the delay time; and S4, real-time double-window scheduling: distributing messages sent by sending nodes into three priority queues, and dividing time windows into two periods, so that messages of all the sending nodes are sent synchronously. Compared with the prior art, the time synchronization and scheduling method for the vehicular Ethernet disclosed by the invention has the advantages of improving the practical synchronization stability,ensuring real-time scheduling and the like.

Protected real time clock with hardware interconnects

Abstract: Disclosed herein are systems and methods for initializing and synchronizing a protected real time clock via hardware connections. For example, in some embodiments, a protected real time clock on a trusted execution environment may initialize via a hardware connection to a master clock, which is synchronized to a trusted time source via a hardware connection. In some embodiments, a protected real time clock on a trusted execution environment may initialize to a master clock during a system hardware reset sequence. In some embodiments, before a system is running normally, a real time clock on an integrated Intellectual Property agent may initialize and synchronize to a protected real time clock via a hardware connection. In some embodiments, after a system is running normally, a real time clock on a discrete device may initialize and synchronize to a protected real time clock via a hardware connection.

A Synchronization Method for Local Applications of EtherCAT Master-Slave in Open CNC System

Abstract: A synchronization method for local applications of EtherCAT master-slave is proposed in this paper. Firstly, initial shift time is defined according to the communication structure of EtherCAT master-slave in open CNC system. Then, the initial shift time and clock rate ratio between master clock and reference clock is calculated for initialization of SYNC0 signal. After that, master’s cycle remaining time is defined for adjusting the master cycle time. Finally, reference shift time and measuring shift time is defined and calculated. The time difference of them is used as the basis for compensating the cycle remaining time. The master’s cycle time is adjusted by compensating the cycle remaining time and the synchronization of local applications of EtherCAT master-slave is realized by adjusting the master’s cycle. Experimental results showed that good synchronization effect of local applications of EtherCAT master-slave can be achieved in open CNC system.

Time synchronization method, master clock device, slave clock device and time synchronization system

Abstract: The invention provides a time synchronization method, a master clock device, a slave clock device and a time synchronization system. When a first synchronous clock message is completely generated anda sending condition is triggered, the master clock device inserts the first synchronous clock message in a first multiframe to send the first synchronous clock message to a to-be-synchronized slave clock device; and after the slave clock device receives the first synchronous clock message, when a second synchronous clock message is completely generated and a frame sending condition is satisfied, the slave clock device inserts the second synchronous clock message in a second multiframe to send the second synchronous clock message to the master clock device, therefore the recorded sending timestamp when the multiframe is actually sent can be close to the time when the synchronous clock message is actually sent from the device. The error between the actual sending time of the synchronous clock message recorded by the device and the time when the synchronous clock message is actually sent from the device can be reduced as much as possible, and the accuracy of subsequent clock synchronization can be further improved.

Clock recovery device with switchable transient non-linear phase adjuster

Abstract: A clock recovery device recovers a master clock over a packet network from incoming synchronization packets. A frequency locked loop generates a control input to a controlled oscillator, which generates an output clock. The frequency locked loop is responsive to pure offset information obtained from the incoming synchronization packets. A transient phase adjuster extracts information from the incoming synchronization packets taking into account transit delays to effect fast frequency adjustment of the control input and to provide a phase adjustment input to the frequency locked loop. A secondary phase path is selectable in response to de-activation of the transient phase adjuster to provide a phase correction to the control input derived from said pure offset information when the transient phase adjuster is inactive.

System, apparatus and method for programmably controlling generation of a notch at a radio frequency using arbitrary pulse pairing

Abstract: In one embodiment, a radio receiver includes: a programmable frequency synthesizer to generate a first clock signal; a first frequency divider to divide the first clock signal to generate a master clock signal; a second frequency divider to divide the master clock signal to generate a mixing signal; and a mixer to downconvert a radio frequency (RF) signal to a second frequency signal using the mixing signal. A voltage converter to couple to the radio receiver includes a switch controllable to switchably couple a first voltage to a storage device and a pulse generator to generate at least one pulse pair formed of a first pulse and a second pulse substantially identical to the first pulse, when a second voltage is less than a first threshold voltage, the second pulse separated from the first pulse by a pulse separation interval.

Improved reference clock connection interface for prototype IEEE 1588 master clocks

Abstract: In this paper we present a fundamentally redesigned Global Navigational Satellite System (GNSS) receiver to master clock interface based on our previous design for IEEE 1588 Precision Time Protocol (PTP) master clocks. The new design is optimized for modern timing GNSS receivers; including GPS, Galileo, and GLONASS GNSS; which provide better timing accuracy and precision than previous generic navigational or even older timing GPS receivers. The new design is required because new timing GNSS receivers have lower than 10 ns error while the errors introduced by the previous interface solution is one or two magnitudes bigger than that, causing degraded system wide timing performance for new systems. Better performance is achieved by an error source analysis and a delicate component selection based on the results of the analysis, and in addition, timing oriented PCB routing. Furthermore, the new design is more compact, integrated with a CPU board, and therefore, ready to be deployed in prototype applications. The paper also provides an initial performance evaluation of the improved reference clock interface.

Synchronisation in a communications network

Abstract: A spread spectrum system is used for transmitting data to and from devices operable as sensors and actuators in a distributed system. Each device is allocated a respective spread spectrum code, or combination of such codes in a branched network, for decoding and decoding the data (52, 58) and has a corresponding encoder/decoder in a central control system operating the same spread spectrum codes, the encoded data relating to the individual devices all being aggregated over a shared channel. To reduce the decoding overhead, the coding and encoding processes are synchronised using a pulse train of a master clock transmitted by a broadcasting antenna(400) and the devices and control centre receive, decode and operate according to time based on the pulse train. An offset may be calculated (83) to allow for distance from the transmitter, based on received power (81), GPS, or other data.

Task level synchronization method based on network communication

Abstract: The invention discloses a task level synchronization method based on network communication. The method is applied to a mutual communication process of master controllers. The method comprises the steps that S1, link transmission delay and offset time between a master clock and a slave clock are measured; S2, a host sends a data frame for starting a slave task within a sending window period of a next task period, after a slave receives the data frame, the slave calculates starting time of a next task of the host according to the time contained in the starting frame, sets starting time of the task of the slave and waits for starting; and S2, the data frame interacted between the host and the slave periodically comprises current host task starting time information, and the slave periodicallycorrects an offset coefficient, thereby finishing periodic synchronization adjustment. Through utilization of the task level synchronization method based on the network communication, the technical effect of reducing the system response time without additionally increasing a hardware circuit is achieved.

Research on Rubidium Atomic Clock Disciplined Method Based on LabWindows/CVI

Abstract: With the increasing demand for stable, accurate and reliable frequency standard sources in the field of measurement and control, rubidium atomic clocks with strong environmental adaptability and low price are widely used but are limited by long-term frequency drift. In this paper, 1PPS signal as the reference signal provided by the National Time Service Center, and a rubidium atomic clock frequency automatic calibration system was designed and implemented. Experimental results show that, the clock difference is less than 8ns between the rubidium atomic clock and the master clock of the NTSC, the Modified Allan Deviation is 1.83E-12@100s, and 2.70E-13@10000s. The experiment proves that the self-calibrating frequency system gives rubidium atomic clock a good accuracy and long-term stability.

Methods and systems for determining optimal packets

Abstract: This invention relates to timing message selection techniques that can be used in conjunction with a clock recovery mechanism to mitigate the effects of packet delay variation on timing messages exchanged over a packet network, particularly when seeking to synchronize the time of a clock in a slave device to that of a master clock. The selection techniques allow the identification of optimal or minimally-delayed timing messages which can subsequently be used in timing synchronisation. Embodiments of the invention provide techniques which identify optimal timing messages in both forward and reverse directions which are then processed to form composite timing messages which are used in a frequency estimation algorithm. Timing messages selected by the methods of the invention are particularly useful in phase synchronization between the master and slave clocks.

Passive Clock Synchronization for TDOA-based UWB Indoor Positioning Systems

Abstract: This paper considers the problem of estimating the parameters of the quadratic clock model to achieve clock synchronization for time difference of arrival (TDOA)-based ultra wideband (UWB) indoor positioning systems. It is assumed that a reference node with a master clock is available and as a result, we are able to synchronize an arbitrary number of receiving nodes in a passive manner using wireless connections. A practical algorithm for identifying the quadratic clock model parameters is proposed by tailoring and enhancing an existing solution. In particular, the clock synchronization is accomplished in two steps, where in the first step, the clock drift is estimated while the clock offset and skew are found in the second step. Both processing steps utilize the closed-form weighted least squares (WLS) optimization only. Method for simplifying the evaluation of the weighting matrices is introduced and is shown to be capable of reducing the computational time greatly. Simulation results show that the newly developed clock parameters estimation technique is approximately efficient in the sense that it can attain the Cramer-Rao lower bound (CRLB) performance. Experiments using data from a real TDOA-based UWB indoor localization system further confirm the advantage of using the quadratic clock model over the simplified linear clock model in maintaining long-term synchronization.

SDH transmission method of IEC61588

Abstract: The invention discloses an SDH transmission method of IEC61588. S1: ethernet bit stream including a PTP protocol message is transmitted by a primary PTP master clock through the ethernet. S2: the ethernet bit stream of S1 is converted to E1 HDB3 bit stream by a protocol converter. S3: the E1 HDB3 bit stream of S2 is transmitted by the SDH internet step by step. S4: the E1 HDB3 bit stream of S3 isconverted to the ethernet bit stream by the protocol converter. S5: the PTP protocol message is obtained by a slave clock from the ethernet bit stream of S4, and time of the slave clock is adjusted according to a hardware time stamp of the PTP protocol message. The SDH transmission method of IEC61588 utilizes the SDH transmission to transmit clock signal so that cost is effectively saved, and precision of the PTP networking is high so that nanometer precision is achieved through precise compensation.

Clock source reliability safeguard mechanism suitable for master-slave mode time synchronization method

Abstract: The invention provides a clock source reliability safeguard mechanism suitable for a master-slave mode time synchronization method and belongs to the technical field of onboard network communication.The master-slave mode time synchronization method has the advantages of being simple, easy to realize, high in efficiency and the like, but also has a problem of low reliability. If a clock source isin fault, the whole time synchronization process goes wrong or paralyzes. In order to reduce negative influences from the clock source fault to the master-slave mode time synchronization, a clock ratespecific ratio between a clock main node and a clock slave node is adopted as a judgment basis to judge whether the clock state of the master clock and the clock state of the slave node are in consistence; then whether the state of the current clock source is normal or not and whether the clock reference source is necessary to select again are determined through a voting mode. Meanwhile, adjacentslave nodes monitor the running state of each other to reduce the influence from wrong nodes to the voting result of the clock source.

Secure time-to-live

Abstract: Determining whether to allow access to a message is disclosed. A message is received from a sender. The message is associated with a first time-to-live (TTL) value. A determination is made that the first time-to-live value has not been exceeded. The determination is made at least in part by obtaining an external master clock time. In response to the determination, access is allowed to the message.

Out-Degree Based Clock Synchronization In Wireless Networks Using Precision Time Protocol

Abstract: In this paper, an extension of Precision Time Protocol (PTP) to enable energy-efficient clock synchronization between the nodes within Wireless Sensor Network (WSN) is proposed. PTP is nanosecond accuracy clock synchronization protocol in which nodes are organized in master-slave hierarchy on the basis of clock accuracy by means of Best Master Clock (BMC) algorithm. The algorithm considers clock accuracy to select best clock in the system. A novel modification of IEEE 1588 BMC algorithm for energy-constraint multi-hop WSN has been proposed to reduce clock convergence time and energy needed by considering out-degree of clocks without sacrificing synchronization accuracy. The new algorithm results in energy efficient clock synchronization that makes it most appropriate for low-power multi-hop wireless sensor networks. We present NS-3 simulation data that confirms the effectiveness of work.

Block diagram of the multichannel master generator of the adaptive information-measuring system for vibro tests of the radioelectronic equipment

Abstract: To improve the efficiency of test for determining dynamic characteristics of the structure of electronic tools developed by specifying multi-channel generator. The generator is part of the information-measuring system intended for the dynamic vibration. The description of the structural scheme of the device and principle of operation of information-measuring system. The master clock consists of four independent channels. Each channel is built on the basis of independent modules implementing digital synthesis of frequencies in the range from 1 to 12000 Hz. The chosen architecture defines a multi-channel generator allows you to expand the possibilities of vibration test equipment with separate control parameters for each channel. The proposed structural scheme allows, for each channel, to specify individually the initial phase, the amplitude and frequency of the output harmonic signal. It is also possible to choose the form of the output signal and changes the frequency of the signal at a speed not less than 2 octaves per minute. The latter achieved through the using of modern DDS modules that are optimized to the digital interface, and the application of each DDS module registers two separate frequencies. To optimize the parameters switch between frequency registers in the modules of the applied method, Ramped-FSK.

Robust Time Scale Design and Implementation for Telescope Time in a Remote Desert Environment

Abstract: A clock ensemble for tracking time for a next generation radio telescope (MeerKAT) is being built, to be able provide robust timing w.r.t. UTC over long periods (~10 years) in a remote desert environment at the phase center of the MeerKAT-the master clock timing edge as supplied to the telescope is called the KTT (Karoo Telescope Time). This system consists out of two masers, two GPS/Rb clocks, a high stability crystal, and two time transfer systems to link with the National Metrology Institute of South Africa (NMISA), and hardware based clock selection devices to enable signal routing of the master clock pulse per second and 10MHz frequency reference to the telescope. The system is designed for high availability by making use of redundant climate control, multiple power backup and redundant software logging. Data on the initial time tracking capabilities are presented. Low phase noise and drift of the system for supplying synthesizers has been achieved via vibration isolation, and temperature stabilization in purpose built infrastructure as is shown in data. The system timing is calculated post facto (as opposed to real time realization) due to the lowest timing uncertainty needed on pulsar timing data especially for gravitational wave work. The system architecture and initial measurement on the system is presented.

FPGA-based interface signal remapping method

Abstract: An FPGA-based interface signal remapping method, relates to the technical field of nuclear power system, and solves the technical problems of poor reliability, readability and debuggability in the prior art. The method comprises dividing an internal programmable logic of an FPGA chip into two independent modules, with one module being an I/O module and the other module being a Core module, using the I/O module to process signal excursion occurring when an external signal is input to or output from the FPGA chip, signal collision caused by line multiplexing, metastable state in a data transmission process, and a data transmission error between asynchronous clock domains, using the Core module to implement logical processing and computing; and introducing a master clock signal outside the FPGA chip into the FPGA chip through a global clock pin of the FPGA chip. The method provided in the invention is suitable for a nuclear power protection system platform.

Time synchronization system and time synchronization system method

Abstract: PROBLEM TO BE SOLVED: To reduce a lag between standard time delivered by each master clock and true standard time in a configuration where a plurality of master clocks are distributedly arranged.SOLUTION: A time synchronization system 10 comprises a plurality of master clocks 20 (20A-20F) for delivering standard time received from a GPS satellite 40 to slave devices 50 (50A-50B). Each master clock 20 receives a first standard time candidate value from the GPS satellite 40, while also receiving second standard time candidate values from the other master clocks 20 within the time synchronization system 10, calculates a standard time estimated value that is estimated to be a true standard time using these standard time candidate values, and delivers the calculated standard time estimated value to the slave devices 50. Each master clock 20, furthermore, transmits the standard time estimated value of their own as a second standard time candidate value in the other master clocks 20.SELECTED DRAWING: Figure 1

Precise clock synchronization implementation method based on PTPd2 protocol

Abstract: The invention relates to a precise clock synchronization implementation method based on the PTPd2 protocol, belonging to the field of communication technology and computer networks. The invention realizes precise clock synchronization through an interactive communication message of master and slave clock devices, and the PTPd2 protocol can obtain an precise timestamp of the message arriving at thenetwork driver layer of the master and slave clock devices; compared with the timestamp obtained by the NTP protocol at the application layer, the interference of the protocol stack can be effectively avoided; at the same time, by capturing the time of the message reaching the MAC layer of the master and slave clock devices, and compensating for the delay and jitter generated by transmitting themessage from the network driver layer to the MAC layer in the master and slave clock devices, the clock synchronization precision can be improved. Tests show that when the master clock device and slave clock device are directly connected through a network cable, the parameters are reasonably set and the boundary time is compensated, the clock synchronization precision can reach 19[Mu]s; the universality is good; and the precise clock synchronization implementation method based on the PTPd2 protocol is easy to implement.