scispace - formally typeset
Search or ask a question

Showing papers on "Memistor published in 2022"


Journal ArticleDOI
TL;DR: In this paper, a multilayer resistive switching (RS) and neuromorphic characteristics emerges as a promising paradigm to build power-efficient computing hardware for high density data storage memory and artificial intelligence.

38 citations


Journal ArticleDOI
Jia-xin Shao1
TL;DR: In this article , a multilayer resistive switching (RS) and neuromorphic characteristics emerges as a promising paradigm to build power-efficient computing hardware for high density data storage memory and artificial intelligence.

32 citations


Journal ArticleDOI
01 May 2022
TL;DR: In this paper , the simplification of the JART memristor model, a generic physics-based model of Valence Change Mechanism (VCM) memristors, is presented.
Abstract: Memristors are promising nanoelectronic devices for the implementation of future AI-driven sensor-processor electronic systems, which are essential for the ongoing digitalization of our world. Accurate and computationally cost-effective models for the manufactured memristors are essential for the design of such systems, especially for the simulation of large circuits. In this brief we address the simplification of the JART memristor model, a generic physics-based model of Valence Change Mechanism (VCM) memristors which accurately describes the dynamic behavior of fabricated memristor devices. Furthermore, the proposed model and simplification methodology have the potential to capture the dynamics of a wide range of memristor devices. Importantly, the implicit description of the current through the memristor is replaced by an explicit mathematical relationship. The proper reproduction of memristor dynamics, verified by applying the system-theoretic Dynamic Route Map (DRM) graphical analysis tool, applicable to first-order systems, can be observed through the proposed simplified model and enables the time-efficient simulation of large arrays of VCM devices.

12 citations


Journal ArticleDOI
Han Bao, Ruoyu Ding, Men Hua, Huagan Wu, Bei Chen 
TL;DR: In this paper , a two-memristor-based jerk (TMJ) system is presented, and the authors study complex dynamical effects induced by memristor and non-Memristor initial conditions therein.
Abstract: Memristor-based systems can exhibit the phenomenon of extreme multi-stability, which results in the coexistence of infinitely many attractors. However, most of the recently published literature focuses on the extreme multi-stability related to memristor initial conditions rather than non-memristor initial conditions. In this paper, we present a new five-dimensional (5-D) two-memristor-based jerk (TMJ) system and study complex dynamical effects induced by memristor and non-memristor initial conditions therein. Using multiple numerical methods, coupling-coefficient-reliant dynamical behaviors under different memristor initial conditions are disclosed, and the dynamical effects of the memristor initial conditions under different non-memristor initial conditions are revealed. The numerical results show that the dynamical behaviors of the 5-D TMJ system are not only dependent on the coupling coefficients, but also dependent on the memristor and non-memristor initial conditions. In addition, with the analog and digital implementations of the 5-D TMJ system, PSIM circuit simulations and microcontroller-based hardware experiments validate the numerical results.

12 citations


Journal ArticleDOI
TL;DR: In this article , the authors review the state of the art of multi-state memristor technologies and their associated CMOS/Memristor circuit design, and discuss the challenges regarding device imperfection factors, modelling, peripheral circuit design and layout.
Abstract: Memristors show great potential for being integrated into CMOS technology and provide new approaches for designing computing-in-memory (CIM) systems, brain-inspired applications, trimming circuits and other topologies for the beyond-CMOS era. A crucial characteristic of the memristor is multi-state (also often referred as multibit, and multi-level) switching. Memristors are capable of representing information in an ultra-compact fashion, by storing multiple bits per device. However, certain challenges remain in multi-state memristive circuits and systems design such as device stability and peripheral circuit complexity. In this paper, we review the state of the art of multi-state memristor technologies and their associated CMOS/Memristor circuit design, and discuss the challenges regarding device imperfection factors, modelling, peripheral circuit design and layout. We present measurement results of our in-house fabricated multi-state memristor as an example to further illustrate the feasibility of applying multi-state memristors in CMOS design, and demonstrate their related future applications such as multi-state memristive memories in machine learning, memristive neuromorphic applications, trimming and tuning circuits, etc. In the end, we summarize past and present efforts done in this field and envisage the direction of multi-state memristor related research.

8 citations


Journal ArticleDOI
TL;DR: Li-based composite memristor (LCM) as mentioned in this paper is a Li-doped TiO2 as a Li reservoir and Li4Ti5O12 as the insulating phase, where resistive switching correlates with the change in the relative fraction of the metallic and insulating phases.
Abstract: Emerging energy-efficient neuromorphic circuits are based on hardware implementation of artificial neural networks (ANNs) that employ the biomimetic functions of memristors. Specifically, crossbar array memristive architectures are able to perform ANN vector-matrix multiplication more efficiently than conventional CMOS hardware. Memristors with specific characteristics, such as ohmic behavior in all resistance states in addition to symmetric and linear long-term potentiation/depression (LTP/LTD), are required in order to fully realize these benefits. Here, we demonstrate a Li-based composite memristor (LCM) that achieves these objectives. The LCM consists of three phases: Li-doped TiO2 as a Li reservoir, Li4Ti5O12 as the insulating phase, and Li7Ti5O12 as the metallic phase, where resistive switching correlates with the change in the relative fraction of the metallic and insulating phases. The LCM exhibits a symmetric and gradual resistive switching behavior for both set and reset operations during a full bias sweep cycle. This symmetric and linear weight update is uniquely enabled by the symmetric bidirectional migration of Li ions, which leads to gradual changes in the relative fraction of the metallic phase in the film. The optimized LCM in ANN simulation showed that exceptionally high accuracy in image classification is realized in fewer training steps compared to the nonlinear behavior of conventional memristors.

7 citations


Journal ArticleDOI
TL;DR: In this article , the authors demonstrate a flexible memristor with a record high 106 ON/OFF ratio, which is induced by sequential processes of Schottky barrier modification at the contact interface and filament formation inside the electrolyte.
Abstract: Flexible memristors hold great promise for flexible electronics applications but are still lacking of good electrical performance together with mechanical flexibility. Herein, we demonstrate a full-inorganic nanoscale flexible memristor by using free-standing ductile α-Ag2S films as both a flexible substrate and a functional electrolyte. The device accesses dense multiple-level nonvolatile states with a record high 106 ON/OFF ratio. This exceptional memristor performance is induced by sequential processes of Schottky barrier modification at the contact interface and filament formation inside the electrolyte. In addition, it is crucial to ensure that the cathode junction, where Ag+ is reduced to Ag, dominates the total resistance and takes the most of setting bias before the filament formation. Our study provides a comprehensive insight into the resistance-switching mechanism in conductive-bridging memristors and offers a new strategy toward high performance flexible memristors.

6 citations


Journal ArticleDOI
TL;DR: In this paper , a novel electrochemical metallization memristor based on solution-processed Pt/CuI/Cu structure is proposed and demonstrated, with a high resistance switching ratio of 1.53 × 107.
Abstract: Memristors are intensively studied as being regarded as the critical components to realize the in‐memory computing paradigm. A novel electrochemical metallization memristor based on solution‐processed Pt/CuI/Cu structure is proposed and demonstrated in this work, with a high resistance switching ratio of 1.53 × 107. Owing to the efficient drift paths provided by Cu vacancies for Cu cations in CuI, very small operating voltages (Vset = 0.64 V and Vreset = −0.19 V) are characterized, contributing to ultralow standby power consumption of 9 fW and per set transition of 8.73 µW. Using CuI memristor arrays, a set of Boolean logic operations and a half‐adder are implemented. Moreover, by building the model for a 75 × 48 one‐transistor‐one‐memristor array, the feasibility of hardware encryption and decryption for images is verified. All these demonstrate that solution‐processed CuI memristors possess great potential in constructing energy‐efficient logic‐in‐memory computing architectures.

5 citations


Journal ArticleDOI
TL;DR: For implementing edge-intelligence hardware with memristor crossbars, various techniques such as quantization, training, parasitic resistance correction, and low-power crossbar programming, and so on are reviewed.
Abstract: In the internet-of-things era, edge intelligence is critical for overcoming the communication and computing energy crisis, which is unavoidable if cloud computing is used exclusively. Memristor crossbars with in-memory computing may be suitable for realizing edge intelligence hardware. They can perform both memory and computing functions, allowing for the development of low-power computing architectures that go beyond the von Neumann computer. For implementing edge-intelligence hardware with memristor crossbars, in this paper, we review various techniques such as quantization, training, parasitic resistance correction, and low-power crossbar programming, and so on. In particular, memristor crossbars can be considered to realize quantized neural networks with binary and ternary synapses. For preventing memristor defects from degrading edge intelligence performance, chip-in-the-loop training can be useful when training memristor crossbars. Another undesirable effect in memristor crossbars is parasitic resistances such as source, line, and neuron resistance, which worsens as crossbar size increases. Various circuit and software techniques can compensate for parasitic resistances like source, line, and neuron resistance. Finally, we discuss an energy-efficient programming method for updating synaptic weights in memristor crossbars, which is needed for learning the edge devices.

4 citations


Journal ArticleDOI
TL;DR: This work engineered the device stack to achieve a much-improved uniformity in the relaxation time and implemented the hierarchy of time surfaces (HOTS) algorithm to utilize the tunable and uniform relaxation behavior for spike generation.
Abstract: A diffusive memristor is a promising building block for brain-inspired computing hardware. However, the randomness in the device dynamics limits the wide-range adoption of diffusive memristors in large arrays. In this work, we engineered the device stack to achieve a much-improved uniformity in the relaxation time (standard deviation σ reduced from ∼12 to ∼0.32 ms). We further connected the memristor with a resistor or a capacitor and tuned the relaxation time between 1.13 μs to 1.25 ms, ranging from three orders of magnitude. We implemented the hierarchy of time surfaces (HOTS) algorithm to utilize the tunable and uniform relaxation behavior for spike generation. We achieved 77.3% accuracy in recognizing moving objects in the neuromorphic MNIST (N-MNIST) dataset. Our work paves the way for building emerging neuromorphic computing hardware systems with ultralow power consumption. This article is protected by copyright. All rights reserved.

4 citations


Journal ArticleDOI
Zhang Zhang, Ao Xu, Chao-You Li, Gang Liu, Xin Cheng 
TL;DR: In this article , the authors proposed a mathematical model of the three-valued memristor with nonlinear and symmetric hysteresis loops and constructed a circuit emulator with fundamental components.

Journal ArticleDOI
Wu-Yang Zhu, Yifei Pu, Bo Liu, Bo Yu, Jiliu Zhou 
TL;DR: Fractional-order memristor calculus has the characteristics of non locality, weak singularity and long term memory which traditional integer-order calculus does not have, and can accurately portray or model real-world problems better than the classic integer order calculus as mentioned in this paper .
Abstract: The memristor is also a basic electronic component, just like resistors, capacitors, and inductors. It is a nonlinear device with memory characteristics. In 2008, with HP’s announcement of the discovery of the TiO2 memristor, the new memristor system, memory capacitor(memcapacitor) and memory inductor(meminductor) were derived. Fractional-order calculus has the characteristics of non locality, weak singularity and long term memory which traditional integer-order calculus does not have, and can accurately portray or model real-world problems better than the classic integer-order calculus.In recent years, researchers have extended the modeling method of memristor by fractional calculus, and proposed the fractional-order memristor, but its concept is not unified. This paper reviews the existing memristive elements, including integer-order memristor systems and fractional-order memristor systems. We analyze their similarities and differences, give the derivation process, circuit schematic diagrams, and an outlook on the development direction of fractional-order memristive elements.

Journal ArticleDOI
TL;DR: The results show that compared with the state-of-the-art technology, the memory designed in this paper has better storage density and read–write speed and when it is applied to image storage, it achieves the effect of no distortion and fast storage.
Abstract: As a new type of nonvolatile device, the memristor has become one of the most promising technologies for designing a new generation of high-density memory. In this paper, a 4-bit high-density nonvolatile memory based on a memristor is designed and applied to image storage. Firstly, a memristor cluster structure consisting of a transistor and four memristors is designed. Furthermore, the memristor cluster is used as a memory cell in the crossbar array structure to realize the memory design. In addition, when the designed non-volatile memory is applied to gray scale image storage, only two memory cells are needed for the storage of one pixel. Through the Pspice circuit simulation, the results show that compared with the state-of-the-art technology, the memory designed in this paper has better storage density and read–write speed. When it is applied to image storage, it achieves the effect of no distortion and fast storage.

Journal ArticleDOI
TL;DR: Fractional-order memristor calculus has the characteristics of non-locality, weak singularity and long term memory which traditional integer-order calculus does not have, and can accurately portray or model real-world problems better than the classic integer order calculus as discussed by the authors .
Abstract: The memristor is also a basic electronic component, just like resistors, capacitors and inductors. It is a nonlinear device with memory characteristics. In 2008, with HP’s announcement of the discovery of the TiO2 memristor, the new memristor system, memory capacitor (memcapacitor) and memory inductor (meminductor) were derived. Fractional-order calculus has the characteristics of non-locality, weak singularity and long term memory which traditional integer-order calculus does not have, and can accurately portray or model real-world problems better than the classic integer-order calculus. In recent years, researchers have extended the modeling method of memristor by fractional calculus, and proposed the fractional-order memristor, but its concept is not unified. This paper reviews the existing memristive elements, including integer-order memristor systems and fractional-order memristor systems. We analyze their similarities and differences, give the derivation process, circuit schematic diagrams, and an outlook on the development direction of fractional-order memristive elements.

Proceedings ArticleDOI
28 May 2022
TL;DR: In this article , the memristor crossbar array, binary hypervectors, and neural network are used for image cryptography for proof-of-concept and text en/decryption with 100% decryption accuracy.
Abstract: We present a novel cryptography architecture based on memristor crossbar array, binary hypervectors, and neural network. Utilizing the stochastic and unclonable nature of memristor crossbar and error tolerance of binary hypervectors and neural network, implementation of the algorithm on memristor crossbar simulation is made possible. We demonstrate that with an increasing dimension of the binary hypervectors, the nonidealities in the memristor circuit can be effectively controlled. At the fine level of controlled crossbar non-ideality, noise from memristor circuit can be used to encrypt data while being sufficiently interpretable by neural network for decryption. We applied our algorithm on image cryptography for proof of concept, and to text en/decryption with 100% decryption accuracy despite crossbar noises. Our work shows the potential and feasibility of using memristor crossbars as an unclonable stochastic encoder unit of cryptography on top of their existing functionality as a vectormatrix multiplication acceleration device.

Journal ArticleDOI
TL;DR: In this paper , the authors discuss a powerful modeling framework that eases creating and implementing new memristor models, illustrating with some examples of use, and discuss how to use this framework to develop and test memristors.
Abstract: Memristors were first proposed in 1971 by Leon Chua. These devices are usually regarded as being one of the newest fundamental breakthrough for electronics. Their role in designing new electronic systems is expected to be an important, key-factor. As an example, they already come in many forms: PCA, ReRAM, etc., to mention a few. In any case, since actual memristors have only appeared quite recently, this technology has yet to be mature enough to provide with readily available, off-the-shelf components. This implies that developing and testing new concepts or design architectures based on memristors are performed mainly by the use of numerical simulation. In this paper, we discuss a powerful modeling framework that eases creating and implementing new memristor models, illustrating with some examples of use.

Journal ArticleDOI
TL;DR: The development status of memristors and the detection methods related to memristor faults are introduced in detail and an improved method, namely, artificial feature enhancement model, was proposed, which can accurately judge whether the Memristor in the circuit are faulty.
Abstract: Memristor is the fourth basic circuit component after the three basic circuit components of resistance, capacitance and inductance. It has the characteristics of nonlinear characteristics and memory function and shows great application prospects in the fields of memory, neural network, logic operation, chaotic circuit and so on. The appearance of memristor provides a new choice for the circuit realization of chaotic system. The chaotic circuit based on memristor has different characteristics compared with the chaotic circuit constructed by general components. Therefore, we studied the chaotic circuit based on memristor. It will be of great significance to the application of memristive chaotic attractors in practical engineering. In order to improve the accuracy and effectiveness of memristors in various circuits, the method of combining the artificial neural network and fuzzy analysis is used for fault detection of memristors in chaotic circuits, which can accurately judge whether the memristors in the circuit are faulty. The work of this paper is as follows: (1) development status of memristors and the detection methods related to memristor faults are introduced in detail. This paper also introduces and summarizes the development of machine learning, especially neural networks considering references of related theories in memristor fault detection. (2) Introduced the relevant theory of CNN and proposed to use one-dimensional CNN for fault diagnosis. Based on this, an improved method, namely, artificial feature enhancement model, was proposed. (3) The memristor fault detection data set was designed, and the validity of the structure and parameters of the selected CNN is verified. Finally, the effectiveness and superiority of the improvement are verified by the comparison of the CNN model and the artificial feature enhancement model.

Proceedings ArticleDOI
24 May 2022
TL;DR: In this article , an emulator using DVCC and OTA analog building blocks to emulate memristive behavior was proposed, which works in incremental and decremental mode and operates up to 8 MHz.
Abstract: In this article, we have proposed an emulator using DVCC and OTA analog building blocks to emulate memristive behavior. Along with OTA and DVCC, one resistor and one capacitor are used in the memristor emulator. The presented memristor emulator works in incremental and decremental mode and operates up to 8 MHz. The proposed memristor emulator is simulated using PSpice with a 180 nm CMOS parameter. The flexibility of the memristor is tested by simulating it at different temperatures. The adaptability of the memristor emulator during circuit implementation is tested by connecting the memristors in parallel.

Journal ArticleDOI
Zhang Zhang, Ao Xu, H. Ren, Gang Liu, Xin Cheng 
TL;DR: In this paper , the authors presented a behavioral level model of a general multivalued memristor FPGA that exhibits continuous or discrete behavior, similar to electrochemical metallization memories.
Abstract: Compared with the traditional memristor, it's more significant to research the multivalued memristor in improving the stability and reliability of memristive neural networks. Developing some multivalued memristor emulators is highly attractive since the fabrication and integration of the memristor are not mature at present. This work presents a behavioral‐level model of a general multivalued memristor FPGA that exhibits continuous or discrete behavior, similar to electrochemical metallization memories. The proposed solution has been successfully synthesized and verified on a Xilinx ZYNQ‐7000 FPGA XQ7Z020 with less than 1% hardware utilization. Additionally, to test the synaptic function of the memristor model in artificial neural networks, this paper constructs a quantized artificial neural network based on eight‐valued memristors in FPGA. In the training of the neural network, the pixel values of the images and the network weights are quantized and then mapped to the input voltage and conductance respectively of the memristor during the forward propagation. The experimental results show that the memristive network circuit achieves 92.8% recognition accuracy for 10,000 MNIST images.

Journal ArticleDOI
TL;DR: In this paper , the authors proposed a novel sneak path-free ReRAM system capable of both memory and logic operations using complementary resistive switches (CRS) or complementary memristors (CMs) crossbar array.

Journal ArticleDOI
TL;DR: In this article , a pseudo-CMOL monolithic chip core is demonstrated for spiking neural network (SNN) with 64 input neurons, 64 output neurons and 4096 1T1R synapses, fabricated in 130nm CMOS with 200nm-sized Ti/HfOx/TiN memristors.
Abstract: The advent of nanoscale memristors raised hopes of being able to build CMOL (CMOS/nanowire/molecular) type ultra-dense in-memory-computing circuit architectures. In CMOL, nanoscale memristors would be fabricated at the intersection of nanowires. The CMOL concept can be exploited in neuromorphic hardware by fabricating lower density neurons on CMOS and placing massive analog synaptic connectivity with nanowire and nanoscale-memristor fabric post-fabricated on top. However, technical problems have hindered such developments for presently available reliable commercial monolithic CMOS-memristor technologies. On one hand, each memristor needs a MOS selector transistor in series to guarantee forming and programming operations in large arrays. This results in compound MOS-memristor synapses (called 1T1R) which are no longer synapses at the crossing of nanowires. On the other hand, memristors do not yet constitute highly reliable, stable analog memories for massive analog-weight synapses with gradual learning. Here we demonstrate a pseudo-CMOL monolithic chip core that circumvents the two technical problems mentioned above by: (a) exploiting a CMOL-like geometrical chip layout technique to improve density despite the 1T1R limitation, and (b) exploiting a binary weight stochastic Spike-Timing-Dependent-Plasticity (STDP) learning rule that takes advantage of the more reliable binary memory capability of the memristors used. Experimental results are provided for a spiking neural network (SNN) CMOL-core with 64 input neurons, 64 output neurons and 4096 1T1R synapses, fabricated in 130nm CMOS with 200nm-sized Ti/HfOx/TiN memristors on top. The CMOL-core uses query-driven event read-out, which allows for memristor variability insensitive computations. Experimental system-level demonstrations are provided for plain template matching tasks, as well as regularized stochastic binary STDP feature-extraction learning, obtaining perfect recognition in hardware for a 4-letter recognition experiment.

Journal ArticleDOI
TL;DR: In this article , three different models of the memristor are presented using the modified nodal analysis (MNA) formulation technique, each stamp is tested and compared with a theoretical model.
Abstract: The memristor has long been presented as the fourth fundamental circuit element alongside the resistor, the capacitor, and the inductor. As the future of computing heads toward neuromorphic circuits, there has been a renewed interest in the modeling and simulation of memristors which have emerged as promising key components in the design of these systems. Despite such critical applications, very few models have been presented in the literature that allow for the automated and flexible integration of memristors in different simulators. In this article, three different models of the memristor are presented using the modified nodal analysis (MNA) formulation technique. Each stamp is tested and compared with a theoretical model of the memristor. Simulations are also performed on a memristor-based active high-pass filter circuit to demonstrate the accuracy of the model.

Book ChapterDOI
01 Jan 2022
TL;DR: In this paper, the conceptual description of memristive devices as key elements of neuromorphic systems is presented, starting from the definition of the memristor, proposed by L. Chua in 1971, a comparison of this device with other resistance switching elements (memistor and mnemotrix, in particular) is presented.
Abstract: The chapter is dedicated to the conceptual description of memristive devices as key elements of neuromorphic systems. Starting from the definition of the memristor, proposed by L. Chua in 1971, a comparison of this device with other resistance switching elements (memistor and mnemotrix, in particular) is presented. A current state of the art in the field of inorganic and organic memristive devices is overviewed with special attention to their synapse mimicking properties and neuromorphic applications.

Journal ArticleDOI
TL;DR: In this paper , it was shown that a resistor with memory is not a memristor and is simply an inductor with memory, which casts further doubts that ideal memristors do actually exist in nature or may be easily created in the lab.
Abstract: A simple and unambiguous test has been recently suggested [J. Phys. D: Applied Physics, 52, 01LT01 (2018)] to check experimentally if a resistor with memory is indeed a memristor, namely a resistor whose resistance depends only on the charge that flows through it, or on the history of the voltage across it. However, although such a test would represent the litmus test for claims about memristors (in the ideal sense), it has yet to be applied widely to actual physical devices. In this paper, we experimentally apply it to a current-carrying wire interacting with a magnetic core, which was recently claimed to be a memristor (so-called `$\Phi$ memristor') [J. Appl. Phys. 125, 054504 (2019)]. The results of our experiment demonstrate unambiguously that this `$\Phi$ memristor' is not a memristor: it is simply an inductor with memory. This demonstration casts further doubts that ideal memristors do actually exist in nature or may be easily created in the lab.

Journal ArticleDOI
TL;DR: In this paper , a reconfigurable memristor emulator that can be implemented in digital circuits is proposed, which has been successfully synthesized and confirmed on a Xilinx ZYNQ-7000 FPGA.

Journal ArticleDOI
TL;DR: This paper studies some circuits studied by predecessors on read/write circuit, compares the experimental results, analyzes the reason for the resistance state deviation of memristor, and puts forward a new parallel structure of Memristor based on opposite polarity.
Abstract: In recent years, computation-intensive applications, such as artificial intelligence, video processing and encryption, have been developing rapidly. On the other hand, the problems of “storage wall” and “power consumption wall” for the traditional storage and computing separated architectures limit the computing performance. The computational circuits and memory cells based on nonvolatile memristors are unified and become a competitive solution to this problem. However, there are various problems that prevent memristor-based circuits from entering practical applications, one of which is the memristor state deviation problem caused by continuous reading. In this paper, we study some circuits studied by predecessors on read/write circuit, compare the experimental results, analyze the reason for the resistance state deviation of memristor, and put forward a new parallel structure of memristor based on opposite polarity. The logic “1” and logic “0” are represented by the positive and negative voltage difference of two memristors with opposite polarity, which can effectively alleviate the problem of the resistance state deviation caused by continuous reading. A reading voltage of 2 V is applied to the four circuits at the same time, and continuous reading is carried out until the output voltage becomes stable. The voltage offset of the optimized circuit when reading logic “0” is reduced to 78 mV, which is significantly smaller than that of other circuits. In addition, when reading logic “1”, it has the effect of enhancing the information stored in the memristor.

Journal ArticleDOI
TL;DR: This review explains the design principles and switching mechanism of a Ta/HfO2 memristor and shows that the device meets most key requirements on device properties for in-memory computing.
Abstract: Hardware implementation of neural networks with memristors can break the “von-Neumann bottleneck,” offer massive parallelism, and hence substantially boost computing throughput and energy efficiency. In this review, we first explain the design principles and switching mechanism of a Ta/HfO2 memristor. We show that the device meets most key requirements on device properties for in-memory computing. We then introduce the integration of the memristor with foundry-made metal-oxide-semiconductor transistors and the programming of the one-transistor-one-resistance switch (1T1R) arrays. We demonstrate that the crossbar arrays can be used in various neural networks. Finally, we discuss the remaining challenges of scaling up the memristive neural networks for larger scale real-world problems.

Proceedings ArticleDOI
08 Jun 2022
TL;DR: In this article , a simple, fast functioning modified metal oxide memristor model is suggested and its corresponding LTSPICE library model is generated and successfully analyzed in a simple neural network.
Abstract: The memristor is a new and promising electronic memory element and could be a possible replacement for the present CMOS components. Due to its nano size, low energy usage and memory effect, it could be used in neural nets, memory crossbars, reconfigurable analogue and digital devices and other electronic schemes. In this paper, a simple, fast functioning modified metal oxide memristor model is suggested. Its corresponding LTSPICE library model is generated and successfully analyzed in a simple neural network. The model’s behavior is in accordance with the basic fingerprints of the memristor elements. Its proper operation and applicability in memristor-based devices is established.

Journal ArticleDOI
TL;DR: In this article , the authors proposed a complete CMOS realized neuromorphic system for pattern recognition having CMOS-based memristor emulators as synaptic circuits, where the crossbar array of the system is modeled by considering the emulator circuit's area to determine the spacing between the interconnects.
Abstract: This paper proposes a complete CMOS realized neuromorphic system for pattern recognition having CMOS-based memristor emulators as synaptic circuits. The crossbar array of the system is modeled by considering the emulator circuit's area to determine the spacing between the interconnects. The interconnect parasitics are obtained from the ANSYS Q3D extractor. Parasitics extracted are also validated using the analytical model. A crossbar array architecture modeled with the extracted parasitic components and the memristor emulator will provide an understanding of the behavior of the crossbar array and can be used to analyze the parasitic effects on various real-time applications. Our analysis shows that as the operating frequency increases, the recognition rate of the neuromorphic system is reduced to 66.67% due to the crossbar's parasitics, non-idealities of the neuron, and memristor circuits. The memristor's state, either low or high resistance, significantly affects the system's performance, which is evaluated by the rise time and signal delay. The energy consumed by the CMOS-based memristor emulator synapse for recognizing each pattern is 0.44 $nJ$, which is significantly lower when compared with the previous works. The circuit design and verification are done using 180-nm CMOS technology.

Journal ArticleDOI
D. Crouzet1
TL;DR: In this paper , an efficient and flexible window function is presented for a linear drift memristor model, which provides a unique feature (controllable window function discontinuity at the boundaries) to solve the distorted pinched hysteresis loop problem.
Abstract: The memristor is a novel nanostructured resistive tuning two-terminal electronic device that has been widely explored in the areas of neuromorphic computing systems, memory, digital circuits, analog circuits, and many more new applications. In this article, an efficient and flexible window function is presented for a linear drift memristor model. The proposed parametric cubic parabolic window function provides a unique feature (controllable window function discontinuity at the boundaries) to a linear drift memristor model by which the distorted pinched hysteresis loop problem is resolved and the number of programming resistance states of the memristor is improved. Five control parameters are introduced in the proposed window function in order to correct the existing problems (such as boundary effect, boundary lock and inflexibility) and are able to provide asymmetric nonlinearity at the boundaries of the device, making it feasible for tracking the resistive switching dynamic of a futuristic oxide-based memristive device with different inert electrodes. The proposed model is validated with a solution-processed ZnO-based fabricated memristive device. A programmable analog gain amplifier circuit is ultimately executed to simulate the utilization of the evolved memristor model, and the effect of memristance resolution is investigated.