Memistor

About: Memistor is a research topic. Over the lifetime, 608 publications have been published within this topic receiving 34905 citations.

Memristive Model for Synaptic Circuits

Abstract: As a promising alternative for next-generation memory, memristors provide several useful features such as high density, nonvolatility, low power, and good scalability as compared with conventional CMOS-based memories. In this brief, a voltage-controlled threshold memristive model is proposed, which is based on experimental data of memristive devices. Moreover, the model is more suitable for the design of memristor-based synaptic circuits as compared with other memristive models. The effects of memristance variations are considered in the proposed model to evaluate the behavior of memristive synapses within memristor-based neural networks.

Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems

Abstract: Neuromorphic computing system (NCS) is a promising architecture to combat the well-known memory bottleneck in Von Neumann architecture. The recent breakthrough on memristor devices made an important step toward realizing a low-power, small-footprint NCS on-a-chip. However, the currently low manufacturing reliability of nano-devices and the voltage IR-drop along metal wires and memristors arrays severely limits the scale of me-mristor crossbar based NCS and hinders the design scalability. In this work, we propose a novel system reduction scheme that significantly lowers the required dimension of the memristor crossbars in NCS while maintaining high computing accuracy. An IR-drop compensation technique is also proposed to overcome the adverse impacts of the wire resistance and the sneak-path problem in large memristor crossbar designs. Our simulation results show that the proposed techniques can improve computing accuracy by 27.0% and 38.7% less circuit area compared to the original NCS design.

Sneak-path constraints in memristor crossbar arrays

Abstract: In a memristor crossbar array, a memristor is positioned on each row-column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this work, we study the sneak path problem in crossbars arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method we match a constraint on the array content that guarantees sneak-path free readout, and calculate the resulting capacity.

A 860 kHz grounded memristor emulator circuit

Abstract: A grounded memristor emulator circuit operating from 16 Hz to 860 kHz is proposed. The emulator circuit is built around a plus-type second generation current conveyor, a four quadrant analog multiplier, a capacitor and a resistor. Two DC voltage sources are used for controlling the zero crossing of the frequency-dependent pinched hysteresis loop over a broad range of amplitude A m of the input signal, and principally when the memristor emulator circuit is operating at high-frequency. It describes in detail the derivation of the behavioral model of the proposed emulator circuit, including parasitic elements and showing that the charge-controlled memductance is a first-order function. Furthermore, a design guide to choose the numerical value of each discrete element in function of the operating frequency and A m is also given. The emulator circuit is built with off-the-shelf devices, and numerical results obtained by means of the behavioral model are compared with HSPICE simulations and experimental tests, showing good agreement among all them in a wide range of frequencies. This is against with some memristor emulator circuit available in the literature which present a good behavior at low-frequency and however, the zero crossing of the pinched hysteresis loop is deviated when the operating frequency increases. It is worth to stress that for the best knowledge of the authors, this is the first memristor emulator circuit that is operating to high-frequency. Moreover, the proposed emulator circuit can be configured as decremental or incremental memristor in order to be used in future applications such as cellular neural networks, modulators, sensors, chaotic systems, relaxation oscillators, nonvolatile memory devices and programmable analog circuits.

Memristor crossbar deep network implementation based on a Convolutional neural network

Abstract: This paper presents a simulated memristor crossbar implementation of a deep Convolutional Neural Network (CNN). In the past few years deep neural networks implemented on GPU clusters have become the state of the art in image classification. They provide excellent classification ability at the cost of a more complex data manipulation process. However once these systems are trained, we show that the analog crossbar circuits in this paper can highly parallelize the recognition phase of a CNN algorithm. One of the drawbacks of using memristors to carry out computations is that the data stored will likely have less precision when compared to typical 32-bit floating point memory. However, we show the proposed system is capable of operating with zero loss in classification accuracy if the memristors utilized are able to store at least 16 unique values (essentially acting as 4-bit devices). To the best of our knowledge, this is the first paper that presents a memristor based circuit for implementing CNN recognition. This is also the first paper that provides a circuit for precise memristor based analog convolution.