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Memistor

About: Memistor is a research topic. Over the lifetime, 608 publications have been published within this topic receiving 34905 citations.


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Journal ArticleDOI
TL;DR: This work developed a stochastic behavior model based on the statistical analysis of experimental data of TiO2 device and presented a macro cell design composed of multiple parallel connecting memristors that provide a feasible solution in memristor-based hardware implementation of neural networks.
Abstract: As the fourth basic circuit element, memristor has a unique synapse-alike feature which demonstrates great potentials in neuromorphic circuit design. However, a large gap exists between the theoretical memristor characteristics and the actual device behavior. For example, though the continuous changing in resistance state is expected in neuromorphic circuit design, it is difficult to maintain arbitrary intermediate state. In addition, the stochastic switching behaviors have been widely observed in nano-scale memristor devices. In this work, we first developed a stochastic behavior model in order to facilitate the investigation on memristor-based hardware implementation. Our modeling was based on the statistical analysis of experimental data of ${\rm TiO }_{2}$ device. By leveraging the stochastic behavior of memristors, a random number generator was proposed. We also presented a macro cell design composed of multiple parallel connecting memristors which can be successfully used in implementing the weight storage unit and the stochastic neuron. The designs of these fundamental components provide a feasible solution in memristor-based hardware implementation of neural networks.

19 citations

Proceedings ArticleDOI
08 Jul 2015
TL;DR: This paper proposes a generic and flexible interconnect network for memristor-based logic circuits within a crossbar architecture based on the use of reserved memristors (within the crossbar), and can be applied both at intra-tile as well as inter-tile level.
Abstract: As the down-scaling of CMOS technology reaches inherent physical device limits, major challenges arise such as reliability, power consumption, etc. Novel technologies are under investigation as an alternative for next-generation VLSI circuits. Memristor is one of the promising candidates due to its scalability, non-volatility, practically zero leakage, high integration density, etc. Several applications have been proposed for the memristor crossbar architecture; examples are neuromophic, memories and logic circuits. This paper proposes a generic and flexible interconnect network for memristor-based logic circuits within a crossbar architecture. The scheme is based on the use of reserved memristors (within the crossbar) and the execution of copy operations from and/or to the reserved memristors; it can be applied both at intra-tile as well as inter-tile level, where a tile is a basic block performing a simple logic function. To illustrate the potential of the proposed scheme, two intra-tile and one inter-tile case study are evaluated using SPICE simulation, and their incurred costs are analyzed; the case studies consist of interconnect networks for (a) a specific function within a tile (i.e., the matrix transpose), (b) generic logic functions within a tile, and (c) communication between tiles.

18 citations

Journal ArticleDOI
TL;DR: This paper presents a compact and efficient scheme of reading and writing for two memristors per transistor-based multivalued memory using the VTEAM model of the memristor and verification of feasibility of reading operations and writing operations for multivaluing memory is achieved through HSPICE simulation.
Abstract: The multivalued memory achieved with memristors is a promising approach to enhance the memory density. Effective and compact methods of reading and writing for multivalued memories can significantly improve the performance of circuits. In this paper, we present a compact and efficient scheme of reading and writing for two memristors per transistor-based multivalued memory. With the VTEAM model of the memristor, the verification of feasibility of our reading operations and writing operations for multivalued memory is achieved through HSPICE simulation.

18 citations

Journal ArticleDOI
TL;DR: A novel memistor-based neuron circuit, in which the memristor-CMOS hybrid synaptic circuit simply utilizes the positive voltage to change the Memristor and output voltage changes in the neuron circuit is proposed.
Abstract: This paper proposes a novel memistor-based neuron circuit, in which the memristor-CMOS hybrid synaptic circuit simply utilizes the positive voltage to change the memristance. At the same time, in order to obtain the memristance and output voltage changes in the neuron circuit, a mathematical deduction is implemented according to the circuit structure. Then, the memristor-based recognition and recall network circuits are constructed based on the proposed neuron circuit. The recognition and recall functions are realized by associative learning between the unconditional stimuli and the conditional stimuli (CS). After the learning stages, the single presentation of CS activates forgetting stages in the two networks. Furthermore, the related parameter changes in the learning and forgetting stages can be calculated by the deduced equations approximately. The PSPICE simulations are implemented to demonstrate the effectiveness of the proposed circuits and the deduced equations.

18 citations

Journal ArticleDOI
TL;DR: This note clarifies the circuit-theoretic differences between a memristor and a memistor.
Abstract: This note clarifies the circuit-theoretic differences between a memristor and a memistor.

18 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202328
202277
20212
20201
20191
201815