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Memistor

About: Memistor is a research topic. Over the lifetime, 608 publications have been published within this topic receiving 34905 citations.


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Proceedings ArticleDOI
01 Sep 2016
TL;DR: This paper demonstrates how two bits of information can be stored and read back from a single Memristor unit and proposes encoding schemes that can enhance the reliability of digitally writing two and three bits of data in a single memristor using digital bit streams.
Abstract: Memristors have been used in various applications, including single- and multi-bit storage units. The non-linear voltage-current relation in memristors is often seen as a problem, necessitating complex circuits and methods for a reliable write-in. In this paper, we take advantage of this phenomenon for storing more than one bit of information in a single memristor using digital bit streams. First, we demonstrate how two bits of information can be stored and read back from a single memristor unit. Then, we propose encoding schemes that can enhance the reliability of digitally writing two and three bits of data in a single memristor. To verify the reliability of this method for multi-bit data storage, we have run simulations based on the most prominent simulation models available.

15 citations

Proceedings ArticleDOI
20 May 2012
TL;DR: A memristor based new synaptic circuit, consisting of five Memristor in a bridge structure together with one differential amplifier, able to perform positive and negative weighting for pulse type inputs in neural cells is presented.
Abstract: This paper presents a memristor based new synaptic circuit, consisting of five memristor in a bridge structure together with one differential amplifier. The circuit is able to perform positive and negative weighting for pulse type inputs in neural cells. Processing is conducted with applied pulses at a common terminal in different time slots. It is compact, non-volatile and low power efficient. Simulations of sign setting, weight setting and synaptic multiplication are performed with hp TiO 2 memristor models.

15 citations

Posted Content
TL;DR: The original memristive systems framework is extended to incorporate 3-terminal, non-passive devices and the applicability of such dynamic systems models to 1) the Widrow-Hoff memistor, 2) floating gate memory cells, and 3) nano-ionic FETs is explained.
Abstract: Memristive systems were proposed in 1976 by Leon Chua and Sung Mo Kang as a model for 2-terminal passive nonlinear dynamical systems which exhibit memory effects. Such systems were originally shown to be relevant to the modeling of action potentials in neurons in regards to the Hodgkin-Huxley model and, more recently, to the modeling of thin film materials such as TiO2-x proposed for non-volatile resistive memory. However, over the past 50 years a variety of 3-terminal non-passive dynamical devices have also been shown to exhibit memory effects similar to that predicted by the memristive system model. This article extends the original memristive systems framework to incorporate 3-terminal, non-passive devices and explains the applicability of such dynamic systems models to 1) the Widrow-Hoff memistor, 2) floating gate memory cells, and 3) nano-ionic FETs. Keywords-memristive systems, memistor, transconductance, synaptic transistor, non-linear dynamic systems

15 citations

Proceedings ArticleDOI
01 Dec 2011
TL;DR: It is demonstrated that firstly, the Spike-Timing-Dependent Plasticity (STDP) can be implemented by a single memristor device and secondly, a Memristor-based competitive Hebbian learning through STDP using a 1×1000 synaptic network.
Abstract: We present new computational building blocks based on memristive devices. These blocks, can be used to implement either supervised or unsupervised learning modules. This is achieved using a crosspoint architecture which is an efficient array implementation for nanoscale two-terminal mem-ristive devices. Based on these blocks and an experimentally verified SPICE macromodel for the memristor, we demonstrate that firstly, the Spike-Timing-Dependent Plasticity (STDP) can be implemented by a single memristor device and secondly, a memristor-based competitive Hebbian learning through STDP using a 1×1000 synaptic network. This is achieved by adjusting the memristor's conductance values (weights) as a function of the timing difference between presynaptic and postsynaptic spikes. These implementations have a number of shortcomings due to the memristor's characteristics such as memory decay, highly nonlinear switching behaviour as a function of applied voltage/current, and functional uniformity. These shortcomings can be addressed by utilising a mixed gates that can be used in conjunction with the analogue behaviour for biomimetic computation. The digital implementations in this paper use in-situ computational capability of the memristor.

15 citations

Proceedings ArticleDOI
10 Jun 2012
TL;DR: A memristor-based neuromorphic competitive control circuit, which utilizes a single sensor and can control the output of N actuators delivering optimal scalable performance, and immunity from device variation and environmental noise is presented.
Abstract: Recent work in neuroscience is revealing how the blowfly rapidly detects orientation using neural circuits distributed directly behind its photo receptors. These circuits like all biological systems rely on timing, competition, feedback, and energy optimization. The recent realization of the passive memristor device, the so-called fourth fundamental passive element of circuit theory, assists with making low power biologically inspired parallel analog computation achievable. Building on these developments, we present a memristor-based neuromorphic competitive control (mNCC) circuit, which utilizes a single sensor and can control the output of N actuators delivering optimal scalable performance, and immunity from device variation and environmental noise.

15 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202328
202277
20212
20201
20191
201815