Memistor

About: Memistor is a research topic. Over the lifetime, 608 publications have been published within this topic receiving 34905 citations.

Memristor-based comparator with programmable hysteresis

Abstract: In this paper, we adopt a memristor network to implement a voltage comparator with programmable hysteresis. The basic building block is based on chopping technique which has been used to control the charge integrated in the device in order to avoid drift effects. By doing this, the memristance value can be preserved, thus obtaining a programmable resistance that can be used in several circuital configurations. Its minimum size is orders of magnitude less than that of a standard resistor implemented in CMOS, which means a significant reduction in silicon area. Moreover, the memristance can be easily programmed through digital pulses. The functionality of the comparator has been simulated. Varying the flux across any of the memristors will change the comparator's hysteresis.

Implementation of adaptive coupling through memristor

Abstract: Since its discovery, memristor attracted a lot of attention for its potential applications as next generation electronic device, as system for modeling and implementing biological synapses and as key component in nonlinear circuits. Here we exploit the peculiarities of the HP memristor in order to realize an adaptive coupling, able to reach consensus and synchronization between two dynamical systems. In particular, the coupling scheme consists of two HP memristors connected in antiparallel which allow to deal with consensus/synchronization error of either positive and negative sign. Simulation results on consensus of two agents with integrator dynamics and synchronization of two Chua's circuits show the suitability of the proposed approach. (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Memristor-Based Discrete Fourier Transform for Improving Performance and Energy Efficiency

Abstract: Memristor has emerged as one of the most promising candidates for the fundamental device in the beyond-CMOS era. With their unique advantage on implementing low-power high-speed matrix multiplication, memristors have shown great and vast potentiality in many specific applications. This paper, for the first time, investigates the hardware design of DFT using memristors. Two implementations of DFT using memristors have been presented for effectively trading-off between hardware complexity and computing speed. Simulation results show that as compared to the conventional CMOS-based design, the proposed memristor-based design enables significant reduction in computation latency and improvement in power efficiency with very low inaccuracy. Simulation results show that the proposed memristor-based implementation could reach up to 10X improvement in speed and 109.8X reduction in power efficiency compared to CMOS-based design.

A memristor-based memory cell with no refresh

Abstract: This paper analyzes and improves the performance of a hybrid memory cell consisting of a memristor and ambipolar transistors. This work extends a previous design by efficiently biasing the memristor (as controlled by the ambipolar transistors), such that no refresh operation is now required. By utilizing macroscopic models, the features of the cell are characterized for the memory operations and no modification is needed to the cell circuit other than the memristor biasing scheme. A detailed treatment of the memory cell with respect to the new biasing scheme of the memristor is provided. Simulation results show that the proposed memory cell has superior performance compared with the previous memristor-based cell.

Synthesizing HDL to memristor technology: A generic framework

Abstract: Memristors are emerging devices with huge potentials. It has been shown that they can be used not only to design non-volatile memories, but also logic circuits. In the latter, memristor devices are stacked on a CMOS circuit which generates the required control signals needed by the memristors to perform the required functionality. This paper sets a step towards automating this process; it proposes a generic synthesis framework to map logic circuits on memristor crossbar. The framework takes HDL descriptions as input and generates both its memristor circuitry and its associated CMOS control. The framework consists of three phases: (i) netlist generation, (ii) partition and mapping, and (iii) placement and routing. To illustrate the framework, a combinational and a sequential circuit are investigated. The results are validated using HSPICE simulations.