Memistor

About: Memistor is a research topic. Over the lifetime, 608 publications have been published within this topic receiving 34905 citations.

Neural processor design enabled by memristor technology

Abstract: Matrix-vector multiplication is a key computing operation in neural processor design and hence greatly affects the execution efficiency. Memristor crossbar is highly attractive for the implementation of matrix-vector multiplication for its analog storage states, high integration density, and built-in parallel execution. The current deign schemes can be generally divided into two different approaches - “spiking-based” design and “levelbased” design. The performance and robustness of the proposed neural process designs are also evaluated by using the application of digital image recognition. In this work, a heuristic flow including device modeling, circuit design, architecture, and algorithm is studied. The proposed neural processor designs that leverages nano-scale memristor technology are summarize and compared. This work indicates that the spiking neuromorphic engine has a good tolerance in resistive device imperfection, but more vulnerable to the fluctuations in output spike generation. The improved level-based computing engine has a higher computation accuracy with better stability.

Digital model of TiO2 memristor for field-programmable gate array

Abstract: A digital model which imitates the behaviour of a TiO2 memristor as a new block in Alter DSP Builder is proposed in this Letter The proposed model can be used as an independent memristor unit working with other units for designing memristor circuits based on field-programmable gate array The accuracy of the digital model is confirmed not only by simulations, but also by hardwire experiments

Write scheme for multiple Complementary Resistive Switch (CRS) cells

Abstract: Amongst emerging technologies with the potential to usher in a new generation of Non Volatile Memory (NVM) is the memristor. The memristor makes it possible to build simple and highly dense memory structure via cross point architecture. Memristor array however suffers exponentially from sneak path leakages as array size increases, which leads to excessive power consumption and poor data integrity. Complementary Resistive Switch (CRS) was proposed to mitigate the sneak-path problem. However, when writing into multiple cells in CRS-based memory array, the state of unselected and and half-selected cell(s) in the array are affected in an undesired way depending on the polarity, magnitude and duration of the voltage applied during the write operation. The effect of these disturbance to non-selected cell(s) is a resultant corrupted output in subsequent read operation on these cell(s). In this paper, we reviewed the basic operation of the memristor and CRS cell in relation to their application as a memory device. Finally, we implemented an improved scheme for writing alternating data patterns into multiple cells in CRS-based memory array, we also examine how the initial state of the cell affects the performance of this scheme.

Multi-level programming of memristor in nanocrossbar

Abstract: Utilizing memristor to obtain multi-level memory in nano-crossbar is a promising approach to enhance the memory density. In this paper, we proposed a solution for multi-level programming of memristor in nanocrossbar, which can be implemented on nanocrossbar without the need for extra selective devices. Meanwhile, using a general device model, this solution is demonstrated to be adaptive to a wide range of memristors that have been experimentally fabricated through HSPICE simulation.

A novel hybrid design of a memory cell using a memristor and ambipolar transistors

Abstract: This paper presents a novel memory cell consisting of a memristor and ambipolar transistors. Macroscopic models are utilized to characterize the operations of this memory cell. A detailed treatment of the two basic memory operations (write and read) with respect to memristor features is provided; particular, emphasis is devoted to the threshold characterization of the memristance and the on/off states. Extensive simulation results are provided to assess performance in terms of the write/read times, transistor scaling and power dissipation. The simulation results show that the proposed memory cell achieves superior performance compared with other memristor-based cells found in the technical literature.