Memistor

About: Memistor is a research topic. Over the lifetime, 608 publications have been published within this topic receiving 34905 citations.

Diffusive Memristors with Uniform and Tunable Relaxation Time for Spike Generation in Event-Based Pattern Recognition.

Abstract: A diffusive memristor is a promising building block for brain-inspired computing hardware. However, the randomness in the device dynamics limits the wide-range adoption of diffusive memristors in large arrays. In this work, we engineered the device stack to achieve a much-improved uniformity in the relaxation time (standard deviation σ reduced from ∼12 to ∼0.32 ms). We further connected the memristor with a resistor or a capacitor and tuned the relaxation time between 1.13 μs to 1.25 ms, ranging from three orders of magnitude. We implemented the hierarchy of time surfaces (HOTS) algorithm to utilize the tunable and uniform relaxation behavior for spike generation. We achieved 77.3% accuracy in recognizing moving objects in the neuromorphic MNIST (N-MNIST) dataset. Our work paves the way for building emerging neuromorphic computing hardware systems with ultralow power consumption. This article is protected by copyright. All rights reserved.

A reference-less multilevel memristor based RRAM module

Abstract: This paper presents a robust reference-less multilevel memristor based Resistive RAM (RRAM) module In contrast to similar multilevel RRAMs, the proposed multilevel module eliminates the need for any comparing reference level Because of the use of a differential 1T2M memory cell, data decoding is performed with traditional standard cells On the other hand, no feedback loops are needed to ensure read, write and data decoding correctness In addition, the proposed module is pinout compatible with the traditional 6T SRAM module Simulation results, along with a comparison with other memristor based multilevel modules are presented

Thermal optimization for memristor-based hybrid neuromorphic computing systems

Abstract: Neuromorphic computing is used for accelerating the computation of neural network which can simulate the brain of animal and composed by neurons and synapses. However, the neuromorphic computing with the traditional computer architecture leads to serious von Neumann bottleneck because of the gap between high frequency CPU computation and memory access. The emerging memristor is an innovation technology for future VLSI circuits potentially can be acted as both data storage and computing unit to transform the computer architecture. Furthermore, the characteristics of memristors include low programming energy, parallel process, small footprint, non-volatility, etc, which have attracted significant researches on neuromorphic computing. However, some important issues such as thermal damage defect the reliability of memristors. High thermal of memristor is a critical issue which impacts the reliability of the systems. To estimate the thermal of the memristor, we formulated the thermal as the power consumption problem. In this paper, a thermal optimization algorithm for memristor-based hybrid neuromorphic computing system is proposed to solve the the reliability issue by the incremental cluster network flow. Our results show that the maximum power consumption can be reduced about 31%.

Survey on memrister models

Abstract: While hardware in a computer have developed greatly, users still has faced problems with its speed, and memory in terms of its performance. The recent developments in memristors made it possible to reduce the problems, as memristive models have been be designed to suit the requirements of time. However, different characteristics are expected from memristors depending upon its applications. The paper aims to compare three major models of memristors focusing on their advantages and limitations. It identifies the most suitable model of memristor that satisfies the memristive device conditions. Out of the three models, Voltage threshold adaptive memristor model (VTEAM) fits into the requirements and it has sufficient accuracy and computational efficiency.

Low power application for nano scaled Memristor based 2∶1 multiplexer

Abstract: Now a day market demands compressed devices that operates on low voltage and causes less noise in the output. Advanced nano scale very large integrated circuits are facing significant timing closure challenges especially due to random on chip threshold voltage variations. Memristor can play an important role in improving the scalability and efficiency of existing memory technology. Accordingly this article introduces Memristor based 2∶1 multiplexer. Memristor is non linear passive two terminal electrical components relating electric charge. Memristor has dynamic relationship between current and voltage including a memory of past voltage or current. In this paper two main properties of Memristor is highlighted firstly nano scale dimension and another it's non volatile memory characteristics. By using these properties it gives better way to design the circuit as well as it stored output too. With the many advantages of Memristor CMOS it becomes possible to reduce the area on silicon chip. Here many CMOS transistors are replaced by few Memristor and multiplexer is made. All related parameters of multiplexer, are calculated in the cadence virtuoso tool and 45nm technology with 0.7 v operating voltage.