Showing papers on "Memory management published in 1968"

Human memory ; A proposed system and its control processes

Abstract: Publisher Summary This chapter presents a general theoretical framework of human memory and describes the results of a number of experiments designed to test specific models that can be derived from the overall theory. This general theoretical framework categorizes the memory system along two major dimensions. The first categorization distinguishes permanent, structural features of the system from control processes that can be readily modified or reprogrammed at the will of the subject. The second categorization divides memory into three structural components: the sensory register, the short-term store, and the long-term store. Incoming sensory information first enters the sensory register, where it resides for a very brief period of time, then decays and is lost. The short-term store is the subject's working memory; it receives selected inputs from the sensory register and also from long-term store. The chapter also discusses the control processes associated with the sensory register. The term control process refers to those processes that are not permanent features of memory, but are instead transient phenomena under the control of the subject; their appearance depends on several factors such as instructional set, the experimental task, and the past history of the subject.

Further experimental data on the behavior of programs in a paging environment

Abstract: Results are summarized from an empirical study directed at the measurement of program operating behavior in those multiprogramming systems in which programs are organized into fixed length pages. The data collected from the interpretive execution of a number of paged programs are used to describe the frequency of page faults, i.e. the frequency of those instants at which an executing program requires a page of data or instructions not in main (core) memory. These data are used also for the evaluation of page replacement algorithms and for assessing the effects on performance of changes in the amount of storage allocated to executing programs.

An algorithm for minimizing read only memories for machine control

Abstract: This paper describes an algorithm for minimizing the storage required of a Read Only Memory that is going to be used as the control element for a digital machine. The technique is based upon the fact that not all sub-commands are required in all words so that bits of the memory may be time shared between subcommands. The algorithm provides a means for determining what sub-commands should share a common set of bits. The algorithm is essentially one of exhaustive evaluation but it is one that directs you toward the solution rather than one which randomly tries all possible solutions and chooses the best. In addition certain bounds on the "size" of the solution are derived and these in turn eliminate a large segment of the possible solution set from consideration. Finally, the algorithm is quite iterative and as such lends itself readily to implementation of a digital machine.

Resource management for a medium scale time-sharing operating system

Abstract: Task scheduling and resource balancing for a medium-size virtual memory paging machine are discussed in relation to a combined batch processing and time sharing environment. A synopsis is given of the task scheduling and paging algorithms that were implemented and the results of comparative simulation are given by tracing the development of the algorithms through six predecessor versions. Throughout the discussion particular emphasis is placed on balancing the system performance relative to the characteristics of all the system resources. Simulation results relative to alternate hardware characteristics and the effects of program mix and loading variations are also presented.

Addressable list memory systems

Abstract: A memory system includes at least a main list memory. When the memory system is to be accessed for an operation of reading or writing a word, it receives the desired word address. Words are then sequentially transferred from the list memory. As each word is transferred, its address is indicated as available. When a predetermined relationship, such as equality is detected between the desired word address and indicated address, the read or write operation is performed. In the several embodiments of the disclosure, the indicated available address is derived either from a counter or from the contents of the words being transferred. In addition, the various embodiments show the main list memory as either a Last-in First-out (LIFO) type or a Firstin First-out (FIFO) type.

Addressing an operating memory of a digital computer system

Abstract: IN A DIGITAL DATA PROCESSING SYSTEM ARRANGED TO OPERATE WITH INSTRUCTION WORDS HAVING AN ADDRESS PORTION CONSISTING OF A GIVEN NUMBER OF BITS, WHICH SYSTEM INCLUDES AN OPERATING MEMORY HAVING A NUMBER OF ADDRESS LOCATIONS WHICH IS GREATER THAN THE NUMBER OF LOCATIONS WHICH CAN BE ADDRESSED BY AN INSTRUCTION WORD ADDRESS PORTION, A METHOD AND APPARATUS FOR PERMITTING ANY GROUP OF OPERATING MEMORY ADDRESS LOCATIONS TO BE ADDRESSED BY THE INSTRUCTION WORD ADDRESS PORTION BY DIVIDING THE OPERATING MEMORY INTO A PLURALITY OF SECTIONS ALL OF THE ADDRESS LOCATIONS OF WHICH CAN BE ADDRESSED BY A NUMBER OF BITS WHICH IS LESS THAN THAT CONTAINED IN THE INSTRUCTION WORD ADDRESS PORTION, DEILVERING THAT NUMBER OF BITS OF THE INSTRUCTION WORD ADDRESS PORTION DIRECTLY TO THE OPERAING MEMORY, LOGICALLY COMBINING THE REMAINING BITS OF THE INSTRUCTION WORD ADDRESS PORTION WITH A PREDETERMINED STATUS WORD TO FORM A STATUS ADDRESS PORTION, AND DELIVERING SUCH STATUS ADDRESS PORTION TO THE OPERATING MEMORY FOR DETERMINING WHICH PARTIAL SECTIN OF THE MEMORY IS BEING ADDRESSED BY THE INSTRUCTION WORD.

A Combination Hardware-Software Debugging System

Abstract: A scheme is proposed for automatically detecting many programming errors; in particular, those errors which can cause a program to misbehave in different ways, depending upon how the faulty program and its data are mapped into storage. Error detection is accomplished by simultaneously running two versions of a program which purport to be logically identical, with appropriate hardware checking between them.

System protection apparatus

Abstract: APPARATUS IN A COMPUTER SYSTEM FOR PROTECTING OPERATING PROGRAMS AND RELATED DATA STORED IN THE COMPUTER MEMORY AND FOR PREVENTING UNAUTHORIZED ACTIONS IN THE SYSTEM WHILE AN UNDEBUGGED PROGRAM IS BEING EXECUTED BY THE SYSTEM A STATUS REGISTER IS PROVIDED IN THE SYSTEM ARITHMETIC UNIT FOR STORING A SYSTEM PROTECTION STATUS WORD ANOTHER REGISTER IS PROVIDED TO IDENTIFY THE GROUP OR VOLUME OF MEMORY STORAGE LOCATIONS WHOSE PROTECTION STATUS IS DEFINED BY THE STATUS WORD IN THE STATUS REGISTER EACH TIME MEMORY IS ADDRESSED, THE STATUS WORD APPLICABLE TO THE ADDRESSED MEMORY STORAGE LOCATION IS CHECKED THE STATUS WORD DEFINES ONE OF A PLURALITY OF PROTECTION STATES FOR THE ADDRESSED MEMORY STORAGE LOCA- TION LOGIC GATES ARE PROVIDED WHICH ARE RESPONSIVE TO THE PROTECTION STATUS WORD, TO THE TYPE OF OPERATION FOR WHICH MEMORY IS BEING ADDRESSED, AND TO OTHER CONDITIONS TO DETERMINE IF A SYSTEM PROTECTION VIOLATION HAS OCCURED UPON DETECTION OF A SYSTEM PROTECTION VIOLATION, ACCESS TO THE ADDRESSED MEMORY LOCATION IS INHIBITED AND EXECUTION OF AN ERROR ROUTINE IS INITIATED

A note on the efficiency of a LISP computation in a paged machine

Abstract: The problem of the use of two levels of storage for programs is explored in the context of a LISP system which uses core memory as a buffer for a large virtual memory stored on a drum. Details of timing are given for one particular problem.

Addressing patterns and memory handling algorithms

Abstract: One of the principal problems facing the designer of a high performance computer system is the efficient handling of memory. In arranging a memory system the designer, lacking knowledge of the programs to be run, usually selects "worst case" assumptions concerning addressing patterns. This paper is an attempt to compare a set of selected disparate programs and analyze their actual addressing traces with respect to the various memory algorithms.

Optimization of information storage systems

Abstract: In this paper the writers have developed a model and an optimization technique for the design of hierarchical structures of memory so as to minimize the average access time to blocks of information stored in the hierarchy for a given cost constraint. The assumption is made that the “activity profile” giving the relative frequencies with which blocks are accessed (for a given set of problems) is available. The designs are tailored to fit the given activity profiles. The first part of the paper introduces the basic problem solved and some terminology used in the development of the theory. The second part consists of: (a) A method of evaluating memory types, i.e., a method of selecting an optimum subset of memory types which will compose the hierarchy from the set of all available memory types, and (b) The determination of the optimum sizes of each memory type in the subset so as to minimize the average access time to addresses in the hierarchy for a given cost constraint and a given activity profile. (c) The third part develops the optimization technique when the number of members in the memory hierarchy is limited. The last part is a discussion on the possible application of the technique to the evaluation of multi-precision arithmetic and to language translation. The second part also considers the problem of deriving the cost-average-access-time characteristic for a given profile. This characteristic will be useful in memory allocation problems as well as a valuable tool to computer designers for determination of memory sizes.

Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor

Abstract: —The Cambridge System, comprising a standard IBM System/360 Model 40 and an associative memory, is described from the viewpoint of its implementation using the READ-only control storage of the Model 40. In particular, we discuss the use of the ROS in 1) controlling the flow of data between the CPU and the associative memory registers, and 2) handling translation control, absent page indications, and variable field operand pretesting, when the associative memory is used for page translation in a time-sharing mode of operation. Although the main use of the system is as a computer facility that may be shared simultaneously by up to fifteen users, it may also be used as an ordinary batch processor having a small experimental associative memory among its facilities. The magnitude of the ROS additions and modifications, in terms of numbers of microinstructions, is given.

A Simple Probability Model Yielding Performance Bounds for Modular Memory Systems

Abstract: A simple probability model is defined that represents modular memory systems under saturation demand for storage. An analysis of the model based on the theory of finite Markov chains leads to results that demonstrate the effects of changes in loading times and the number of modules on system performance.

The SDP-1 Stored-Program Computer

Abstract: A stored-program computer could be used to advantage on small scientific spaeeraft because of its flexibility. This paper describes the design and programming of a stored-program computer specifically adapted to this particular application. In order to be suitable for use in a small scientific spacecraft, a computer must have the following characteristics: reliability, low power drain, light weight, small size, problem-solving power, and flexibility. To meet these requirements, a computer was designed that has 1024 words of program memory and 512 words of data memory. The words are 12 bits in length and both memories are randomly accessed. In order to protect the program, the program memory is of the nondestrutive read-out type. The data memory is the conventional read/write variety. The computer is organized such that the power drain is small and less hardware is required by restricting parallel gating of information, number of registers, and number and complexity of instructions. Considerable effort has been devoted to programming the computer. Analysis shows that it takes on the order of two milliseconds to perform one of the floating-point operations. These limitations should be acceptable; the computer is not expected to be required to perform extremely complex or lengthy computations.