Showing papers on "Memory management published in 1969"

Organizing matrices and matrix operations for paged memory systems

Abstract: Matrix representations and operations are examined for the purpose of minimizing the page faulting occurring in a paged memory system. It is shown that carefully designed matrix algorithms can lead to enormous savings in the number of page faults occurring when only a small part of the total matrix can be in main memory at one time. Examination of addition, multiplication, and inversion algorithms shows that a partitioned matrix representation (i.e. one submatrix or partition per page) in most cases induced fewer page faults than a row-by-row representation. The number of page-pulls required by these matrix manipulation algorithms is also studied as a function of the number of pages of main memory available to the algorithm.

Defect-tolerant digital memory system

Abstract: A defect-tolerant memory system has means for determining when memory operations are addressed to locations that are defective, and for directing these operations to spare memory locations in a main memory. A content addressable memory is provided which has an argument section for storing the addresses of defective locations in the main memory, and a function section for storing a substitute address for each of the defective locations. When the content addressable memory determines that an addressed memory location of the main memory is one whose address is stored in its argument section, it directs the memory operation to a substitute location which has been assigned to that defective main memory location in its function section, thus enabling bypassing of the defective memory location.

Method and apparatus for allocating small memory spaces to a computer program

Abstract: An arrangement for allocation of small spaces in an addressable memory for use by a computer program. Blocks of memory are each subdivided into a predetermined number of equal areas. The base address of a block, the size of the subdivided areas in the block, and the availability status of each area in the block are specified in a status word associated with the block. Each block has its own status word stored in memory Whenever a particular size are a is needed in memory, the status words are examined to locate a block having an area of the required size available. If no area of the required size is available, a new block is established and a status word defining the new block is loaded into memory.

Study of "Look-Aside" Memory

Abstract: A small, but fast, associative memory can be used in a "look-aside" manner to improve the overall memory performance of a computer. For a 128-cell 100-ns associate memory working with a 1-us main memory, the effective memory cycle time is reduced to between 350-to 400-ns.

Memory maintenance arrangement for recognizing and isolating a babbling store in a multist ore data processing system

Abstract: A data processing system wherein the central processors are duplicated and are associated with a group of duplicated memory storage units over a set of duplicated communications buses is disclosed. Each memory unit is identified by a unique name code as well as a unique identification word stored in the memory unit independently of the name code. After a particular memory unit is addressed, the identification word received by the central processor in response thereto is analyzed for determining and isolating any babbling store which spuriously responds to the addressing of the desired memory unit.

Information processing system having free field storage for nested processes

Abstract: This disclosure relates to an information processing system employing plural processors which system is provided with a free field storage array to accommodate operands and data segments of any size and format. Each of the respective memory storage units is, in fact, structure oriented. However, pairs of such storage units are provided with isolation units having the capability of extracting and inserting fields of information independent of the memory structure. During a fetching operation, the isolation unit is adapted to fetch two contiguous parallel words and a shifting network or barrel switch is provided to position the desired field for transfer to the requesting device. During a store operation, the shifting network or barrel switch is employed to position incoming data into the proper bit location of the memory. The selected field is determined by the starting bit and the length field information provided by the memory control word and also by the type of operation requested. Each of the requesting devices is provided with its own interface unit that contains logic to construct a memory control word for each memory module involved in a fetch or store operation. In this manner, the entire array of memory units will appear to each of the requesting devices as being free field or without structure.

Equipment Configuration in Balanced Computer Systems

Abstract: A computer system is said to be balanced whenever the set of running programs presents a total demand, for both processors and memory, that matches the available equipment. The equipment configuration, here defined as the proper relative capacities of processor and memory resources in a balanced computer system, may be determined analytically.

Multistage queuer system

Abstract: Queuing systems for storing access request words for a rotating disc file or other sequential access device and implementing them individually as the device becomes ready to effect the corresponding data transfers. The access request words are stored initially in a large capacity cyclically scanned memory unit and are then transferred to a smaller capacity, more rapidly scanned memory unit as the corresponding file locations in the storage device are upcoming. The request words in the first memory are systematically compared for transfer to the secondary memory, where each is again systematically compared with the state of the sequential data file for access to it. If access for a request word in the second memory is not established when the corresponding data file address is reached, (device becomes ready for it) the request is transferred back to the first memory unit.

A Multiaccess Associative Memory

Abstract: Accessing of more than one word truly simultaneously in time from the same memory module is termed multiaccess. An associative memory with such a capability can be made from reset-set flip-flops. There are practical limitations to the number of words that can be simultaneously accessed. Some hardware and software implications of multiaccessibility are discussed.

A Simplified Analysis of Processor "Look-Ahead" and Simultaneous Operation of a Multi-Module Main Memory

Abstract: This paper focuses attention upon the design of a processor and memory system which is structured to achieve a satisfactory balance of processor speed and memory speed when both the processor and input–output controller are simultaneously competing for memory service. A mathematical model is developed to investigate the degree to which the processor is capable of overlapping memory references with instruction execution as a function of respective cycle times, the number of instruction "look-aheads," the number of independent memory modules, and input–output traffic. Utilizing this model, design trade-offs and performance indices are graphically examined for a hypothetical system.

Silicon-on-sapphire complementary MOS circuits for high speed associative memory

Abstract: The utility of associative memory in a wide variety of information handling systems has been long recognized and in the early 1950's such memory systems were proposed for implementation through cryotron logic and storage arrays. Cryogenic element technology afforded the ingredient of compatible logic and memory within a basic cell, a requirement essential to the practical realization of associative memories. To date, such an approach has not been successful due mainly to processing difficulties connected with thin film elements operating in a liquid helium environment. Other approaches, involving the use of multi-apertured magnetic elements, have been proposed and implemented, but the resultant cost was prohibitive due to complexities of peripheral electronics as well as the magnetic storage element itself. Furthermore, systems of this type have relatively long parallel search times (~ 10 μsecs) especially if access is on a serial-by-bit basis. These considerations have seriously limited the applicability of associative concepts in all forms of data processing and have resulted in a situation where system designers do not consider associative memory as a solution to a given problem in spite of many obvious advantages in applications such as sorting, merging, pattern recognition, and most recently, memory allocation in time shared computers.

On the Design of Bayesian Storage Allocation Algorithms for Paging and Segmentation

Abstract: This short note focuses attention upon techniques for dynamic memory allocation in multiprogrammed systems which employ the addressing mechanisms of paging and segmentation. Here, event indicators and mathematical tools are presented which supply characterizations of the paging and segmentation addressing processes. It is shown that these statistical characterizations form data bases which can be used to derive Bayesian storage allocation algorithms conditionally based upon usage, demand, and processing history. It is argued that these characterizations, and algorithms similar to those constructed here, provide a flexible basis for efficient memory management in multiprogrammed, and by extension, time-shared environments. Although emphasis is directed to managing primary (main) memory residence, the techniques could be extended to govern memory management for a hierarchy of storage devices.

A Glass Delay Line Content-Addressed Memory System

Abstract: A glass delay line content-addressed memory system is described which was designed and constructed for use with a general -purpose computing system. A functional description of the system is given along with solutions to the major problems of implementation.

Mass memory in computer systems

Abstract: Mass memory has three distinct uses in a computer system. Each places distinct requirements on the technology. This paper gives a personal estimate of the requirements for each use in the next five years. 1) A mass memory may be used as a cheaper extension of main memory. For this use, cycle time must be \leq 10 \mu s, capacity 1-8 million bytes, addressed to the word, read-write, and cost per bit must be less than 1/4 that of main memory. 2) A mass memory may be used for residence of the control program and compilers. For this use, cycle time must be \leq 10 \mu s, block transfer rate ≥ 1 million byte/s, capacity 8-32 million bytes. It may be read-only (if easily changeable) and addressed only in blocks. Cost per bit must be less than 1/10 that of main memory. 3) A mass memory may be used for storage of an on-line data base. Such a memory must have >500 million bytes capacity, a cycle time <100 ms, may be block addressed, may be read-only for some uses but not most. Cost must be <0.004 cent/bit to compete with today's technologies. Special memory properties, such as content-addressing, distributed logic, etc., will not redeem a memory that is not competitive on cycle time, capacity, block transfer rate, and cost.

Fault location in memory systems by program

Abstract: The subject of automatic fault location in memory systems by program so far has been neglected in computer literature. A program (AMNESA) has been written at Honeywell that not only detects failures in memory, but also diagnoses the cause of the failure. This paper describes the approach used in the writing of AMNESA. It is also shown that this approach can be used for different memory organizations.