Showing papers on "Memory management published in 1970"

A Logic-in-Memory Computer

Abstract: If, as presently projected, the cost of microelectronic arrays in the future will tend to reflect the number of pins on the array rather than the number of gates, the logic-in-memory array is an extremely attractive computer component. Such an array is essentially a microelectronic memory with some combinational logic associated with each storage element. A logic-in-memory computer is described that is organized around a logic-enhanced ``cache'' memory array. Used as a cache, a logic-in-memory array performs as a high-speed buffer between a conventional CPU and a conventional memory. The effect on the computer system of the cache and its control mechanism is to make the main memory appear to have all of the processing capabilities and almost the same performance as the cache. Operations within the array are naturally organized as operations on blocks of data called ``sectors.'' Among the operations that can be performed are arithmetic and logical operations on pairs of elements from two sectors, and a variety of associative search operations on a single sector. For such operations, the main memory of the computer appears to the program to be composed of a collection of logic-in-memory arrays, each the size of a sector. Because of the high-speed, highly parallel sector operations, the logic-in-memory computer points to a new direction for achieving orders of magnitude increase in computer performance. Moreover, since the computer is specifically organized for large-scale integration, the increased performance might be obtained for a comparatively small dollar cost.

A study of interleaved memory systems

Abstract: There is frequently a severe mismatch between achievable processor and memory speeds in today's computer systems. For example, the CDC-7600 has a 27ns (nanosecond) processor cycle time and a 270ns memory cycle time; the IBM-360/91 has a 60ns processor cycle time and a 750 ns memory cycle time. In order to obtain the desired increase in the effective memory speed, an efficient memory system must use such techniques as interleaving memory modules and implementing an automatic level in a memory hierarchy (e.g., a slave memory as in the IBM-360/85 or 195 and the CDC-7600). In the past, interleaving was often studied by simulation using a random address generating source to obtain memory requests. This paper discusses results of mathematical analyses of models of interleaved memory systems. In these investigations the properties of addresses generated by instructions and data have been distinguished.

Computer Simulation of Short-Term Memory: A Component-Decay Model

Abstract: Publisher Summary This chapter discusses the computer simulation of short-term memory. The first of these systems is the sensory storage or very-short-term memory, viewed as a peripheral or perceptual storage. There is general agreement that information stored in this type of memory decays with time and is lost in a matter of a few seconds or less. Another type of memory, short-term memory (STM), is the focus of these various models. Despite general agreement that information is lost from STM, there are two views as to the nature of this loss. One view is that information is lost as a result of decay; an alternative is that STM has a limited capacity so that items are lost by being replaced by new items entering the system. The model represents the human at an information-processing level of description. At this level, the human is viewed as having available a variety of processing mechanisms which can be employed to operate upon information.

Data storage system with means for eliminating defective storage locations

Abstract: A data storage system containing an integrated memory for the storage of words of a given number of bits wherein the memory is constructed so that each word address in the memory is provided with a number of memory elements in excess of the given number of bits of the words to be stored and any unusable memory elements in the matrix are modified so that when interrogated they cause a distinctive signal to be produced. In response to these distinctive signals circuitry is provided for directing the data bits into those bit locations or columns of a word address containing only usable memory elements during the writing operation and for compacting or eliminating the gaps between the data bits as the result of unusable memory elements in certain bit locations of a word address during read out. A number of techniques for identifying the unusable memory elements upon interrogation, as well as additional features and schemes for improving the operation of such data systems are also disclosed.

Sorting in a paging environment

Abstract: This sorting study was part of an extensive measurement project undertaken on the M44/44X, an experimental paging system which was conceived and implemented at IBM Research in order to explore the virtual machine concept. The study was concerned with the implementation of sorting procedures in the context of the dynamic paging environment characteristic of virtual memory machines. Descriptions of the experimental sort programs and analysis of the performance measurement results obtained for them are presented. The insight gained from the experimental effort is used to arrive at a set of broad guidelines for writing sort programs for a paging environment.

Memory control system which enables access requests during block transfer

Abstract: A buffer memory control system for a buffer memory having a shorter access time and a smaller number of memory locations than a main memory. If the requested information is not present in the buffer memory, the block including the requested information is transferred from the main memory to the buffer memory. When a read or write request for the information of another block which is different from the said block is made during the transfer of the latter block, the transfer of the block is interrupted temporarily to immediately effect the reading from or writing in the another block of the buffer memory, after the completion of which the transfer of the block is resumed if the requested information of the another block is present in the buffer memory.

Information processing system having means for dynamic memory address preparation

Abstract: This disclosure relates to an information processing system having means to dynamically prepare memory addresses for any particular element in a field of variable length which field may reside in any portion of the systems storage. Each desired element is specified by a descriptor which contains all the information necessary for such specification and the system is provided with an evaluation section which is adapted to evaluate the descriptor to extract that information necessary to create the memory control word which is employed to address the system storage. Because of the dynamic nature of the descriptor evaluation or memory address preparation, absolute memory addresses need not be created until such time as they are required. Furthermore, the method and apparatus employed allow for the accessing of a hierarchy of nested structures within the system storage.

Integrated-circuit content-addressable memories

Abstract: This paper will cover IC-content addressable memory designs employing simple memory cells (six to nine transistors per cell), and resolver circuits capable of automatically resolving multiple responses and performing other special logic operations.

Capture combination system

Abstract: A capture combination system for use in an electronic organ provides rapid reprogramming of the entire combination memory while permitting manual selection of desired stop combinations at any time. Desired stop combinations are selected for each piston and set into the working memory of the system. These combinations, upon command, are transferred from the working memory to a storage or external memory. A full combination of stop settings may be stored on the external memory by transfer from the internal memory, and a number of such external memories corresponding to a number of different full combinations of stop settings thus may be prepared and, subsequently, selectively presented to the system as desired. The combination settings from the external memory are transferred upon command into the internal working memory for establishing the desired combination of stop settings therein. Transfer into or out of the external memory requires but a few seconds. Whenever desired, the working memory may be altered to modify one or more stop combinations, whether set manually, or entered therein from the external memory and, in the latter case, while retaining the combinations recorded in the external memory.

The management of a multi-level non-paged memory system

Abstract: There is a clear tendency for large-scale and, especially time-sharing computer systems to have several levels of random access memory with gradations in access time, degree of addressability, and functional capability. In our configuration at The University of Texas at Austin these are a high-speed magnetic core memory, an extended core memory of magnitude 4 times the size of the main memory, and 4 large, fast disks. An extensive literature has already developed on the management of multi-level systems where the main memory is structured in pages, usually with an extended logical addressing space.

The Organization of High-Speed Memory for Parallel Block Transfer of Data

Abstract: This paper describes the organization of a multi-module memory, designed to facilitate parallel block transfers. All modules are assumed to be identical, and the individual modules can fetch or store no more than one word or word group during any single memory cycle. Parallel block transfers are made possible in multimodule memories by utilizing a device called the memory circulator and by organizing the memory in a particular way. The memory circulator consists of a bank of interconnected registers, one for each memory, and control circuitry. The memory system is organized so that ascending logical addresses are distributed cyclically among the modules. If there are 2b modules, then any individual word is accessed by using the least significant b bits of a memory address to select a module and by using the remaining bits to select an address within a module. The memory circulator can load and store a contiguous block of 2b words by selecting all modules and broadcasting a single address to all modules. A contiguous block can be displaced in memory by a multiple of 2b words by broadcasting different load and store addresses for a block of data. The circulator control circuitry includes a masking capability so that blocks smaller than 2b can be moved in this fashion. When the displacement of a block transfer is not a multiple of 2b a physical circulation of the data in the memory circulator registers is required.

On Static Memory Allocation in Computer Systems

Abstract: An algorithm for allocation of memory resources is presented making use of a priori information about a computer program. This static allocation algorithm is based on a directed graph model of computations with particular attention to the memory allocation of programs assigned for execution on multiprocessor systems.

Some Effects of Advances in Memory System Technology on Computer Organization

Abstract: Technological improvements in memory systems in the '70s are expected to have a significant impact on computer organization. The expected advances will result in associative memories at reasonable cost, small-capacity random-access memories at low cost, and mass memories with greatly reduced access time. Possible implications or effects of each of these advances on the organization or design of future computer systems are identified.

Associative capabilities for mass storage through array organization

Abstract: Since computers first came into wide usage, digital systems designers have been intrigued by the possibilities of associative or content addressable memories. The concept is quite easy to understand; whereas, in the conventional case, the address is furnished to the memory and the data stored at that location is the expected result, in the associative reference, the data is furnished and the expected result is a list of all addresses which contain matching data. Up to now, however, the physical systems which exhibit the requisite symmetry to realize this concept have been necessarily very costly because the commonly used, low cost, random access memories do not easily lend themselves to this new operation. Those digital systems designers who predicted widespread use of associative memories by the late 1960's are found in retrospect to have seriously underestimated the difficulty in implementing thin magnetic film or superconducting memory systems, on which these forecasts heavily depended.

Memory Protection in Multiprocessor Computer Systems.

Abstract: : The paper presents a study of the memory protection problem in a multiprocessing computer system. The general area of memory protection is investigated in terms of the following three categories: memory access conflict resolution, private data protection, and common data protection. Memory access conflict resolution may be subdivided into two areas--fixed and dynamic priority assignment. Special emphasis is given to a procedure for the design of a dynamic memory access conflict resolution circuit. An example of this procedure is also given. Techniques for the protection of private and common data within memory are reviewed. (Author)