Showing papers on "Memory management published in 1974"

Method for providing a substitute memory in a data processing system

Abstract: A method for substituting one memory module for another, faulty, memory module comprises designating and marking a memory module as the substitute module, which, upon detection of a fault in the other memory module, is inhibited from responding to its own address when called, and responds to the address of the faulty module whenever the latter is called.

A simple linear model of demand paging performance

Abstract: Predicting the performance of a proposed automatically managed multilevel memory system requires a model of the patterns by which programs refer to the information stored in the memory. Some recent experimental measurements on the Multics virtual memory suggest that, for rough approximations, a remarkably simple program reference model will suffice. The simple model combines the effect of the information reference pattern with the effect of the automatic management algorithm to produce a single, composite statement: the mean number of memory references between paging exceptions increases linearly with the size of the paging memory. The resulting model is easy to manipulate, and is applicable to such diverse problems as choosing an optimum size for a paging memory, arranging for reproducible memory usage charges, and estimating the amount of core memory sharing.

Plural control memory system with multiple micro instruction readout

Abstract: A microprogramming control system employing a plurality of low read rate control memories, for storing micro instructions, individually addressed in turn at a rate greater than the read rate of each memory. Each addressed control memory reads out a plurality of micro instructions. A selection circuit receives the plurality of micro instructions, in time shared fashion, read out in turn from each addressed control memory, then selects and gates a single micro instruction to a storage device. One portion of the selected micro instruction is designated as an address for the next micro instruction to be read out from the same control memory, and is accordingly gated to an address storage device at the input of the corresponding control memory.

Performance of replacement algorithms with different page sizes

Abstract: Dynamic memory management is an important advance in memory allocation, especially in virtual memory systems. In this paper we consider the case of paged memory systems — i.e., systems whose physical and logical address space is partitioned into equal sized blocks of contiguous addresses. Paged memories have been used by many computer systems. However, the relationships among page fault frequency (the frequency of those instances at which an executing program requires a page of data or instructions not in main memory), efficiency, and space-time product with various replacement algorithms and page sizes are still not sufficiently understood and are of considerable interest.

Dynamic Memories with Rapid Random and Sequential Access

Abstract: We propose a new architecture for dynamic memories in which the contents of any cell in memory can be accessed by applying a sequence of two primitive memory operations. The advantage of our memory over previous designs is its fast sequential access. Any word in an n cell memory can be accessed in 0(log n) steps. However, once two consecutive words have been accessed, following words can be accessed in one step per word.

An Organization for a Highly Survivable Memory

Abstract: A memory organization is considered for which a large number of faults can be tolerated at a low cost in redundancy. The primitive element in the memory is a large-scale integrated (LSI) chip that realizes a section of memory, b bits wide by y words long, together with an address decoder for the y words. The chips (including spares) are connected via a switching network so that the memory can be reconfigured effectively in the presence of chip failures. The main results of the paper relating to the switching network are as follows.

Computer systems overlap of memory operation

Abstract: This relates to a digital computer system having a plurality of memories. Retrieval operations in the memories are overlapped so that a retrieval operation in one memory can be initiated before a previously initiated retrieval operation in another memory has been completed.

Reconfigurable decoding scheme for memory address signals that uses an associative memory table

Abstract: This specification describes an associative memory decoder for a memory system in which the units in the memory system are reconfigurable both in size and in number. The decoder is designed to take an address for that memory system and address memory space in the memory system irrespective of the amount of storage in the system so that the decoder has to change as memory capacity is added or subtracted from the memory system.

Experimental data on page replacement algorithm

Abstract: Although paged VM (Virtual Memory) systems are being implemented more and more, their full capabilities have not yet been realized. Early research in this field pointed to possible inefficiencies in their implementation. Subsequent studies, however, led to the conclusion that paged VM systems could provide a productive means to run large programs on small main memory, if proper techniques are employed. One of the most influential of these is the choice of an efficient page replacement algorithm (RA) to minimize page traffic between the different levels of memory.

A virtual memory for microprocessors

Abstract: A virtual memory system for microprocessors is described. The system is designed to be extensible, to minimize software and execution overhead and to minimize operating system requirements. Specific application of the virtual memory system with the INTEL 8080 microprocessor is given, describing the necessary software constraints and operating system requirements.

Analyse d'un algorithme de gestion simultanée mémoire centrale -- disque de pagination

Abstract: Commonly used memory management strategies in a paged environment optimize separately the page-fault rate (by proper choice of a replacement algorithm) and the response time of the paging drum (by a shortest-access-time-first discipline with multiple sectors). In this paper we consider replacement strategies which attempt to maximize useful CPU utilisation and hence throughput by choosing the page to be replaced on the basis of its probability of reference as well as on the rapidity with which the page can be removed from main memory, assuming that a fixed-head disk or drum is used as a secondary memory. An analysis of the approach is given using a mathematical model. Analytical results for the gain in CPU utilisation are obtained under mono-programming and numerical examples are presented illustrating the effects of variation of program behaviour and of variants of the replacement strategy.

Measurements of the virtual memory demands of Algol-60 programs (Extended Abstract)

Abstract: Programming languages such as Algol-60 use block structure to express the way in which the name space of the current environment, in the contour model (1) sense of that word, changes during program execution. This dynamically-varying name space corresponds to the virtual memory required by the process during its execution on a computer system. The research to be presented is an empirical study of the nature of the memory demands made by a collection of Algol-60 programs during execution. The essential characteristics of any such resource requiest are the amount of memory requested, and the holding time for which the resource is retained and these distributions will be presented for several components of the virtual memory required by the Algol programs.

On the Memory Conflict Problem in Multiprocessor Systems

Abstract: This paper presents quadratic programming models of memory conflict in multiprocessor systems where main memory consists of a set of memory modules common to all processors. Two jobs (programs) are said to be in conflict, or subject to memory conflict, whenever at a given time portions of them must be executed in the same memory module by different processors. We are interested in minimizing the total conflict by the proper assignment of jobs to main memory. Two allocation models are considered: one in which the jobs-to-memory assignment is to be made independent of any particular processors-to-jobs schedule, that is, expected memory conflict is to be minimized over the space of all schedules; and the second in which a definite processor schedule is assumed to be available. For both models, algorithms are formulated for the assignment of jobs to memory.

An experimental analysis of program reference patterns in the multics virtual memory

Abstract: This thesis reports the design, conducting, and results of an experiment intended to measure the paging rate of a virtual memory computer system as a function of paging memory size. This experiment, conducted on the Multics computer system at MIT, a large interactive computer utility serving an academic community, sought to predict paging rates for paging memory sizes larger than the existent memory at the time. A trace of all secondary memory references for two days was accumulated, and simulation techniques applicable to "stack" type page algorithms (of which the least-recently-used discipline used by Multics is one) were applied to it. A technique for interfacing such an experiment to an operative computer utility in such a way that adequate data can be gathered reliably and without degrading system performance is described. Issues of dynamic page deletion and creation are dealt with, apparently for the first reported time. The successful performance of this experiment asserts the viability of performing this type of measurement on this type of system. The results of the experiment are given, which suggest models of demand paging behavior.

Circulating shift register memory having editing and subroutining capability

Abstract: A circulating shift register memory used in a hand-held programmable calculator is described in which the informational words of data contained therein are edited by selectively including one-word storage register in or excluding such registers from the circulation path of the memory. The selectable storage elements contain new or discardable data at the time of their inclusion in or exclusion from the circulation path. Logic circuitry for controlling the number of storage elements in the circulation path is responsive to unique control words which share memory space with the information words. The same circuitry and a similar method are used for subroutining in the same memory.

Organization for Execution of User Microprograms from Main Memory: Synthesis and Analysis

Abstract: Microprogrammed computers are categorized by main memory/control storage (CS) organization for use in analysis of methods of allowing dynamic user microprogramming. A system design is described in which user microroutines are executed directly from main memory, rather than from writable control storage (WCS). This design is analyzed and compared with the use of WCS for allowing dynamic user microprogramming in a multiprogramming system. It is shown that the use of main memory for microprogram residence is a viable alternative in many user job environments.

Multiprogramming and program behavior

Abstract: Dynamic multiprogramming memory management strategies are classified and compared using extant test data. Conclusions about program behavior are then drawn.

Optimal memory management in a system with garbage collection

Abstract: This paper discusses the problem of determining cost-saving policies for obtaining memory in systems with garbage collection, in particular the run time system of DEC-10 Simula. A mathematical model of the problem is defined and a policy is obtained from the model and a certain amount of heuristic reasoning. The implementation and validation of the policy is also described.

A Problem in Multiprogrammed Storage Allocation

Abstract: A simple mathematical model of (time-varying), program demand for main memory is developed. The model is based on the use of the immigration-death process, and is particularly suited to modeling the total demand of several programs. The goal is to study the behavior of the system under various schemes of dynamically allocating main memory among the programs. In particular, given some sort of working-set storage management we study what margin of free space should be reserved when programs are moved in and out of main memory, so that the frequency of overflow-underflow events is kept reasonably low, while at the same time maintaining a reasonably high degree of multiprogrammig.

AAPL: An Array Processing Language

Abstract: AAPL is a dialect of APL designed to be more amenable to compilation than the standard version of APL. The principal differences include the use of name prefixes, the ability to accept a limited character set for denoting the primitive functions, some variations and restrictions on the use of the program-branching primitive, and some additional I/O primitives. The reasons for each of these modifications are discussed in detail, as well as the implications for transportability between the two dialects. An implementation of AAPL has been undertaken for the STARAN Associative Processor. An outline of this implementation and a progress report on the work is presented.

Stack Replacement Algorithms for Two-Level Directly Addressable Paged Memories

Abstract: In this paper we consider the application of the stack algorithm concept to a two-level paged storage hierarchy in which both levels are directly addressable by the central processor. Since both levels are directly addressable, pages need not reside in the first level of memory for a reference to be completed. The effectiveness of a page replacement algorithm in such a storage hierarchy is measured by the frequency of references to the first level of memory and the number of page promotions. It is shown that the stack algorithm concept can easily be extended to apply to two-level directly addressable memory hierarchies. A class of page replacement algorithms called stack replacement algorithms is defined. An efficient procedure exists for collecting data on the performance of stack replacement algorithms.

DOT memory systems

Abstract: New developments in memory technology are attempting to fill the void between main and secondary storage by providing alternatives to rotating storage devices with considerable performance advantages over the latter and at far less cost than main memory. The greater emphasis being placed on the use of virtual storage techniques in data processing systems has reaffirmed the need for fast, reliable, low cost memory devices with much reduced page swapping times. A principal developmental effort in this area is the development of moving magnetic domain techniques. The DOT, or Domain Tip, storage technology has an intrinsic capability for providing non-volatile, fast access, block or page-oriented memory systems. The relatively few steps required to manufacture DOT devices and the simple planar packages used offer the potential of low manufacturing cost. The memory medium, insensitive to temperature and to shock and vibration, is electronically passive with no connections being required between the storage medium and the drive or sense electronics. These factors suggest the capability of the DOT of providing highly reliable solid state memory.

Chapter 4 – memory management

Abstract: Publisher Summary This chapter discusses the memory management functions and the general linkage problem. Memory management may be thought of as three functions, which include naming function, memory function, and content function. A given name may refer to different objects, depending on the context in which it is used. The problem of matching names with their corresponding objects is pervasive in software systems. In block structured programming languages, a given name can refer to several different variables, depending on the block in which it is used. In operating systems the context with which one is generally concerned is that of the user program. Several users may have the same names for different files or procedures. It is the job of the operating system to associate the correct object with every name within each user context. Each separately compiled procedure or data structure, called an object module, is coded relative to address zero. Modules cooperate, so that one module can call a procedure or can access data in another module.

On the Modeling of Demand Paging Algorithms by Finite Automata

Abstract: Two finite automata are devised for modeling two classes of demand paging algorithms. The first one of one input and three outputs models the class of algorithms with a constant amount of allocated space. The second one of one input and six outputs models the class of algorithms with a variable amount of allocated space. Some evaluation techniques are developed following each model. The memory states of the first class algorithm with the Least Recently Used (LRU) replacement policy and the working set model of the second class are recursively defined by strings of the loaded pages. The adopted replacement policy and the state string updating procedure are imbedded in the recursive definition of memory states. Properties of some algorithms are developed to fit the finiteness assumption of a reference string.

ATOPSS (Adage Tutorial Operating System Simulator): A computer graphic simulation of a discrete time operating system for introducing elementary concepts

Abstract: This paper introduces two films made under a discrete time operating system simulator that is programmed and run on an Adage 30 Graphics Terminal at The Pennsylvania State University.Using the graphic hardware available on the system, the simulator displays the contents of all major operating system queues along with the contents of memory and active hardware. The observer can then watch the flow of information from one job step to another in the discrete time simulation of different operating system configurations.Various parameters specified by the user allow the operating system simulator to operate under different hardware configurations and operating system strategies such as multiprogramming and multiprocessing, along with preemption and different memory allocation techniques.

On Program Placement in a Directly Executable Hierarchy of Memories

Abstract: The efficient utilization of a two-level directly executable memory system is investigated. After defining the time and space product resulting from static allocation of the most often referenced pages, from paging, and from an optimal algorithm when the amount of primary memory is constrained, we introduce a learning algorithm. Its basic feature is to monitor references in such a way that it prevents seldom accessed pages to be brought into primary memory. The additional hardware requirements are not extensive. Simulations attest to the validity of the concept, and show that results are comparable with those obtained from the static allocation (the latter being impractical since it requires the knowledge of the whole reference stream) and superior to those obtained with paging. In the case of application programs, contributions to the learning algorithm can be made at compile time. Algorithms and data stuctures necessitated in an optimizing phase of the compiler are described.

A Study of the Electrochemical Cell as a Storage Element for the Memory Access Gap

Abstract: A memory device is proposed which is intended to fill the memory access gap, i.e., whose speed, cost, and capacity are intermediate between those of the electronic and electromechanical memories. Information is stored by electroplating metal on one or the other of two electrodes. The memory is random access and nonvolatile. Selection is by a coincident-voltage technique and stack operation is similar to the operation of core memories. The estimated driving requirement of a selection line is 1 V at 1 mA, indicating that small-area IC logic circuits will be able to drive the memory. The proposed memory will be mass-fabricated and the cost is foreseen as being primarily the interconnection cost between the IC decoding and sensing chips and the bit select conductors. The cost is estimated at 5 mcents/bit.

Algorithmic generality in memory management design

Abstract: As computer systems grew in complexity, the area of memory management has become increasingly important. In future operating systems what is needed is a generalized, flexible, modular, and open ended-design of the functional modules (e.g. memory management modules). To achieve these properties, sufficient ingenuity and effort are required during both design and implementation. This paper outlines an approach which should lead to a design having these properties. A memory management system was designed using this generalized approach. The system was subsequently modeled and implemented in SIMSCRIPT I.5 as a test case. The model and the successful results prove the feasibility of the approach and can be used to evaluate different memory management schemes. The functional modules within the model are general so that their mode of operation can be set from outside (this may be called parametric generality). However, the actual algorithm employed for memory management can be tailored at the site generation (or system generation) time using a convenient specification language. This design strategy is best characterized by the term "Algorithmic Generality."