Showing papers on "Memory management published in 1975"

Some principles of memory schemata

Abstract: Publisher Summary A fundamental aspect of the structure of material contained within a large, intelligent memory system is that the contexts, in which units of the stored information are accessed, are critically important in determining the way that information is interpreted and used. Most of the schemes, currently under active consideration, can be viewed as variants of list structures or semantic network structures. This chapter discusses some implications of these memory structures in regard to how the connections among different memory units are formed and interpreted, and some of the issues of processing that arise when these memory structures are used. It also discusses the nature of memory reference processes that can lead automatically, without particular effort, to the richness of the retrievals that it is believed to be a fundamental property of human memory. When two or more processes use the same resources at the same time, they may both interfere with one another, neither may interfere with the other, or one may interfere with a second without any interference from the second process to the first. The important principle is that a process can be limited in its performance either by the amount of available processing resources, such as memory or processing effort, or by the quality of the data available to it. Competition among processes can affect a resource-limited process, but not a data-limited one.

Multiprogrammed memory management

Abstract: A queueing network is used to show that the page-fault-rate functions of active programs axe the critical factors in system processing efficiency. Properties of page-fault functions are set forth in tenns of a locality model of program behavior. Memory management policies are grouped into two fixed-partition and three variable-partition classes acording to their methods of allocating memory and controlling the multiprogramming load. It is concluded that the so-called working set policies can be expected to yield the lowest paging rates and highest processing efficiency of all the classes.

Data security system employing automatic time stamping mechanism

Abstract: A data security system employing an automatic time-stamping mechanism for stamping a current time code in a data storage area or register associated with each storage section of a memory or an auxiliary storage device, such that each data read or write in a memory storage section updates the time code device. For every storage section of a memory, there is a time stamp storage element associated with it. Similarly, there is a time stamp storage element associated with every data channel. Whenever a storage section of memory is read from or written into the time stamp in the form of a unique binary number from a clock, indicating the current time of day and the date, is inserted into the time stamp storage element associated with that memory storage section. Examination of the contents of each time stamp storage element enables determination of whe the last read or write in a storage section occurred. A full memory address register is used to read or write data in the memory while only special high order bits of the memory address register are used to read or write the time stamp storage element associated with the memory storage section. The system provides a mechanism which automatically marks blocks of data with a time code as they are read from or written into memory and such mechanism cannot be bypassed by program means.

A Simple Hardware Buddy System Memory Allocator

Abstract: The design of a simple hardware memory allocator is described, which allocates blocks of different lengths L = 2h = K, K-1,..., K-n in a memory according to the buddy system algorithm. The binary tree, representing the distribution of free and used blocks in memory is mapped into a set of shift registers. They are connected for end-around shifting and clocked with frequencies different for each register, preserving thereby the internal structure of the binary tree. A small counter, attached to each shift register in the set holds the address of the first free block and can be read out on request within 0.5 μs. A simple control unit realizes the algorithm. Having answered a request the system needs about 130 μs to compute the addresses of free blocks in a total of 511 blocks managed by the device.

Fail soft memory

Abstract: A firmware/hardware mechanism in a general purpose computer system automatically provides alternate addressing paths for addressing data in the same or another main memory module when a failure is detected in a portion of the main memory or main memory module. Two types of memory failures are detected and an alternate path provided for each type of failure. The first type is a failure in a memory which is not detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an exception processing mechanism to provide an alternate path to a good memory module. The second type of failure is detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an interrupt processing mechanism to provide an alternate path to a good memory module.

Automatic configuration of main storage addressing ranges

Abstract: An apparatus for automatically selecting the one of a plurality of main storage units containing a range of addresses which includes the address of the data to be accessed. The storage capacity of each storage unit is simultaneously compared with a portion of the memory address indicative of the data to be accessed to determine whether the memory address is greater than, less than or equal to the storage capacity of any memory storage unit. If the memory address is greater than the capacity of a given memory storage unit but less than or equal to the storage capacity of the next adjacent memory storage unit, that unit is automatically selected for response to the full memory address.

Terabit memory systems: A design history

Abstract: The TBM memory system development effort is described, starting with initial concepts in 1965, through feasibility experiments in 1966, engineering model in 1968, manufacturing prototype in 1971, first delivered system in 1972, and system developments that have occurred in the last three years. The evolution of the initial concepts is illustrated by examining the features incorporated in these successive models. Projections describing possible future systems are also made.

Queueing network model of interactive computing systems

Abstract: A closed queueing network model with state dependent routing probabilities is developed for the study of interactive computing systems which use swapping as a memory managmnent strategy. An algorithm to obtain an approximate solution of the mathematical model is proposed. Based on meamuements of a dual-processor PDP-10 system, the model is found to be better in predicting the system performance than the classical model without state dependent routing probabilities.

A machine and configuration independent Fortran: Portable Fortran {PFortran}

Abstract: Describes the design of a programming language suitable for writing portable, machine independent programs. Based on Fortran, and implemented at the lowest level by means of subprograms, this language (PFortran) provides features which allow programs to be designed so as to be rather insensitive to computer architecture (byte versus word addressable) or to main memory size.

Student's computer

Abstract: This disclosure describes a novel computer system in which a large capacity, serial storage medium, on which standardized programs and data banks can be economically recorded, as the primary memory component. The operating software program is not transferred into core memory, as is typical of present day computers, but remains resident in the memory on which it has been prerecorded. The resulting system is lower in cost, and especially suitable for using standardized programs which can be distributed in machine compatible form at modest cost.

How to evaluate page replacement algorithms

Abstract: The designer of a virtual memory system can obtain accurate estimates of the average memory requirements of programs running in the system by weighting the average allocation during execution intervals with the average allocation during page waiting intervals. We show how to combine the averages, how to use the measure to determine the size of primary memory while achieving system balance between memory and processor demands, and how to partially order the performance of paging algorithms.

Buffer memory control method

Abstract: PURPOSE: When the main memory is shared by other data processing equipment, jamming by the other processing equipment is avoided by shortening the working cycle time of the address indexing equipment than that of the buffer memory. COPYRIGHT: (C)1976,JPO&Japio

The Place of Computers in Medicine

Abstract: To the computer specialist the thoughts of applying his technology to the determination and preservation of his own and society's health by computer is very attractive. To the physician the computer appears as a complex unknown. Depending on his computer-related, experience, it may be a threat or a tool.

Memory steering in a data processing system

Abstract: In an input/output data processing system employing local and remote memory and paged data storage, memory steering is included in the address development, thus eliminating the need for special memory configuration logic. Words used in constructing absolute memory addresses for data fetches include address portions referencing local/remote memory, specific memory, and/or lack of memory residence for effecting a system fault procedure.

Projections of data processing memory usage

Abstract: An overview of the demand for various types of memory used with computer systems is presented. The types of memory and the major memory applications are discussed and analyzed for trends which will affect the amount and type of memory required for future computer systems. General business and scientific computers are by far the largest users of memory. This trend will continue with the advent of centralization of files, teleprocessing, and the use of virtual memory techniques to reduce the cost of memory and provide for machine-controlled memory management. The amount of on-line or direct-access memory available to users will continue to increase permitting extremely large files, program libraries, and information libraries which will be accessed by remote terminals and CPU's. Additional large demands for memory are developing in minicomputer-and microcomputer-based systems for industrial, business, and scientific uses as well as in intelligent terminal and data entry devices. These smaller processors, while contributing to the trend toward distributed processing, will also serve as the controllers for distributed file storage. The recent developments in the field of "mini" storage devices will be extended to provide even lower cost storage for use with small systems.

A time-wise hierarchy imposed upon the use of a two-level store

Abstract: Following general design principles a paging system has been developed in which has been aimed at high efficiency and a strong separation between store management and processor scheduling and a minimal influence of the program mix upon the system's performance. It is, furthermore, described how some dedicated hardware can be expected to contribute effectivel to memory management and the prevention of thrashing. Finally, the properties of the system should be such that a mismatch between configuration and workload gives a clear indication as to what reconfigurations seem indicated.

Functional aspects of information processing in human memory

Abstract: This study was designed to investigate the assumption of two-storage theories of human memory that information after being preprocessed in a sensory register is directly transferred into a short-term storage system. To test this assumption a reaction-time task was used. Ss had to scan the contents of their short-term store. Some of the elements of short-term memory target sets were associated with test stimuli by learning trials preceding the memory search.