Showing papers on "Memory management published in 1982"
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02 Jun 1982TL;DR: In this paper, a virtual storage system for use in conjunction with a host computer is described, which divides user-defined data sets into blocks of a size convenient for storage on, e.g., magnetic media and individually assigns these blocks to locations determined external to the host.
Abstract: A virtual storage system for use in conjunction with a host computer is disclosed. The system features a memory control processor external to the host computer which divides user-defined data sets into blocks of a size convenient for storage on, e.g., magnetic media and individually assigns these blocks to locations determined external to the host. In this way, the extent of a particular data file is not specified by the user; nor is empty space allocated in anticipation of future use. The virtual memory system may additionally comprise a high speed cache memory for receiving data written to the memory system at high speed from the host. Data anticipated to be the subject of future requests can be staged to the cache, so that it can be supplied to the host at high speed, thus improving system performance. Data compression and decompression may be incorporated in the storage system. Numerous data back-up and automated recovery processing operations may additionally be performed by this system without specific instruction from the host.
295 citations
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TL;DR: A memory system designed for parallel array access based on the use of a prime nwnber of memories and a powerful combination of indexing hardware and data alignment switches is described.
Abstract: In this paper we describe a memory system designed for parallel array access. The system is based on the use of a prime nwnber of memories and a powerful combination of indexing hardware and data alignment switches. Particular emphasis is placed on the indexing equations and their implementation.
187 citations
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TL;DR: The effective bandwidth in a multiprocessor with shared memory with N processors and N memory modules is compared using as interconnection networks the crossbar or the multiple-bus.
Abstract: In this paper we compare the effective bandwidth in a multiprocessor with shared memory using as interconnection networks the crossbar or the multiple-bus. We consider a system with N processors and N memory modules, in which the processor requests to the memory modules are independent and uniformly distributed random variables. We consider two cases: in the first the processor makes another request immediately after a memory service, and in the second there is some internal processing time.
128 citations
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15 Aug 1982
TL;DR: A real-time, effectively distributed, garbage collector of the mark-sweep variety, called the marking-tree collector, is shown to accomplish reclamation in parallel with the main computation, with no centralized data or control other than a logical rendezvous between phases of the collector.
Abstract: The problem of automatic storage reclamation for distributed implementations of applicative languages is explored. Highly parallel distributed systems have several unique characteristics that complicate the reclamation process; in this setting, the deficiencies of existing storage reclamation schemes are thus noted. A real-time, effectively distributed, garbage collector of the mark-sweep variety, called the marking-tree collector, is shown to accomplish reclamation in parallel with the main computation, with no centralized data or control other than a logical rendezvous between phases of the collector. In addition, it is capable of finding and subsequently deleting active processes which are determined to be no longer relevant to the computation.
105 citations
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IBM1
TL;DR: In this article, the replacement area is provided by a flexibly dynamically deallocated portion of the main memory so that it can be selected from any section of the original memory by inserting the appropriate page address in the replacement-page register.
Abstract: A single error correcting memory is constructed from partially good components on the design assumption that the components are all-good. Those small number of logical lines containing double-bit errors are replaced when detected with good lines selected from a replacement area of the memory. The replacement area is provided by a flexibly dynamically deallocated portion of the main memory so that it can be selected from any section of the original memory by inserting the appropriate page address in the replacement-page register. With such a memory architecture until the first double-bit error is detected (either in testing or actual use) all pages may be used for normal data storage. When such an error is detected some temporarily unused page in the memory is deal-located, that is rendered unavailable for normal storage, and dedicated to providing substitute lines. The same procedure is followed for subsequent faults. If the replacement area itself becomes defective, a different page may be chosen to provide substitute lines simply by providing a different address in the replacement page register.
84 citations
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IBM1
TL;DR: In this article, a memory system is provided with a simple flexible control arrangement for assigning locations in an alternate memory as replacements for previously identified defective fault areas in main memory, taking into consideration the defect status of other failure independent bit positions of a data word and the power of the ECC code used in connection with the memory system.
Abstract: A memory system is provided with a simple flexible control arrangement for assigning locations in an alternate memory as replacements for previously identified defective fault areas in main memory (30). The assignment of the replacement locations in the alternate memory is made on a selective basis taking into consideration the defect status of other failure independent bit positions of a data word and the power of the ECC code which is used in connection with the memory system. A relatively small writable index, which is addressed by a subset of the main memory address signals, provides a partial address and control fields to the alternate memory in accordance with control data transferred from the host system. Control data is developed by the host system each time it is powered on and is based on identifying each defective location in main memory through a diagnostic routine and analyzing the defect distribution in a way to provide control signals which minimize the number of replacements that are assigned and maximize the number of data words that can be transferred from the memory system to the host system before an uncorrectable error is encountered by the ECC system.
82 citations
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11 Nov 1982TL;DR: In this article, a modular working memory formed by a plurality of memory modules sends to a central processing unit information related to the capacities of the constituting modules (M1, M2, M3, M4) during the system initialization.
Abstract: A memory module selection and reconfiguration apparatus in a data processing system wherein a modular working memory formed by a plurality of memory modules sends to a central processing unit information related to the capacities of the constituting modules (M1, M2, M3, M4) during the system initialization. The central unit processes such information and provides memory, via a channel (30), with information representative of the capacity of the first modules (G1), of the sum of the capacities of the first and second module (G2), of the sum of the capacities of the first, second and third module (G3) and so on, up to the total capacity of the working memory. This information is stored into registers (31, 32), each one related to a possible module, of a module selection unit included inside the working memory. When the memory is addressed, the most significant address portion (BA 03-06) is compared simultaneously by several comparators (33, 34, 35, 36), one for each register, with the content of the several registers. The result of the comparison from the comparators are applied to a decoder (37) which generates signals selecting one among the several memory modules.
71 citations
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03 Mar 1982
TL;DR: In a hierarchical memory system, replacement of segments in a cache memory is governed by a least recently used algorithm, while trickling of segments from the cache memory to the bulk memory was governed by the age since first write.
Abstract: In a hierarchical memory system, replacement of segments in a cache memory is governed by a least recently used algorithm, while trickling of segments from the cache memory to the bulk memory is governed by the age since first write The host processor passes an AGEOLD parameter to the memory subsystem and this parameter regulates the trickling of segments Unless the memory system is idle (no I/O activity), no trickling takes place until the age of the oldest written-to segment is at least as great as AGEOLD A command is generated for each segment to be trickled and the priority of execution assigned to such commands is variable and determined by the relationship of AGEOLD to the oldest age since first write of any of the segments If the subsystem receives no command from the host processor for a predetermined interval, AGEOLD is ignored and any written-to segment becomes a candidate for trickling
68 citations
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26 Feb 1982TL;DR: In this article, the shadow copy of a data structure is periodically updated at a series of checkpoints, and updating without recopying is enabled by prelinking the list item in the read-only list to the beginning of a second read/write list, which is appended to the first list at the next checkpoint.
Abstract: Operation of a computer system after a main memory failure is enabled by storing a read-only access shadow copy of its data structures in another memory having an independent failure mode. The shadow copy is periodically updated at a series of checkpoints. Where the data structure is a linked list, updating without recopying is enabled by prelinking the list item in the read-only list to the beginning of a second read/write list, which is appended to the first list at the next checkpoint.
63 citations
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03 Mar 1982
TL;DR: In this paper, the write-back of data segments in the cache memory to the bulk memory for replacement purposes is accomplished in accordance with a least recently used algorithm while the writeback of written-to segments to the base memory without replacement is accomplished according to an age since first write algorithm.
Abstract: In a memory system having a cache memory and a bulk memory, write-back of data segments in the cache memory to the bulk memory for replacement purposes is accomplished in accordance with a least recently used algorithm while the write-back of written-to segments to the bulk memory without replacement is accomplished in accordance with an age since first write algorithm.
61 citations
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09 Jun 1982TL;DR: In this article, a memory management system is designed for use with a self-contained microprocessor to form a multi-user computer, which operates to establish user and kernel modes each having different operating permissions.
Abstract: A memory management system is structured for use with a self-contained microprocessor to form a multi-user computer. The system operates to establish user and kernel modes each having different operating permissions. When the system is operating in the user mode, certain of the fixed functions of the microprocessor, such as interrupt-off and halt, are blocked from enablement by any user. The system is designed having multiple memory maps, some accessible when in the user mode and all accessible from the kernel mode.
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30 Mar 1982
TL;DR: In this paper, a memory request arbitrator is provided for selecting one of a plurality of requesting devices, such as microprocessors, which may make a request to access a memory device common to the plurality of requestors.
Abstract: A memory request arbitrator is provided for selecting one of a plurality of requesting devices, such as microprocessors, which may make a request to access a memory device common to the plurality of requestors. Requests from the devices are applied in common as a portion of an address to a read only memory, a priority sequencer providing another portion of the address. The read only memory provides a selection signal to the selected requestor. The priority sequencer is periodically updated to thereby change the priority of requestors such that priority is given to each of the requestors over time. The priority sequencer may be temporarily disabled to thereby allow a requestor a "back-to-back" memory access for a multi-cycle memory instruction. Finally, the initial state of the request lines is checked upon system start up to determine whether any of the request lines are unused. Only those request lines associated with presently operating requestors are able to provide request signals to the read only memory.
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01 Mar 1982TL;DR: This paper describes how the memory management mechanisms of the Intel iAPX-432 are used to implement the visibility rules of Ada, and shows how Ada's view of sharing is the same as the 432, but differs totally from the sharing permitted by traditional systems.
Abstract: In this paper, we describe how the memory management mechanisms of the Intel iAPX-432 are used to implement the visibility rules of Ada. At any point in the execution of an Ada® program on the 432, the program has a protected address space that corresponds exactly to the program's accessibility at the corresponding point in the program's source. This close match of architecture and language did not occur because the 432 was designed to execute Ada—it was not. Rather, both Ada and the 432 are the result of very similar design goals.To illustrate this point, we compare, in their support for Ada, the memory management mechanisms of the 432 to those of traditional computers. The most notable differences occur in heap-space management and multitasking. With respect to the former, we describe a degree of hardware/software cooperation that is not typical of other systems. In the latter area, we show how Ada's view of sharing is the same as the 432, but differs totally from the sharing permitted by traditional systems. A description of these differences provide some insight into the problems of implementing an Ada compiler for a traditional architecture.
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20 Aug 1982
TL;DR: In this paper, the authors present a data access control system for a data base management system with a first memory and a sub-memory for storing data required to execute a program, including at least one data operation instruction.
Abstract: Data access in a data base management system is controlled. The method for controlling the data access in a computer having a first memory and a sub memory, both for storing data required to execute a program, including at least one data operation instruction comprises the steps of transferring data required by the data operation instruction from the sub memory to a location in the first memory, prior to execution of the data operation instruction, and informing the data operation instruction of the address of the location of the data required thereby, prior to execution of the data operation instruction. The apparatus for controlling data access comprises a sub memory for storing a data base and programs including at least one task unit having at least one data operation instruction, a first processor for executing each task unit stored in the sub memory, a first memory for storing programs and data executed by the first processor, a second processor connected to the sub memory, and a second memory for storing programs and data executed by the second processor, whereby the first processor executes the task unit read out from the sub memory, while the second processor reads out the data from the sub memory specified by the data operation instruction included in the task unit, based on the parameter supplied from the first processor and stores the data read out from the sub memory and corresponding addresses in the first memory.
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IBM1
TL;DR: In this article, a circuit for allocating main memory cycles between two data processors has means for making the allocation by either of two procedures, Code Idle and Code Release, where the control memory of a processor selects the process by two bits called code idle and code release.
Abstract: A circuit for allocating main memory cycles between two data processors has means for making the allocation by either of two procedures. In one procedure, control of memory is transferred only after a request for memory access has been made. In a second procedure, transfer of memory control to a requesting processor is automatically accompanied by a request to return control. The control memory of a processor selects the process by two bits called Code Idle and Code Release. Code Idle accompanies instructions that usually mean that the releasing processor will not need memory for several memory cycle times, and an explicit request for transfer is made when memory is actually needed. Code Release accompanies instructions that do not require memory access at the time but are typically followed by a memory request within a processor cycle time or a few processor cycle times. Memory control is returned without the delay that is associated with an explicit request.
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01 Apr 1982
TL;DR: A priority-based task management scheduling algorithm is then defined which uses the optimal schedule of the formal model as a parameter, and its performance is simulated.
Abstract: A multiprocessor architecture is proposed which is based on the Multics concept of having all on-line information processor-addressible. All memory management is done by an intelligent paged virtual memory system, and each processor deals only with those segments relevant to its single executing program. The processors are chosen to have different implementations of a single system-wide instruction set and the problem is to effectively schedule different categories of programs, called task groups, on the dissimilar processors.Average weighted instruction times for each task group on every processor are defined as task/processor suitability measures, and typical values are given for different groups of programs running on IBM 370 models. Through the use of linear programming techniques, an optimal schedule for any such multiprocessor is then defined for the static case where task group loads and task/processor suitability values are known in advance. A priority-based task management scheduling algorithm is then defined which uses the optimal schedule of the formal model as a parameter, and its performance is simulated.
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24 Feb 1982TL;DR: In this paper, a memory accessing method is described which is particularly useful with the Multibus where a dynamic memory is employed, and when the memory is accessed without a refresh collision, a ready signal is generated before the acknowledgement signal.
Abstract: A memory accessing method is described which is particularly useful with the Multibus where a dynamic memory is employed. When the memory is accessed without a refresh collision, a ready signal is generated before the acknowledgement signal. This saves considerable time since the time between the placement of the data on the bus and the CPU's sensing of the data is reduced.
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TL;DR: The design challenges in creating the NS 16000 microprocessor family were met only after thoroughly considering market requirements and LSI technology limitations, and the design allows for a smaller die size, leading to a reduction in chip cost.
Abstract: and slave processors, this group of microprocessors addresses a wide range of system applications. When LSI/MOS chips were first developed, it was possible for designers to place approximately 1000 active elements on a single chip. Now, ten years later, the number of active elements per chip has risen to over 100,000. As we enter the second decade of LSI/MOS technology, applications for its use are continually expanding as the computational power of newly developed 16-and 32-bit microprocessors approaches that of mainframe computers. In short, microprocessor designers have their work cut out for them. Currently, software development efforts are becoming responsible for ever larger shares of product development costs. To offset these costs, microcomputer designers are shifting toward high-level language programming. Increasingly , users expect microprocessors to provide a cost-effective solution for HLL support with minimal degradation in overall system performance; this sets tougher requirements for microprocessor designers. Sophisticated future systems will require a combination of capabilities. Anticipating these needs, National Semiconductor has developed the NS 16000 microprocessor family to incorporate various architectural features into a new generation of devices. Utilizing National Semiconductor's XMOS technology, the design of the NS16000 family is implemented with 3.5-micron gate technology. This allows for a smaller die size, leading to a reduction in chip cost. The design challenges in creating this new family were met only after thoroughly considering market requirements and LSI technology limitations. This article describes some of the capabilities provided by the NS16000 architecture.
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TL;DR: This paper shows that the working set parameter-real memory and real memory-fault rate anomalies mentioned by Franklin, Graham, and Gupta in [13] do occur in traces generated by real programs.
Abstract: This paper shows that the working set parameter-real memory and real memory-fault rate anomalies mentioned by Franklin, Graham, and Gupta in [13] do occur in traces generated by real programs. The results of the detailed investigation of this anomalous behavior in four Fortran programs are presented. In some cases a drop of a factor of two in the average real-time memory allotment is observed when the window size is increased. In some instances a bigger real-time memory allotment means an order of magnitude increase in page faults.
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22 Mar 1982
TL;DR: In this article, the main read only memory is replaced by a correction memory, which is incorporated in the computer when required, and the CPU is arranged to fetch and use instructions or data alternatively from the main memory or the correction memory.
Abstract: A computer having a main read only memory is so arranged that a portion of the information stored in the main read only memory can be changed, if desired, without changing the entire main memory. Information to be substituted for a portion of the main information contained in the main memory is stored in a correction memory, which is incorporated in the computer when required. The CPU is arranged to fetch and use instructions or data alternatively from the main memory or the correction memory in such a manner that a predetermined portion of the main information is replaced by the substitute information. In one embodiment, data is stored in the correction memory for designating which portion is to be replaced and the CPU selects either memory depending upon this data. In another embodiment, one or more comparators are used for comparing the value on an address bus with addresses for designating the start and the end of the portion to be replaced.
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01 Jan 1982
TL;DR: In a tightly coupled multimicrocomputer system suitable for process control applications, the microcomputers are grouped into a cluster and communicate using a high speed parallel common bus, which makes available a virtual machine where processes allocated on different processors are executed in parallel.
Abstract: In a tightly coupled multimicrocomputer system suitable for process control applications, the microcomputers are grouped into a cluster and communicate using a high speed parallel common bus. Hardware mechanisms are provided as supports for the implementation of synchronization primitives between processes allocated on different processors. The system fault-tolerance is achieved by memory management units, which relocate and protect programs and data against faults and programming mistakes. The distributed operating system kernel makes available a virtual machine where processes allocated on different processors are executed in parallel, and processes which reside on the same processor are executed in a multitasking environment. 13 references.
01 Jan 1982
TL;DR: In this paper, the authors present two models relevant to the achievement of this aim: the first model is framed in terms of a memory management and addressing scheme which overcomes the major memory management problems associated with small and large segments, and also address translation problems which arise in systems which make abundant use of segments.
Abstract: SUMMARYThe research described in this thesis was undertaken with the aim of providing a suitable computer architecture for supporting the development and execution of large software systems decomposed into modules according to the information hiding principle. In the course of this work, the author developed two models relevant to the achievement of this aim. The first model is framed in terms of a memory management and addressing scheme which bases protection on capabilities and overcomes the major memory management and address translation problems found in other capability-based architectures. The second model modifying an existing this architecture. It arose from the author's practical work in computer (a Hewlett Packard HP2100A) to support proposes a general technique for upgrading relatively primitive computers to support more advanced features, in terms of addressing modes, additional registers, new instructions and virtual memory. Chapter 1 provides background information which led the author to undertake this research, and explains the structure of the thesis. Chapter 2 surveys the conventional memory management systems, and describes a number of the more common problems associated with them. Chapter 3 describes the hardware used by most memory management systems. Chapter 4 surveys current capability based addressing schemes and highlights their problems. Chapter 5 describes the new architectural model and shows how it solves the problems raised in earlier chapters. Chapter 6 addresses the problem of how to implement the new model both cheaply and quickly. In doing so, it develops a general technique which can be used to implement new computer architectures. Chapter 7 describes a practical implementation of the addressing scheme described in chapter 5 using the technique defined in Chapter 6. The concluding chapter examines the extent to which the two models proposed in this thesis have been successful and practical. The two major contributions of this research work are the new addressing model proposed in Chapter 5, and the architectural enhancement model proposed in Chapter 6 . The new addressing model avoids the two major problems of current capability based computers, namely memory management problems associated with small and large segments, and also address translation problems which arise in systems which make abundant use of segments. The model is shown to be more efficient than the addressing schemes used in other capability systems. Unlike other capability based and conventional computers, it is flexible enough to efficiently implement many different capability addressing structures. Consequently, the software ideas can change and evolve, without affecting the hardware. The new enhancement technique allows many different architectural enhancements to be implemented and tested as an extension of an existing computer system, and thus allows a full scale evaluation of the ideas to be made. Because the technique allows complex structures to be constructed quickly, accurately and cheaply, it avoids the problems found in many theses which propose new architectures without coming to terms with their practical implications. In addition to these contributions, during the course of the implementation work, a new address translation unit was devised which, whilst not significantly different in concept, is significantly different in implementation from many other units.
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12 Jul 1982TL;DR: In this paper, a control-line translation unit is coupled within a control line which connects a memory control circuit with the memory, which is used for read, write and word-erase commands in addition to one further command, wherein the entire memory is cleared.
Abstract: An electronically operated postage meter includes a non-volatile memory for the permanent storage of security and financial data utilized in the operation of the meter. In the operation of the memory, a standardized two-bit control signal is employed for providing read, write and word-erase commands in addition to one further command, namely, a block-erase command, wherein the entire memory is cleared. To avoid unintentional erasure of the entirety of the stored data, as might occur in the event of a fault in a control circuit or computation circuit coupled to the memory, a control-line translation unit is coupled within a control line which connects a memory control circuit with the memory. The control-line translation unit comprises a logic gate and a feed forward path, the gate operation being transparent to three out of the total of four control signals. Thereby, only the block-erase signal is translated, or converted, to a harmless one of the other control signals, more particularly, to the read signal. Thereby, a block-erase signal does not occur inadvertently due to a failure in a control unit external to the non-volatile memory.
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30 Aug 1982TL;DR: This paper describes a set of measurements of the memory reference patterns of some programs, and an attempt is made to classify the programs based on their referencing behavior.
Abstract: This paper describes a set of measurements of the memory reference patterns of some programs. The technique used to obtain these measurements is unusually efficient. The data is presented in graphical form to allow the reader to "see" how the program uses memory. Constant use of a page and sequential access of memory are easily observed. An attempt is made to classify the programs based on their referencing behavior. From this analysis it is hoped that the reader will gain some insights as to the effectiveness of various memory management policies.
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21 Jul 1982
TL;DR: A memory management system for use with a memory device which is common (or shared) with a plurality of user elements utilizing a memory address counter, scratch pad address memory, external memory address inputs and an address multiplexer is described in this article.
Abstract: A unique memory management system for use with a memory device which is common (or shared) with a plurality of user elements utilizing a memory address counter, scratch pad address memory, external memory address inputs and an address multiplexer.
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TL;DR: This work considers the problem of designing an interprocess communication system usable as a base for writing real-time operating and applications systems in a distributed environment where processes may be connected by anything from shared virtual memory to radios, and introduces an inter process communication system based on two mechanisms: queueable objects and connectable objects.
Abstract: We consider the problem of designing an interprocess communication system usable as a base for writing real-time operating and applications systems in a distributed environment where processes may be connected by anything from shared virtual memory to radios. By requiring an interface that minimizes the code an application program must devote to communications, a facility of substantially higher level than basic message passing becomes necessary. This is largely a consequence of four major performance problems with interprocess communication in a distributed environment: system reliability, server congestion, throughput, and response time. We summarize these problems, and introduce an interprocess communication system based on two mechanisms: queueable objects and connectable objects. We briefly review our experience with a limited implementation of queueable objects.
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01 Apr 1982TL;DR: A data flow architecture with a paged memory system to hold both data flow programs and data structures and the token labeling mechanism is coupled with the memory management system in order to provide for each token a unique memory location.
Abstract: During the last ten years, data flow has become an exciting research area and several architectures have been proposed and built. They differ mostly in the way they handle data structures and how they provide mechanisms for token labeling or colouring in order to make data flow graphs reentrant. The paper presents a data flow architecture with a paged memory system to hold both data flow programs and data structures. The token labeling mechanism is coupled with the memory management system in order to provide for each token a unique memory location. The instruction format allows instructions with multiple operands and multiple destinations for each result. Data structures are held in memory while pointers to the structures are circulating as tokens. The proposed architecture is able to execute data flow programs at the level of single instructions or at a higher level.