Showing papers on "Memory management published in 1989"

Memory coherence in shared virtual memory systems

Abstract: The memory coherence problem in designing and implementing a shared virtual memory on loosely coupled multiprocessors is studied in depth. Two classes of algorithms, centralized and distributed, for solving the problem are presented. A prototype shared virtual memory on an Apollo ring based on these algorithms has been implemented. Both theoretical and practical results show that the memory coherence problem can indeed be solved efficiently on a loosely coupled multiprocessor.

Backup control method and system in data processing system using identifiers for controlling block data transfer

Abstract: In a data processing system having a first external memory, a second external memory, and a control memory for storing information on data renewals in the first external memory, a system and a method provide for back-up operations in parallel with ordinary data processing, including dump processing in which renewed data parts in the first external memory are copied as backup data into the second external memory with reference to the contents of the control memory. The method provides the step of storing into the control memory first identifier information for identifying areas of the first external memory where data items were renewed; the step of storing into the control memory second identifier information for identifying areas of the first external memory where data items were renewed during the dump processing; and the step of erasing at completion of the dump processing the first identifier information items except those which identify the same areas as identified by the second identifier information items. Thus, ordinary job processing and the renewals of the data items of the first external memory can be performed even in the course of the data dumping processing.

Process decomposition through locality of reference

Abstract: In the context of sequential computers, it is common practice to exploit temporal locality of reference through devices such as caches and virtual memory. In the context of multiprocessors, we believe that it is equally important to exploit spatial locality of reference. We are developing a system which, given a sequential program and its domain decomposition, performs process decomposition so as to enhance spatial locality of reference. We describe an application of this method - generating code from shared-memory programs for the (distributed memory) Intel iPSC/2.

Mirage: a coherent distributed shared memory design

Abstract: Shared memory is an effective and efficient paradigm for interprocess communication. We are concerned with software that makes use of shared memory in a single site system and its extension to a multimachine environment. Here we describe the design of a distributed shared memory (DSM) system called Mirage developed at UCLA. Mirage provides a form of network transparency to make network boundaries invisible for shared memory and is upward compatible with an existing interface to shared memory. We present the rationale behind our design decisions and important details of the implementation. Mirage's basic performance is examined by component timings, a worst case application, and a “representative” application. In some instances of page contention, the tuning parameter in our design improves application throughput. In other cases, thrashing is reduced and overall system performance improved using our tuning parameter.

The implementation of a coherent memory abstraction on a NUMA multiprocessor: experiences with platinum

Abstract: PLATINUM is an operating system kernel with a novel memory management system for Non-Uniform Memory Access (NUMA) multiprocessor architectures. This memory management system implements a coherent memory abstraction. Coherent memory is uniformly accessible from all processors in the system. When used by applications coded with appropriate programming styles it appears to be nearly as fast as local physical memory and it reduces memory contention. Coherent memory makes programming NUMA multiprocessors easier for the user while attaining a level of performance comparable with hand-tuned programs.This paper describes the design and implementation of the PLATINUM memory management system, emphasizing the coherent memory. We measure the cost of basic operations implementing the coherent memory. We also measure the performance of a set of application programs running on PLATINUM. Finally, we comment on the interaction between architecture and the coherent memory system.PLATINUM currently runs on the BBN Butterfly Plus Multiprocessor.

On determining lifetime and aliasing of dynamically allocated data in higher-order functional specifications

Abstract: We present a static analysis method for determining aliasing and lifetime of dynamically allocated data in lexically scoped, higher-order, strict and polymorphic languages with first class continuations. The goal is validate program transformations that introduce imperative constructs such as destructive updatings, stack allocations and explicit deallocations in order to reduce the run-time memory management overhead. Our method is based on an operational model of higher order functional programs from which we construct statically computable abstractions using the abstract interpretation framework. Our method provides a solution to a problem left open [Hudak 86]: determining isolation of data in the case of higher order languages with structured data.

Memory structure and method for shuffling a stack of data utilizing buffer memory locations

Abstract: A memory structure which can operate as a stack or list, the structure comprising a plurality of contiguous memory locations sub-divided into contiguous sub-structures, each of the sub-structures having at least one buffer memory location associated with it, whereby stack or list shuffle operations can be performed in parallel on the sub-structures. The memory structure can be utilized in a content addressable memory and records can be maintained in sorted order by key in the memory structure. The content addressable memory can be implemented using currently available random access memory (RAM) structures and the content addressable memory can be implemented in very large scale integration (VLSI).

An efficient reference counting solution to the distributed garbage collection problem

Abstract: A good programming language permits the programmer to concentrate on his application rather than on low-level implementation details. In particular, he does not have to concern himself with storage allocation because memory management is dealt with efficiently by the implementation of the language. To reclaim disused storage for reuse the implementation incorporates a garbage collection algorithm. When the language is implemented on a distributed multiprocessor architecture, this algorithm ideally collects garbage as soon as it is created and has minimal overheads in terms of space requirements and interprocess communications. We describe here an elegant algorithm with these properties which makes use of reference counting.

The Oberon system

Abstract: In this paper we describe an operating system for a workstation designed and implemented by the authors within two and a half years. It includes memory management and module loader, a file system, a viewer system, editors for text and graphics, a compiler, a server interface and various tools. The primary motivation was to demonstrate the feasibility of a small, yet highly flexible and powerful, system, a system that is a (decimal) order of magnitude smaller than commonly used operating systems. This is possible due to regularity of concepts and concentration on the essential. The benefits are not only fewer resources needed, but elegance and generality of concepts resulting in transparency and convenience of use and increased reliability. A corner-stone of this approach is genuine extensibility, which is achieved by a new language, in particular by a facility called type extension. It allows for the integration of variables (objects) of a new, extended type in structures of elements of an existing base type.

Generic virtual memory management for operating system kernels

Abstract: We discuss the rationale and design of a Generic Memory management Interface, for a family of scalable operating systems. It consists of a general interface for managing virtual memory, independently of the underlying hardware architecture (e.g. paged versus segmented memory), and independently of the operating system kernel in which it is to be integrated. In particular, this interface provides abstractions for support of a single, consistent cache for both mapped objects and explicit I/O, and control of data caching in real memory. Data management policies are delegated to external managers.A portable implementation of the Generic Memory management Interface for paged architectures, the Paged Virtual Memory manager, is detailed. The PVM uses the novel history object technique for efficient deferred copying. The GMI is used by the Chorus Nucleus, in particular to support a distributed version of Unix. Performance measurements compare favorably with other systems.

Introducing the Intel i860 64-bit microprocessor

Abstract: The authors describe the single-chip i860 CPU, a 64-bit, RISC (reduced-instruction-set-computer)-based microprocessor that executes parallel instructions using mainframe and supercomputer architectural concepts. They designed the 1,000,000-transistor, 10-mm*15-mm processor for balanced integer, floating-point, and graphics performance. They discuss the RISC core, memory management, floating-point unit, graphics, bus interface, software support, and interfacing to a DRAM system. >

Shared memory multiprocessor with data hiding and post-store

Abstract: A digital data processing system includes a plurality of central processor units which share and access a common memory through a memory management element. The memory management element permits, inter alia, data in the common memory to be accessed in at least two modes. In the first mode, all central processing units requesting access to a given datum residing in memory are signalled of the datum's existence. In the second mode, only selected central processing units requesting access to a resident datum are notified that it exists, while others requesting access to the datum are signalled that it does not exist. The common memory can include a plurality of independent memory elements, each coupled to and associated with, a respective one of the central processing units. A central processing unit can include a post-store element for effecting the transfer of copies of data stored in its associated memory element to a memory element associated with another central processing unit.

Models of working memory

Abstract: Publisher Summary This chapter describes the models of working memory. Working memory refers to a functional part of human memory that accomplishes the temporary holding and manipulation of information during the performance of a range of cognitive tasks such as comprehension, learning, and reasoning. At least three different functions performed by working memory, as expressed by models of cognitive processing, can be described in computational terms. Working memory functions as a place to hold operands or things to be operated on by the operations of cognitive processing, a cache to hold in a rapidly accessible state recently input or used information, and a buffer between processes that happen at incommensurate rates. In addition to its functions, working memory has also been characterized from two other points of view: (1) time and (2) structure. It is also distinguished from very short-term memory, lasting for only a fraction of a second. While a number of partial models of working memory exist, they do not yet embrace all the phenomena related to it in a computational framework.

Data protection for computer systems

Abstract: A computer system uses security labels for evey word in memory. Each access to a memory location requires that the security level of the memory location be compared to that of a process which is making the access. If the security level of the process does not dominate that of the memory location, access is denied. Each time a memory location is modified, it is assigned a security level consistent with the levels of all of the data which was used to modify the memory location.

Data flow machine for data driven computing

Abstract: A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output adress; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a ''fire'' signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.

Exporting a user interface to memory management from a communication-oriented operating system

Abstract: One of the most important resources that an operating system manages is main memory Systems often provide virtual memory, using this main memory to cache the contents of a larger virtual storage Unfortunately, existing systems hide the algorithms for controlling the contents of the main memory cache and for managing the external storage used to represent that virtual memory within the operating system kernel, making them unavailable to important systems applications My thesis is that it is desirable and practical to provide an external memory management interface that allows user-level programs to define and manage the contents of memory objects that may be mapped into virtual address spaces Exporting this interface simplifies the construction of complex virtual memory applications, allowing them to manage the sharing, consistency, and permanent storage of their data without being embedded in the operating system kernel These systems applications can also take advantage of the performance benefits of using main memory as a cache of the contents of their data objects This dissertation describes the Mach external memory management interface and implementation in detail The interface design is based on communication: memory objects are communication channels, on which the operating system sends messages to read or write the contents of pages of virtual memory The implementation addresses the modularity and security issues that arise from exporting this interface to user-level programs Several systems applications that have been constructed using the Mach interface are described, including a user-level file system, a transaction-based data management system, and a network shared virtual memory service An evaluation of the Mach system analyzes the cost of using this interface, and shows how it makes a fast path to the main memory cache available to systems applications Experiments also show that the overall performance of the Mach system does not suffer appreciably under normal load, and that this system still outperforms commercially available operating systems under identical benchmarks I conclude that an external memory management interface is a useful, affordable component that should be provided by future operating systems

A methodology for parallelizing programs for multicomputers and complex memory multiprocessors

Abstract: The availability of large distributed memory multiprocessors and parallel computers with complex memory hierarchies have left the programmer with the difficult task of planning the detailed parallel execution of a program; for example, in the case of distributed memory machines, the programmer is forced to manually distribute code and data in addition to managing communication among tasks explicitly Current work in compiler support for this task has focused on automating task partitioning, assuming a fixed data partition or a programmer-specified (in the form of annotations) data partition This paper argues that one of the reasons for inefficient parallel execution is the lack of synergism between task partitioning and data partitioning and allocation; hence data and task allocation should both be influenced by the inherent dependence structure of the computation (which is the source of synergism) We present a methodology based on a unified approach to task and data partitioning; we show how to derive data and task partitions for computations expressed as nested loops that exhibit regular dependencies and how to map these onto distributed memory multiprocessors Based on the mapping, we show how to derive code for the nodes of a distributed memory machine with appropriate message transmission constructs We also discuss related communication optimizations

Introducing Memory Into The Switch Elements Of Multiprocessor Interconnection Networks

Abstract: As VLSI technology continues to improve, circuit area is gradually being replaced by pin restrictions as the limiting factor in design. Thus, it is reasonable to anticipate that on-chip memory will become increasingly inexpensive since it is a simple, regular structure than can easily take advantage of higher densities. In this paper we examine one way in which this trend can be exploited to improve the performance of multistage interconnection networks (MINs). In particular, we consider the performance benefits of placing significant memory in each MIN switch. This memory is used in two ways: to store (the unique copies of) data items and to maintain directories. The data storage function allows data to be placed nearer processors that reference it relatively frequently, at the cost of increased distance to other processors. The directory function allows data items to migrate in reaction to changes in program locality. We call our MIN architecture the Memory Hierarchy Network (MHN), In a preliminary investigation of the merits of this design [8] we examined the performance of MHNs under the simplifying assumption that an unlimited amount of memory was available in each switch. We found that despite the longer switch processing times of the MHN, system performance is improved over simpler, conventional schemes based on caching. In this paper we refine the earlier model to account for practical storage limitations. We study ways to reduce the amount of directory storage required by keeping only partial information regarding the current location of data items. The price paid for this reduction in memory requirement is more complicated (and in some circumstances slower) protocols. We obtain comparative performance estimates in an environment containing a single global memory module and a tree-structured MIN. Our results indicate that the MHN organization can have substantial perfor- mance benefits and so should be of increasing interest as the enabling technology becomes available.

System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer

Abstract: A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access exceptions at a pipeline stage, corresponding fault information is generated and transferred along the pipeline. The fault information is acted upon only when the instruction reaches the execution stage of the pipeline. Each stage of the instruction pipeline is ported into the front end of a memory unit adapted to perform the virtual-to-physical address translation; each port being provided with storage for virtual addresses accompanying an instruction as well as storage for corresponding fault information. When a memory access exception is encountered at the front end of the memory unit, the fault information generated therefrom is loaded into the storage and the port is prevented from accepting further references.

Multi-level shared caching techniques for scalability in VMP-M/C

Abstract: The problem of building a scalable shared memory multiprocessor can be reduced to that of building a scalable memory hierarchy, assuming interprocessor communication is handled by the memory system. In this paper, we describe the VMP-MC design, a distributed parallel multi-computer based on the VMP multiprocessor design, that is intended to provide a set of building blocks for configuring machines from one to several thousand processors. VMP-MC uses a memory hierarchy based on shared caches, ranging from on- chip caches to board-level caches connected by busses to, at the bottom, a high-speed fiber optic ring. In addition to describing the building block components of this architecture, we identify the key performance issues associated with the design and provide performance evaluation of these issues using trace-drive simulation and measurements from the VMP. This work was sponsored in part by the Defense Advanced Re- search Projects Agency under Contract N00014-88-K-0619.

Incremental-scanning compiler for source-code development system

Abstract: A computer-aided software development system includes programs to implement edit, compile, link and run sequences, all from memory, at very high speed. The compiler operates on an incremental basis, line-by-line, so if only one line is changed in an edit session, then only that line need be recompiled if no other code is affected. Scanning is done incrementally, generating a sequential token list which is saved in memory to be used again where no changes are made; increments of the sequential token list are reused when no changes have been made in the increments and related statements. All of the linking tables are also saved in memory so there is no need to generate link tables for increments of code where no changes in links are needed. The parser is able to skip lines or blocks of lines of source code which haven't been changed. All of the source code text modules, the sequential token lists, symbol tables, code tables and related data saved from one compile to another are maintained in virtual memory rather than in files so that speed of operation is enhanced. Also, the object code created is maintained in memory rather than in a file, and executed from this memory image, to reduce delays. A virtual memory management arrangement for the system assures that all of the needed data modules and code is present in real memory by page swapping, but with a minimum of page faults, again to enhance operating speed.

IC memory card incorporating software copy protection

Abstract: A storage portion for a ROM card for storing a distribution software comprises a software storage memory (ROM region) and a temporary memory (RAM region). A memory address trap circuit, when a predetermined specific address is designated, selects a temporary memory portion as an alternative to the software storage memory, while it selects a software storage memory when an address other than the specific address is designated. A software protection program stored, together with the distribution software, or as a sub-routine of the distribution software in the software storage memory, is executed by a program executing portion of a peripheral device to which the card is connected. The software protection program checks the medium in which this software protection program itself is stored to determine whether this medium can be data-accessed as a RAM region when the above-described specific address is designated, while, when an address other than the specific address is designated, it checks whether the medium can be data-accessed as the ROM region. If a desired result cannot be obtained, software protection program determines that the distribution software including the software protection program is unlawfully copied software and prevents its execution.

Re-execution of edit-compile-run cycles for changed lines of source code, with storage of associated data in buffers

Abstract: A computer-aided software development system includes programs to implement edit, compile, link and run sequences, all from memory, at very high speed. The compiler operates on an incremental basis, line-byline, so if only one line is changed in an edit session, then only that line need be recompiled if no other code is affected. Dependency analysis is performed incrementally, without requiring the user to enter dependencies. Scanning is also done incrementally, and the resulting token list saved in memory to be used again where no changes are made. All of the linking tables are saved in memory so there is no need to generate link tables for increments of code where no changes in links are needed. The parser is able to skip lines or blocks of lines of source code which haven't been changed. All of the source code text modules, the token lists, symbol tables, code tables and related data saved from one compile to another are maintained in virtual memory rather than in files so that speed of operation is enhanced. Also, the object code created is maintained in memory rather than in a file, and executed from this memory image, to reduce delays. A virtual memory management arrangement for the system assures that all of the needed data modules and code is present in real memory by paging swapping, but with a minimum of page faults, again to enhance operating speed.

Fault simulation in a pipelined multiprocessor system

Abstract: The authors describe fault simulation algorithms for the MARS hardware accelerator. Two algorithms are considered. The first, serial fault simulation, has a performance that is linear in the number of faults. Its performance is easily predictable and it takes full advantage of the true-value simulation speed of the accelerator; it is also easy to implement. The second algorithm, concurrent fault simulation, is found to have a performance that is nonlinear in the number of faults. It also requires either a large amount of memory or a dynamic memory management, both of which are difficult to implement in an accelerator. Yet the concurrent method has the advantage of more efficient event processing and less duplicated effort. Combining the features of both algorithms, a fixed-memory, multipass, concurrent algorithm is developed for MARS. >

System for periodically reallocating page frames in memory based upon non-usage within a time period or after being allocated

Abstract: A method for memory management and block paging in a control program that controls the execution of tasks on behalf of a plurality of system computing entities, which selects, transfers blocks of data, such as pages, between storage and memory to maintain in memory only those blocks of data necessary for current system processing requirements. Pages in memory are first identified as not referenced within a preceding time period, for example, since the last examination by a core table scan mechanism, on a system wide basis. Pages so identified are then grouped into blocks of pages used by a computing entity and then transferred to storage for later retrieval as a set when any one of the pages in the set is required by the system. Pages not referenced while resident are made available for paging to memory individually. Block paging achieves a significant reduction in the system overhead associated with memory management, as compared with prior art paging mechanisms. Demand driven systemwide or global least recently used memory management achieves more efficient memory utilization.

An analysis of distributed shared memory algorithms

Abstract: Results obtained in a study of algorithms to implement a distributed-shared memory in a distributed (loosely coupled) environment are described. Distributed-shared memory is the implementation of shared memory across multiple nodes in a distributed system. This is accomplished using only the private memories of the nodes by controlling access to the pages of the shared memory and transferring data to and from the private memories when necessary. Alternative algorithms are analyzed to implement distributed-shared memory. The algorithms are analyzed and compared over a wide range of conditions. Application characteristics are identified which can be exploited by the algorithms. The conditions under which the algorithms analyzed perform better or worse than the other alternatives are shown. Results are obtained via simulation using a synthetic reference generator. >

Virtual memory paging apparatus with variable size in-page clusters

Abstract: A virtual memory management system and method in which the mechanism for swapping in pages of memory in secondary storage replaces the overhead of retrieving pages from secondary storage by swapping logically contiguous clusters of pages each time that a page from secondary memory is needed. To improve the efficiency of in-page clustering, the size of the clusters which are read in are heuristically adjusted. Clustered pages are not entered into the working set until they are accessed by the process. Instead, the cluster of pages read in from secondary memory are initially entered a "standby list" of pages which are more eligible for reallocation than pages in the working set of the process. If the process does not access a particular cluster page within a relatively short period of time of its entry onto the standby list it is reallocated by the system's memory manager. In this way, in-page cluster pages do not replace potentially more valuable pages in the working set until those pages are actually requested by the process. Depending on whether the cluster pages are used before being reallocated, cluster sizes in corresponding portions of the virtual memory space are increased or decreased.

Automatic data channels for a computer system

Abstract: A data communications system for a computer for transferring data between the memory of the computer and one or more peripheral devices without requiring an interrupt context switch. The data communications system includes a number of specialized registers in the central processing unit of a computer, a computer memory, a data storage location associated with one or more peripheral devices, and a bus connecting the data storage location to the memory. The specialized registers in the central processing unit are dedicated exclusively to processing data transfers between the memory and the data storage location associated with the peripheral devices. Data transfers between the computer memory and the data storage location associated with the peripheral devices are made under the control of the central processing unit with the use of the special registers without the execution of an interrupt context switch.

Join strategies on KD-tree indexed relations

Abstract: Join algorithms on KD-tree indexed relations are proposed. The join algorithms are based on a concept called wave. The wave is a set of pages that is the object of joining and that propagates over the relation space in the direction of the join attribute axis. Four basic join algorithms that determine the wave from one of the relations and one algorithm that determines the wave from both relations are proposed. The algorithms are described and extensively analyzed with analytical formulas and simulation results. Then a garbage collection mechanism is introduced that discards the unnecessary data loaded in the main memory and extends the previous basic algorithms with an efficient memory management. It is shown that the proposed algorithms perform the join of very large relations with one scan. >

System for managing interprocessor common memory

Abstract: A system for managing an interprocessor common memory in a multiprocessor system includes a memory block pool and a management table. The memory block pool is obtained by chaining N memory blocks of segmented memory blocks in the common memory by using two Queue Control Blocks ("QCBs") respectively assigned to the processors in opposite directions. The management table is constituted by a common memory block total count N required to manage the memory block pool, a memory block count b X (modN) (where X is 1 or 2) fetched by each of the processors, and a memory block count c X (modN) (where X is 1 or 2) which can be fetched at once. Each processor has a semaphore function for realizing means for asynchronously fetching e Y memory blocks from a start of a QCB Y when it is determined by using data of the management table that a condition that at least one memory block is always present in the memory block pool is satisfied, and means for asynchronously returning memory blocks to the start of the QCB Y .