Showing papers on "Memory management published in 1990"

Memory consistency and event ordering in scalable shared-memory multiprocessors

Abstract: Scalable shared-memory multiprocessors distribute memory among the processors and use scalable interconnection networks to provide high bandwidth and low latency communication. In addition, memory accesses are cached, buffered, and pipelined to bridge the gap between the slow shared memory and the fast processors. Unless carefully controlled, such architectural optimizations can cause memory accesses to be executed in an order different from what the programmer expects. The set of allowable memory access orderings forms the memory consistency model or event ordering model for an architecture.This paper introduces a new model of memory consistency, called release consistency, that allows for more buffering and pipelining than previously proposed models. A framework for classifying shared accesses and reasoning about event ordering is developed. The release consistency model is shown to be equivalent to the sequential consistency model for parallel programs with sufficient synchronization. Possible performance gains from the less strict constraints of the release consistency model are explored. Finally, practical implementation issues are discussed, concentrating on issues relevant to scalable architectures.

Weak ordering-a new definition

Abstract: A memory model for a shared memory, multiprocessor commonly and often implicitly assumed by programmers is that of sequential consistency. This model guarantees that all memory accesses will appear to execute atomically and in program order. An alternative model, weak ordering, offers greater performance potential. Weak ordering was first defined by Dubois, Scheurich and Briggs in terms of a set of rules for hardware that have to be made visible to software.The central hypothesis of this work is that programmers prefer to reason about sequentially consistent memory, rather than having to think about weaker memory, or even write buffers. Following this hypothesis, we re-define weak ordering as a contract between software and hardware. By this contract, software agrees to some formally specified constraints, and hardware agrees to appear sequentially consistent to at least the software that obeys those constraints. We illustrate the power of the new definition with a set of software constraints that forbid data races and an implementation for cache-coherent systems that is not allowed by the old definition.

Munin: distributed shared memory based on type-specific memory coherence

Abstract: We are developing Munin, a system that allows programs written for shared memory multiprocessors to be executed efficiently on distributed memory machines. Munin attempts to overcome the architectural limitations of shared memory machines, while maintaining their advantages in terms of ease of programming. Our system is unique in its use of loosely coherent memory, based on the partial order specified by a shared memory parallel program, and in its use of type-specific memory coherence. Instead of a single memory coherence mechanism for all shared data objects, Munin employs several different mechanisms, each appropriate for a different class of shared data object. These type-specific mechanisms are part of a runtime system that accepts hints from the user or the compiler to determine the coherence mechanism to be used for each object. This paper focuses on the design and use of Munin's memory coherence mechanisms, and compares our approach to previous work in this area.

Algorithms implementing distributed shared memory

Abstract: Four basic algorithms for implementing distributed shared memory are compared. Conceptually, these algorithms extend local virtual address spaces to span multiple hosts connected by a local area network, and some of them can easily be integrated with the hosts' virtual memory systems. The merits of distributed shared memory and the assumptions made with respect to the environment in which the shared memory algorithms are executed are described. The algorithms are then described, and a comparative analysis of their performance in relation to application-level access behavior is presented. It is shown that the correct choice of algorithm is determined largely by the memory access behavior of the applications. Two particularly interesting extensions of the basic algorithms are described, and some limitations of distributed shared memory are noted. >

A methodology for implementing highly concurrent data structures

Abstract: A concurrent object is a data structure shared by concurrent processes. Conventional techniques for implementing concurrent objects typically rely on critical sections: ensuring that only one process at a time can operate on the object. Nevertheless, critical sections are poorly suited for asynchronous systems: if one process is halted or delayed in a critical section, other, non-faulty processes will be unable to progress. By contrast, a concurrent object implementation is non-blocking if it always guarantees that some process will complete an operation in a finite number of steps, and it is wait-free if it guarantees that each process will complete an operation in a finite number of steps. This paper proposes a new methodology for constructing non-blocking and wait-free implementations of concurrent objects. The object's representation and operations are written as stylized sequential programs, with no explicit synchronization. Each sequential operation is automatically transformed into a non-blocking or wait-free operation using novel synchronization and memory management algorithms. These algorithms are presented for a multiple instruction/multiple data (MIMD) architecture in which n processes communicate by applying read, write, and compare&swap operations to a shared memory.

Slow memory: weakening consistency to enhance concurrency in distributed shared memories

Abstract: The use of weakly consistent memories in distributed shared memory systems to combat unacceptable network delay and to allow such systems to scale is proposed. Proposed memory correctness conditions are surveyed, and how they are related by a weakness hierarchy is demonstrated. Multiversion and messaging interpretations of memory are introduced as means of systematically exploring the space of possible memories. Slow memory is presented as a memory that allows the effects of writes to propagate slowly through the system, eliminating the need for costly consistency maintenance protocols that limit concurrency. Slow memory processes a valuable locality property and supports a reduction from traditional atomic memory. Thus slow memory is as expressive as atomic memory. This expressiveness is demonstrated by two exclusion algorithms and a solution to M.J. Fischer and A. Michael's (1982) dictionary problem on slow memory. >

Supporting shared data structures on distributed memory architectures

Abstract: Programming nonshared memory systems is more difficult than programming shared memory systems, since there is no support for shared data structures. Current programming languages for distributed memory architectures force the user to decompose all data structures into separate pieces, with each piece “owned” by one of the processors in the machine, and with all communication explicitly specified by low-level message-passing primitives. This paper presents a new programming environment for distributed memory architectures, providing a global name space and allowing direct access to remote parts of data values. We describe the analysis and program transformations required to implement this environment, and present the efficiency of the resulting code on the NCUBE/7 and IPSC/2 hypercubes.

Adaptive software cache management for distributed shared memory architectures

Abstract: An adaptive cache coherence mechanism exploits semantic information about the expected or observed access behavior of particular data objects. We contend that, in distributed shared memory systems, adaptive cache coherence mechanisms will outperform static cache coherence mechanisms. We have examined the sharing and synchronization behavior of a variety of shared memory parallel programs. We have found that the access patterns of a large percentage of shared data objects fall in a small number of categories for which efficient software coherence mechanisms exist. In addition, we have performed a simulation study that provides two examples of how an adaptive caching mechanism can take advantage of semantic information.

Distributed hierarchical control for parallel processing

Abstract: A description is given of a novel design, using a hierarchy of controllers, that effectively controls a multiuser, multiprogrammed parallel system. Such a structure allows dynamic repartitioning according to changing job requirements. The design goals are examined, and the principles of distributed hierarchical control are presented. Control over processors is discussed. Mapping and load balancing with distributed hierarchical control are considered. Support for gang scheduling as well as availability and fault tolerance is addressed. The use of distributed hierarchical control in memory management and I/O is discussed. >

Generalized trace back techniques for survivor memory management in the Viterbi algorithm

Abstract: A general framework for designing survivor memory based on the traceback technique with any number of traceback pointers is presented. It is shown that the memory size is reduced by using more traceback pointers and that a uniform speed realization can be achieved with more than one trace back pointer. Two implementations of the K-pointer trace-back techniques based on standard RAMs and custom-shift registers are presented. >

An empirical evaluation of two memory-efficient directory methods

Abstract: This paper presents an empirical evaluation of two memory-efficient directory methods for maintaining coherent caches in large shared memory multiprocessors. Both directory methods are modifications of a scheme proposed by Censier and Feautrier [5] that does not rely on a specific interconnection network and can be readily distributed across interleaved main memory. The schemes considered here overcome the large amount of memory required for tags in the original scheme in two different ways. In the first scheme each main memory block is sectored into sub-blocks for which the large tag overhead is shared. In the second scheme a limited number of large tags are stored in an associative cache and shared among a much larger number of main memory blocks. Simulations show that in terms of access time and network traffic both directory methods provide significant performance improvements over a memory system in which shared-writeable data is not cached. The large block sizes required for the sectored scheme, however, promotes sufficient false sharing that its performance is markedly worse than using a tag cache.

Compiler-directed data prefetching in multiprocessors with memory hierarchies

Abstract: Memory hierarchies are used by multiprocessor systems to reduce large memory access times. It is necessary to automatically manage such a hierarchy, to obtain effective memory utilization. In this paper, we discuss the various issues involved in obtaining an optimal memory management strategy for a memory hierarchy. We present an algorithm for finding the earliest point in a program that a block of data can be prefetched. This determination is based on the control and data dependencies in the program. Such a method is an integral part of more general memory management algorithms. We demonstrate our method's potential by using static analysis to estimate the performance improvement afforded by our prefetching strategy and to analyze the reference patterns in a set of Fortran benchmarks. We also study the effectiveness of prefetching in a realistic shared-memory system using an RTL-level simulator and real codes. This differs from previous studies by considering prefetching benefits in the presence of network contention.

Memory access dependencies in shared-memory multiprocessors

Abstract: The presence of high-performance mechanisms in shared-memory multiprocessors such as private caches, the extensive pipelining of memory access, and combining networks may render a logical concurrency model complex to implement or inefficient. The problem of implementing a given logical concurrency model in such a multiprocessor is addressed. Two concurrency models are considered, and simple rules are introduced to verify that a multiprocessor architecture adheres to the models. The rules are applied to several examples of multiprocessor architectures. >

Recoverable distributed shared virtual memory

Abstract: The problem of rollback recovery in distributed shared virtual environments, in which the shared memory is implemented in software in a loosely coupled distributed multicomputer system, is examined. A user-transparent checkpointing recovery scheme and a new twin-page disk storage management technique are presented for implementing recoverable distributed shared virtual memory. The checkpointing scheme can be integrated with the memory coherence protocol for managing the shared virtual memory. The twin-page disk design allows checkpointing to proceed in an incremental fashion without an explicit undo at the time of recovery. The recoverable distributed shared virtual memory allows the system to restart computation from a checkpoint without a global restart. >

PLUS: a distributed shared-memory system

Abstract: PLUS is a multiprocessor architecture tailored to the fast execution of a single multithreaded process; its goal is to accelerate the execution of CPU-bound applications. PLUS supports shared memory and efficient synchronization. Memory access latency is reduced by non-demand replication of pages with hardware-supported coherence between replicated pages. The architecture has been simulated in detail and the paper presents some of the key measurements that have been used to substantiate our architectural decisions. The current implementation of PLUS is also described.

Virtual time II: storage management in conservative and optimistic systems

Abstract: The main contribution of this paper is the Cancelback Protocol, an extension of the Time Warp mechanism that handles storage management. It includes both fossil collection, the recovery of storage for messages and states that can never again influence the computation, and cancelback, the recovery of storage assigned to messages and states at times so far in the future that their memory would be better used for more immediate purposes. It guarantees that Time Warp is optimal in its storage requirements when run in shared memory, i.e. Time Warp will successfully complete a simulation using no more space than it would take to execute the same simulation with the sequential event list algorithm. This is better by a factor of two than the only previously published result. Without this protocol (or equivalent) Time Warp’s behavior can be unstable; hence it should be considered an essential part of Time Warp mechanism, rather than simply a refinement. In addition we also prove that asynchronous conservative algorithms, including all of the Chandy-Misra-Bryant (CMB) mechanisms, are not optimal; they cannot necesPermission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific permission.

Stability in a Persistent Store Based on a Large Virtual Memory

Abstract: Persistent systems support mechanisms which allow programs to create and manipulate arbitrary data structures which outlive the execution of the program which created them. A persistent store supports mechanisms for the storage and retrieval of objects in a uniform manner regardless of their lifetime. Since all data of the system is in this repository it is important that it always be in a consistent state. This property is called integrity. The integrity of the persistent store depends in part on the store being resilient to failures. That is, when an error occurs the store can recover to a previously recorded consistent state. The mechanism for recording this state and performing recovery is called stability. This paper considers an implementation of a persistent store based on a large virtual memory and shows how stability is achieved.

Memory array addressing system for computer systems with multiple memory arrays

Abstract: A computer system has a set of memory module slots, each of which may receive a memory module or may be left empty. The memory slots are arranged to accept at least two different types of memory modules having different amounts of memory storage. Each type of memory module generates a module type signal which denotes the type of the module and thus the amount of memory storage in the module. Whenever the system is powered on or reset, the system's memory initialization software analyzes the module type signals generated by the memory modules which are installed in memory slots. Each memory module is assigned a physical address range based solely on the size of the memory module and the slot in which it is located, regardless of what other memory modules are being used. The computer system thereby determines which portions of the computer's address space will be used for primary memory. The computer system is a multitasking computer system which has a virtual memory management system. Once the addresses occupied by memory modules have been identified, the primary memory is divided into a set of pages. The usage of these pages are governed by the computer system's virtual memory management system, which guarantees that all memory references to primary memory will reference only addresses in the aforementioned set of pages.

Buffer management method and system therefor using an I/O buffer on main memory and utilizing virtual memory and page fixing

Abstract: In a computer system including a main memory and an expanded memory for expanding said main memory logically, a program operating on a virtual memory space, which is managed by the virtual memory management of an operating system, for managing the input/output of the data on an external storage device by using an I/O buffer has a function to manage the I/O buffer secured on the expanded memory, so that the I/O processing for the external storage memory may be reduced by either saving the data, if necessary, of the I/O buffer on the virtual space into the I/O buffer on the expanded memory or restoring the same to the I/O buffer on the virtual space, whereby the I/O buffers can be efficiently utilized.

A New Data Structure for Implementing Extensions to Prolog

Abstract: We propose a new data structure for implementing delayed computations in Prolog as efficiently as commonly employed solutions, together with the optimal memory management needed for this data structure. It appears that this data structure (and the associated memory management) is also useful for implementing other extensions where there is a need for reversibly modifying terms other than in the leaves, e.g. functional extensions.

Method and apparatus for a backup power controller for volatile random access memory

Abstract: A method and apparatus for a software actuable backup power controller for selectively controlling power to a volatile random access cache memory. If memory does not contain any data that needs to be retained during a primary power failure the controller isolates memory from the backup power supply during the power failure. Only when the memory contains data to be retained during a power failure will memory be treated as non-volatile and is the backup power supply connected to memory on primary power failure. By selectively enabling the backup power supply with software commands from the computer, a suitable cache memory can be constructed with a compact non-rechargeable battery.

Method of managing memory allocation by association of memory blocks with a tree structure

Abstract: A memory resource is managed by allocation of memory blocks within a larger free memory block to reduce fragmentation and provide efficient methods for consolidation of previously allocated memory blocks into larger free memory blocks.

Resource and memory management algorithms for electric printing and electronic reprographic systems

Abstract: A printing system having an electronic sub system loaded with control software which controls scanning, image storing and the printing operations of the printing system The control software schedules the bandwidth of disk storage and swaps images from a storage disk to a memory so that a desired image will be in memory when the printing of that image is requested The system utilizes resource management and/or memory management software to realize improved job turn around time and to reduce pitch skips

Fault-tolerant digital computing system with reduced memory redundancy

Abstract: A highly reliable data processing system using the pair-spare architecture obviates the need for separate memory arrays for each processor. A single memory is shared between each pair of processors wherein a linear block code error detection scheme is implemented with each shared memory, wherein the effect of random memory faults is sufficiently detected such that the inherent fault tolerance of a pair-spare architecture is not compromised.

Method and apparatus for processing information and providing cache invalidation information

Abstract: An information processing system includes a main memory, a request source, a data buffer, a memory request control unit, and a cache invalidation control unit. The request source generates a memory request to the main memory. The data buffer is provided between the request source and the main memory and temporarily stores memory request information from the request source. The memory request control unit reads out the memory request information from the data buffer to execute and control access of the main memory. The cache invalidation control unit controls cache invalidation processing with respect to the request source on the basis of the memory request information. The information processing system further includes a data read address buffer and a data buffer control unit. The data read address buffer stores a storage address of the memory request information in the data buffer. The data buffer control unit reads out the storage address in the data read address buffer to access the data buffer. A memory request address of the memory request information read out from the data buffer is used to perform the cache invalidation processing with respect to the request source.

Real-Time UNIX® Systems: Design and Application Guide

Abstract: 1 Introduction to Real-Time Computing.- 1.1 Definition and Classification of Real-Time Computer Systems.- 1.2 Computer Requirements for Real-Time Applications.- 1.3 Systems Issues.- 1.4 Real-Time Measures.- 1.4.1 Rhealstone Metric.- 1.4.2 Process Dispatch Latency Time.- 1.4.3 Tri-Dimensional Measure.- 1.4.4 The Real/Stone Benchmark.- 1.5 Model of an Open Real-Time System.- 2 Real-Time Operating Systems.- 2.1 Requirements for Real-Time Operating Systems.- 2.2 Real-Time UNIX Operating Systems.- 2.2.1 The UNIX System and Real-Time.- 2.2.2 Real-Time UNIX Standards.- 2.2.3 Real-Time UNIX Implementations.- 3 Concept of a Fully Preemptive UNIX Operating System.- 3.1 System Concept.- 3.2 Process Subsystem.- 3.2.1 Process Concept.- 3.2.2 Process Creation and Termination.- 3.2.3 Forking Child Processes.- 3.2.4 Waiting for a Child Process to Terminate.- 3.2.5 Process States.- 3.3 Memory Management.- 3.3.1 Data Structures.- 3.3.2 Paging.- 3.3.3 Allocating Memory.- 3.3.4 Locking Pages in Memory.- 3.4 Process Scheduling.- 3.4.1 Data Structure Integrity.- 3.4.2 Timers.- 3.5 Interprocess Communication.- 3.5.1 Signal Mechanism.- 3.5.2 Common Event Notification.- 3.5.3 Shared Memory.- 3.5.4 User-Level Semaphores.- 3.6 File Subsystem.- 3.6.1 File Types.- 3.6.2 File Listings.- 3.6.3 File Permissions.- 3.6.4 User View of a File System.- 3.6.5 Accessing Files in Programs.- 3.6.6 File System Structure.- 3.6.7 Accessing Data Storage Blocks.- 3.6.8 Accessing Free Inodes and Data Blocks.- 3.6.9 File System Access Tables.- 3.6.10 Using the File Access Tables.- 3.7 I/O Subsystem.- 3.7.1 Device I/O.- 3.7.2 I/O Transfer Methods.- 3.7.3 Initiating I/O Operations.- 3.7.4 Device Interrupts.- 3.7.5 Drivers for Real-Time Applications.- 4 Designing Real-Time Applications.- 4.1 Programming Guidelines.- 4.1.1 Real-Time Program Structure.- 4.1.2 Development Procedure.- 4.1.3 Using System Calls.- 4.1.4 Performance Hints.- 4.2 Scheduling Processes.- 4.2.1 Selecting Process Priorities.- 4.2.2 Setting Real-Time Privileges.- 4.2.3 Changing Process Priority.- 4.2.4 Monitoring the Run Queue.- 4.2.5 Real-Time Timers.- 4.3 Real-Time Memory Allocation.- 4.3.1 Controlling Memory Allocation.- 4.3.2 Locking Pages into Memory.- 4.3.3 Example Program: Preallocating Memory for a Process.- 4.3.4 Example Program: Handling Real-Time Memory Violations.- 4.4 Interprocess Communications: Pipes, Signals and Events.- 4.4.1 Pipes and Named Pipes.- 4.4.2 Signals.- 4.4.3 Common Event Notification Mechanism.- 4.5 Interprocess Communications Using Shared Memory.- 4.5.1 Using Shared Memory.- 4.5.2 Creating a Shared Memory Segment.- 4.5.3 Allocating a Physical Shared Memory Segment.- 4.5.4 Controlling Shared Memory.- 4.5.5 Attaching and Detaching a Shared Memory Segment..- 4.5.6 Getting Physical Shared Memory Segment.- 4.5.7 Checking the Status of a Shared Memory Segment.- 4.6 Interprocess Communications Using Semaphores.- 4.6.1 Creating a Semaphore Structure and Array.- 4.6.2 Controlling Semaphores.- 4.6.3 Operations on Semaphores.- 4.6.4 Using Binary Semaphores.- 4.7 Interprocess Communications Using Messages.- 4.7.1 Creating Message Queues.- 4.7.2 Controlling Message Queues.- 4.7.3 Message Operations.- 4.8 Using Files.- 4.8.1 Fast File System.- 4.8.2 Creating Files and File Systems.- 4.8.3 Preallocating File Space.- 4.8.4 Bypassing the Buffer Cache.- 4.8.5 Asynchronous File I/O.- 4.8.6 Using Both Synchronous and Asynchronous I/O on a File.- 4.8.7 Synchronizing Disk Access.- 4.9 Interfacing Devices.- 4.9.1 Asynchronous I/O Operations.- 4.9.2 Traditional UNIX System Interrupts.- 4.9.3 Connected Interrupts.- 4.9.4 Direct I/O.- 4.10 Writing System Calls.- 4.10.1 Overview of System Calls.- 4.10.2 Guidelines for Writing System Calls.- 4.10.3 Installing System Calls in the Kernel.- 4.10.4 Accessing User-Defined System Calls.- 4.11 Porting Applications.- 4.11.1 Porting SVID-Compatible Applications.- 4.11.2 Porting from Proprietary Operating Systems.- 4.12 Performance Management.- 4.12.1 Creating an Efficient Environment.- 4.12.2 Maintaining System Efficiency.- 4.12.3 Solving Performance Problems.- 4.12.4 Measuring Performance.- 4.12.5 Performance Evaluation of the REAL/IX System.- 5 Case Studies.- 5.1 The Data Acquisition and Space Shuttle Launch Control System at NASA Kennedy Space Center.- 5.1.1 The Data Acquisition System.- 5.1.2 The Application Processing System.- 5.2 The Communication Processor at Jet Propulsion Laboratory.

Multi-version memory: software cache management for concurrent B-trees

Abstract: The authors describe a new concurrent B-tree algorithm. The algorithm is designed to work well in large-scale parallel or distributed systems in which the number of processors sharing the tree is large or the communication delay between processors (or between processors and the global memory for a shared-memory system) is large relative to the speed of local computation. The basis of the algorithm is an abstraction that is similar to coherent shared memory, but provides a weaker semantics; this abstraction is called multiversion memory. Multi-version memory uses caches but weakens the semantics of ordinary shared memory by allowing process reading data to be given an old version of the data. This semantics is adequate for the non-leaf nodes in the B-tree algorithms presented. >

Update propagation in distributed memory hierarchy

Abstract: A distributed memory hierarchy (DMH) is a memory system consisting of storage modules distributed over a high-bandwidth local area network. It provides for transaction applications an abstraction of single virtual memory space to which shared data are mapped. As in a conventional memory hierarchy (MH) in a single-machine system, a DMH is responsible for locating, migrating, and caching data pages; however, unlike a conventional MH, a DMH must do so across the storage modules in a network. In addition, a DMH must handle the problem of propagation of transaction updates preserving serializability of transactions. The performance of a DMH system is strongly influenced by concurrency control and update propagation. It is also crucial that performance analysis accounts for memory resources and network requirements. A DMH system is presented, the tradeoffs between conservative and aggressive update propagation strategies are defined, and promising new strategies are identified. >