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Memory management

About: Memory management is a research topic. Over the lifetime, 16743 publications have been published within this topic receiving 312028 citations. The topic is also known as: memory allocation.


Papers
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Patent
21 Sep 2011
TL;DR: In this paper, the Elementary Network Description (END) format is proposed to describe a large-scale neuronal model and implementations of software or hardware engines to simulate such a model efficiently, and the architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity.
Abstract: A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. Methods for managing memory in a processing system are described whereby memory can be allocated among a plurality of elements and rules configured for each element such that the parallel execution of the spiking networks is most optimal.

90 citations

Journal ArticleDOI
TL;DR: Current results show several emerging memory technologies related to nonvolatile memory (NVM) devices are being investigated as an alternative for DRAM and could offer high-bandwidth I/O, larger main memory capacities, persistent data structures, and new approaches for application resilience and output postprocessing.
Abstract: For extreme-scale high-performance computing systems, system-wide power consumption has been identified as one of the key constraints moving forward, where DRAM main memory systems account for about 30 to 50 percent of a node's overall power consumption. As the benefits of device scaling for DRAM memory slow, it will become increasingly difficult to keep memory capacities balanced with increasing computational rates offered by next-generation processors. However, several emerging memory technologies related to nonvolatile memory (NVM) devices are being investigated as an alternative for DRAM. Moving forward, NVM devices could offer solutions for HPC architectures. Researchers are investigating how to integrate these emerging technologies into future extreme-scale HPC systems and how to expose these capabilities in the software stack and applications. Current results show several of these strategies could offer high-bandwidth I/O, larger main memory capacities, persistent data structures, and new approaches for application resilience and output postprocessing, such as transaction-based incremental checkpointing and in situ visualization, respectively.

90 citations

Journal ArticleDOI
TL;DR: An operating system for a workstation designed and implemented by the authors within two and a half years, which includes memory management and module loader, a file system, a viewer system, editors for text and graphics, a compiler, a server interface and various tools.
Abstract: In this paper we describe an operating system for a workstation designed and implemented by the authors within two and a half years. It includes memory management and module loader, a file system, a viewer system, editors for text and graphics, a compiler, a server interface and various tools. The primary motivation was to demonstrate the feasibility of a small, yet highly flexible and powerful, system, a system that is a (decimal) order of magnitude smaller than commonly used operating systems. This is possible due to regularity of concepts and concentration on the essential. The benefits are not only fewer resources needed, but elegance and generality of concepts resulting in transparency and convenience of use and increased reliability. A corner-stone of this approach is genuine extensibility, which is achieved by a new language, in particular by a facility called type extension. It allows for the integration of variables (objects) of a new, extended type in structures of elements of an existing base type.

90 citations

Patent
Kenneth Ma1
04 Jun 2003
TL;DR: In this paper, a method and apparatus for performing adaptive memory power management in a system employing a CPU and a memory subsystem is described, which is performed on a time segment by time segment basis to achieve efficient power management of memory subsystem during CPU run time.
Abstract: A method and apparatus are disclosed for performing adaptive memory power management in a system employing a CPU and a memory subsystem. A CPU throttle control (THR) module generates a CPU throttle control signal indicating when the CPU is idle. A memory controller (MC) module generates memory power management signals based on at least one of the CPU throttle control signal, memory read/write signals, memory access break events, and bus master access requests. Certain portions of the memory subsystem are powered down in response to the memory power management signals. Memory power management is performed on a time segment by time segment basis to achieve efficient power management of the memory subsystem during CPU run time.

89 citations

Patent
Lance W. Russell1
04 Oct 2001
TL;DR: In this paper, the authors describe a shared memory multi-computer environment, where a local shared memory network is provided between local nodes and global shared memory networks are provided between nodes and one or more remote nodes.
Abstract: Systems and methods of processing packets in a shared memory multi-computer environment are described. A local shared memory network is provided between local nodes and a global shared memory network is provided between the local nodes and one or more remote nodes. In this way, local nodes may communicate through standard network interfaces while using shared memory as the physical transport medium. In addition, a multi-computer system may be addressed externally and internally as individual nodes over the local shared memory network. A multi-computer system also may be addressed externally and internally as a single node over the global shared memory network.

89 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202333
202288
2021629
2020467
2019461
2018591