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Memory management

About: Memory management is a research topic. Over the lifetime, 16743 publications have been published within this topic receiving 312028 citations. The topic is also known as: memory allocation.


Papers
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Book ChapterDOI
07 Sep 2005
TL;DR: A new type system for an object-oriented (OO) language that characterizes the sizes of data structures and the amount of heap memory required to successfully execute methods that operate on these data structures is presented.
Abstract: We present a new type system for an object-oriented (OO) language that characterizes the sizes of data structures and the amount of heap memory required to successfully execute methods that operate on these data structures. Key components of this type system include type assertions that use symbolic Presburger arithmetic expressions to capture data structure sizes, the effect of methods on the data structures that they manipulate, and the amount of memory that methods allocate and deallocate. For each method, we conservatively capture the amount of memory required to execute the method as a function of the sizes of the method's inputs. The safety guarantee is that the method will never attempt to use more memory than its type expressions specify. We have implemented a type checker to verify memory usages of OO programs. Our experience is that the type system can precisely and effectively capture memory bounds for a wide range of programs.

74 citations

Journal ArticleDOI
TL;DR: The analysis and numerical evaluation suggest that the proposed Replisom system has significant potential in reducing the delay, energy consumption, and cost for cloud offloading of IoT applications given the massive number of devices with tiny memory sizes.
Abstract: Augmenting the long-term evolution (LTE)-evolved NodeB (eNB) with cloud resources offers a low-latency, resilient, and LTE-aware environment for offloading the Internet of Things (IoT) services and applications. By means of devices memory replication, the IoT applications deployed at an LTE-integrated edge cloud can scale its computing and storage requirements to support different resource-intensive service offerings. Despite this potential, the massive number of IoT devices limits the LTE edge cloud responsiveness as the LTE radio interface becomes the major bottleneck given the unscalability of its uplink access and data transfer procedures to support a large number of devices that simultaneously replicate their memory objects with the LTE edge cloud. We propose Replisom ; an LTE-aware edge cloud architecture and an LTE-optimized memory replication protocol which relaxes the LTE bottlenecks by a delay and radio resource-efficient memory replication protocol based on the device-to-device communication technology and the sparse recovery in the theory of compressed sampling. Replisom effectively schedules the memory replication occasions to resolve contentions for the radio resources as a large number of devices simultaneously transmit their memory replicas. Our analysis and numerical evaluation suggest that this system has significant potential in reducing the delay, energy consumption, and cost for cloud offloading of IoT applications given the massive number of devices with tiny memory sizes.

74 citations

Proceedings ArticleDOI
19 Mar 2018
TL;DR: Illuminator is presented, an efficient memory manager that provides various subsystems, such as the page allocator, the ability to track all unmovable pages, which allows subsystems to make informed decisions and eliminate unnecessary work which in turn leads to cost-effective huge page allocations.
Abstract: The virtual-to-physical address translation overhead, a major performance bottleneck for modern workloads, can be effectively alleviated with huge pages. However, since huge pages must be mapped contiguously, OSs have not been able to use them well because of the memory fragmentation problem despite hardware support for huge pages being available for nearly two decades. This paper presents a comprehensive study of the interaction of fragmentation with huge pages in the Linux kernel. We observe that when huge pages are used, problems such as high CPU utilization and latency spikes occur because of unnecessary work (e.g., useless page migration) performed by memory management related subsystems due to the poor handling of unmovable (i.e., kernel) pages. This behavior is even more harmful in virtualized systems where unnecessary work may be performed in both guest and host OSs. We present Illuminator, an efficient memory manager that provides various subsystems, such as the page allocator, the ability to track all unmovable pages. It allows subsystems to make informed decisions and eliminate unnecessary work which in turn leads to cost-effective huge page allocations. Illuminator reduces the cost of compaction (up to 99%), improves application performance (up to 2.3x) and reduces the maximum latency of MySQL database server (by 30x). Importantly, this work shows the effectiveness of a simple solution for long-standing huge page related problems.

74 citations

Patent
Andre Schaefer1, Matthias Gries1
23 Dec 2009
TL;DR: In this paper, a memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of mappings, and can be modified for any of different granularities possible within the system, from the byte level to memory channel.
Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

74 citations

Patent
03 Aug 1998
TL;DR: In this article, a stand-alone memory interface is presented to provide a menu showing multiple ways in which the user's request can be physically configured by varying the number of rows of memory, number of blocks of memory and the column multiplexing factor of the memory array.
Abstract: A compilier methodology including a stand alone memory interface which provides a user specified memory device of a required number of words of memory of a required bits per word. The stand alone memory interface is a tool to provide a menu showing multiple ways in which the user's request can be physically configured by varying the number of rows of memory, the number of blocks of memory, and the column multiplexing factor of the memory array. From this menu the user selects the memory configuration that best meets the user's requirements and is provided with either various models or representations (views) of the selected memory configuration or a GDS format data file. The views can be used to design large scale integrated circuits in which the memory device is embedded while the data file is used to generate photo mask for making the memory device as an integrated circuit.

74 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202333
202288
2021629
2020467
2019461
2018591