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Memory management

About: Memory management is a research topic. Over the lifetime, 16743 publications have been published within this topic receiving 312028 citations. The topic is also known as: memory allocation.


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Patent
Steven Sprouse1
17 Nov 2010
TL;DR: In this paper, a memory system (100, 200) that includes a memory array (106, 206a, 206b), and a memory controller (104, 204) manages power consumption by maintaining a variable credit value (108, 208, 300) that reflects the amount of power available to the memory system.
Abstract: A memory system (100, 200) that includes a memory array (106, 206a, 206b,) and a memory controller (104, 204) manages power consumption by maintaining a variable credit value (108, 208, 300) that reflects the amount of power available to the memory system (100, 200). The variable credit value (108, 208, 300) may be increased periodically up to a limit. When a power-consuming operation is performed, the variable credit value (108, 208, 300) is reduced to reflect the power used.

71 citations

Patent
19 Feb 2010
TL;DR: In this paper, the first processor of a plurality of processors in a multi-processor system is allowed to access the memory location responsive to a memory access instruction within a speculative region of a program.
Abstract: A method for accessing memory by a first processor of a plurality of processors in a multi-processor system includes, responsive to a memory access instruction within a speculative region of a program, accessing contents of a memory location using a transactional memory access to the memory access instruction unless the memory access instruction indicates a non-transactional memory access. The method may include accessing contents of the memory location using a non-transactional memory access by the first processor according to the memory access instruction responsive to the instruction not being in the speculative region of the program. The method may include updating contents of the memory location responsive to the speculative region of the program executing successfully and the memory access instruction not being annotated to be a non-transactional memory access.

71 citations

Patent
30 Jun 1997
TL;DR: In this article, a method of executing a sequence of multiple dependent operations, each operation including a memory read and a memory write involves overlapping memory accesses of the operations by grouping together memory reads and memory writes of multiple operations and preserving a desired sequence of operations using a circuit external to a memory through which the accesses are performed.
Abstract: A method of executing a sequence of multiple dependent operations, each operation including a memory read and a memory write involves overlapping memory accesses of the operations by grouping together memory reads and memory writes of multiple operations and preserving a desired sequence of the operations using a circuit external to a memory through which the memory accesses are performed. The operations may be updates to one or more linked lists. In one embodiment, the step of overlapping memory accesses may be performed by grouping together memory accesses according to ATM cell arrivals or departures. In this embodiment, the operations are associated with ATM cell arrivals or departures and may be gets or puts. Each get and put operation may be characterized by a number of atomic memory operations to update one or more linked lists. To perform the operations a circuit a having an address processor, a data processor coupled to the address processor and to the external memory, and a prefetch buffer coupled to the external memory, the address processor and to the data processor is provided. The address processor generates memory addresses for the operations according to the step of overlapping memory accesses. The atomic memory operations are grouped so that all of the memory read operations associated with the dependent operations are performed before all of the memory write operations associated with the dependent operations are performed.

71 citations

Patent
25 Nov 1992
TL;DR: In this paper, a data management system for a programming-limited type of semiconductor memory (M) which is programmable a limited number of times and which includes a plurality of storage areas is presented.
Abstract: In a data management system for a programming-limited type semiconductor memory (M) which is programmable a limited number of times and which includes a plurality of storage areas, a management unit (1) manages, for each of the storage areas, the number of times that programming has been performed A control unit (2) selects one of the storage areas for which programming has been performed the smallest number of times and has input data is written into the selected one of the storage areas, so that all the storage areas can be equally programmed

70 citations

Journal ArticleDOI
TL;DR: A generalized conflict-free memory addressing scheme for memory-based fast Fourier transform (FFT) processors with parallel arithmetic processing units made up of radix-2q multi-path delay commutator (MDC) is presented.
Abstract: This paper presents a generalized conflict-free memory addressing scheme for memory-based fast Fourier transform (FFT) processors with parallel arithmetic processing units made up of radix-2q multi-path delay commutator (MDC). The proposed addressing scheme considers the continuous-flow operation with minimum shared memory requirements. To improve throughput, parallel high-radix processing units are employed. We prove that the solution to non-conflict memory access satisfying the constraints of the continuous-flow, variable-size, higher-radix, and parallel-processing operations indeed exists. In addition, a rescheduling technique for twiddle-factor multiplication is developed to reduce hardware complexity and to enhance hardware efficiency. From the results, we can see that the proposed processor has high utilization and efficiency to support flexible configurability for various FFT sizes with fewer computation cycles than the conventional radix-2/radix-4 memory-based FFT processors.

70 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202333
202288
2021629
2020467
2019461
2018591