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Memory management

About: Memory management is a research topic. Over the lifetime, 16743 publications have been published within this topic receiving 312028 citations. The topic is also known as: memory allocation.


Papers
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Journal ArticleDOI
TL;DR: A fundamentally different approach is needed, in which the cache contents are used as side information for coded communication over the shared link, and it is proposed and proved that it is close to optimal.
Abstract: We consider a network consisting of a file server connected through a shared link to a number of users, each equipped with a cache. Knowing the popularity distribution of the files, the goal is to optimally populate the caches, such as to minimize the expected load of the shared link. For a single cache, it is well known that storing the most popular files is optimal in this setting. However, we show here that this is no longer the case for multiple caches. Indeed, caching only the most popular files can be highly suboptimal. Instead, a fundamentally different approach is needed, in which the cache contents are used as side information for coded communication over the shared link. We propose such a coded caching scheme and prove that it is close to optimal.

224 citations

Patent
09 Aug 1999
TL;DR: A hardware assisted memory module (HAMM) is coupled to a conventional computer system as discussed by the authors, which can be configured to copy all or part of the digital information to nonvolatile memory.
Abstract: A hardware assisted memory module (HAMM) is coupled to a conventional computer system. During normal operation of the computer system, the HAMM behaves like a conventional memory module. The HAMM, however, detects and responds to at least one of the following trigger events: 1) power failure, 2) operating system hang-up, or 3) unexpected system reset. Upon detection of a trigger event, the HAMM electronically isolates itself from the host computer system before copying digital information from volatile memory to nonvolatile memory. Once isolated, the HAMM takes its power from an auxiliary power supply. The HAMM can be configured to copy all or part of the digital information to nonvolatile memory. Upon either a request or at power-up, the HAMM copies the digital information from the nonvolatile memory into the volatile memory. If there is a normal computer shutdown, the operating system will first warn the HAMM before shutting down, thus precluding it from performing a backup operation. The operating system determines whether the last shutdown was unexpected by reading a register stored in a reserved area of memory. If the operating system wants the digital information restored, it orders the HAMM to restore the backed-up digital information from nonvolatile memory to volatile memory.

224 citations

Patent
07 Jun 1995
TL;DR: In this paper, a television electronic program guide intelligent memory management system and method automatically deletes the least valuable stored program information at that moment as free memory space is needed by the system.
Abstract: A television electronic program guide intelligent memory management system and method automatically deletes the least valuable stored program information at that moment as free memory space is needed by the system. In advance of a program schedule update, the system executes a two-level memory "housekeeping" operation in which the system first scans the memory to identify obsolete schedule information. If, after this sweep, there is insufficient memory available for the next update, the system performs a second-level memory "triage" operation wherein schedule information is automatically prioritized in accordance with pre-defined rules for assessing the current value of the information to each viewer based on program air time, channel and other variables relating to program utility. The system then deletes schedule information in ascending order of value, starting with the least valuable information, and continues until enough space is available in memory to store the schedule update.

221 citations

Proceedings ArticleDOI
01 Dec 1995
TL;DR: The bare minimum amount of local memories that programs require to run without delay is measured by using the Value Reuse Profile, which contains the dynamic value reuse information of a program's execution, and by assuming the existence of efficient memory systems.
Abstract: As processor performance continues to improve, more emphasis must be placed on the performance of the memory system. In this paper, a detailed characterization of data cache behavior for individual load instructions is given. We show that by selectively applying cache line allocation according the characteristics of individual load instructions, overall performance can be improved for both the data cache and the memory system. This approach can improve some aspects of memory performance by as much as 60 percent on existing executables.

221 citations

Proceedings ArticleDOI
30 Sep 2012
TL;DR: A policy is devised that avoids accessing in PCM data that frequently causes row buffer misses because such accesses are costly in terms of both latency and energy.
Abstract: Phase change memory (PCM) is a promising technology that can offer higher capacity than DRAM. Unfortunately, PCM's access latency and energy are higher than DRAM's and its endurance is lower. Many DRAM-PCM hybrid memory systems use DRAM as a cache to PCM, to achieve the low access latency and energy, and high endurance of DRAM, while taking advantage of PCM's large capacity. A key question is what data to cache in DRAM to best exploit the advantages of each technology while avoiding its disadvantages as much as possible. We propose a new caching policy that improves hybrid memory performance and energy efficiency. Our observation is that both DRAM and PCM banks employ row buffers that act as a cache for the most recently accessed memory row. Accesses that are row buffer hits incur similar latencies (and energy consumption) in DRAM and PCM, whereas accesses that are row buffer misses incur longer latencies (and higher energy consumption) in PCM. To exploit this, we devise a policy that avoids accessing in PCM data that frequently causes row buffer misses because such accesses are costly in terms of both latency and energy. Our policy tracks the row buffer miss counts of recently used rows in PCM, and caches in DRAM the rows that are predicted to incur frequent row buffer misses. Our proposed caching policy also takes into account the high write latencies of PCM, in addition to row buffer locality. Compared to a conventional DRAM-PCM hybrid memory system, our row buffer locality-aware caching policy improves system performance by 14% and energy efficiency by 10% on data-intensive server and cloud-type workloads. The proposed policy achieves 31% performance gain over an all-PCM memory system, and comes within 29% of the performance of an allDRAM memory system (not taking PCM's capacity benefit into account) on evaluated workloads.

219 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202333
202288
2021629
2020467
2019461
2018591