Topic
Memory management
About: Memory management is a research topic. Over the lifetime, 16743 publications have been published within this topic receiving 312028 citations. The topic is also known as: memory allocation.
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TL;DR: This paper proposes a new methodology for constructing lock-free and wait-free implementations of concurrent objects that are presented for a multiple instruction/multiple data (MIMD) architecture in which n processes communicate by applying atomic read, write, load_linked, and store_conditional operations to a shared memory.
Abstract: A concurrent object is a data structure shared by concurrent processes. Conventional techniques for implementing concurrent objects typically rely on critical sections; ensuring that only one process at a time can operate on the object. Nevertheless, critical sections are poorly suited for asynchronous systems: if one process is halted or delayed in a critical section, other, nonfaulty processes will be unable to progress. By contrast, a concurrent object implementation is lock free if it always guarantees that some process will complete an operation in a finite number of steps, and it is wait free if it guarantees that each process will complete an operation in a finite number of steps. This paper proposes a new methodology for constructing lock-free and wait-free implementations of concurrent objects. The object's representation and operations are written as stylized sequential programs, with no explicit synchronization. Each sequential operation is atutomatically transformed into a lock-free or wait-free operation using novel synchronization and memory management algorithms. These algorithms are presented for a multiple instruction/multiple data (MIMD) architecture in which n processes communicate by applying atomic read, write, load_linked, and store_conditional operations to a shared memory.
553 citations
Book•
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11 Feb 1998
TL;DR: This book discusses the role of the Device Driver, the Kernel Classes of Devices and Modules, and more about how Mounting and Unmounting works.
Abstract: Preface. Chapter 1. An Introduction to Device Drivers The Role of the Device Driver Splitting the Kernel Classes of Devices and Modules Security Issues Version Numbering License Terms Joining the Kernel Development Community Overview of the Book. Chapter 2. Building and Running Modules Kernel Modules Versus Applications Compiling and Loading The Kernel Symbol Table Initialization and Shutdown Using Resources Automatic and Manual Configuration Doing It in User Space Backward Compatibility Quick Reference. Chapter 3. Char Drivers The Design of scull Major and Minor Numbers File Operations The file Structure open and release scull's Memory Usage A Brief Introduction to Race Conditions read and write Playing with the New Devices The Device Filesystem Backward Compatibility Quick Reference. Chapter 4. Debugging Techniques Debugging by Printing Debugging by Querying Debugging by Watching Debugging System Faults Debuggers and Related Tools. Chapter 5. Enhanced Char Driver Operations ioctl Blocking I/O poll and select Asynchronous Notification Seeking a Device Access Control on a Device File Backward Compatibility Quick Reference. Chapter 6. Flow of Time Time Intervals in the Kernel Knowing the Current Time Delaying Execution Task Queues Kernel Timers Backward Compatibility Quick Reference. Chapter 7. Getting Hold of Memory The Real Story of kmalloc Lookaside Caches get_free_page and Friends vmalloc and Friends Boot-Time Allocation Backward Compatibility Quick Reference Chapter 8. Hardware Management I/O Ports and I/O Memory Using I/O Ports Using Digital I/O Ports Using I/O Memory Backward Compatibility Quick Reference. Chapter 9. Interrupt Handling Overall Control of Interrupts Preparing the Parallel Port Installing an Interrupt Handler Implementing a Handler Tasklets and Bottom-Half Processing Interrupt Sharing Interrupt-Driven I/O Race Conditions Backward Compatibility Quick Reference. Chapter 10. Judicious Use of Data Types Use of Standard C Types Assigning an Explicit Size to Data Items Interface-Specific Types Other Portability Issues Linked Lists Quick Reference. Chapter 11. kmod and Advanced Modularization Loading Modules on Demand Intermodule Communication Version Control in Modules Backward Compatibility Quick Reference. Chapter 12. Loading Block Drivers Registering the Driver The Header File blk.h Handling Requests: A Simple Introduction Handling Requests: The Detailed View How Mounting and Unmounting Works The ioctl Method Removable Devices Partitionable Devices Interrupt-Driven Block Drivers Backward Compatibility Quick Reference. Chapter 13. mmap and DMA Memory Management in Linux The mmap Device Operation The kiobuf Interface Direct Memory Access and Bus Mastering Backward Compatibility Quick Reference. Chapter 14. Network Drivers How snull Is Designed Connecting to the Kernel The net_device Structure in Detail Opening and Closing Packet Transmission Packet Reception The Interrupt Handler Changes in Link State The Socket Buffers MAC Address Resolution Custom ioctl Commands Statistical Information Multicasting Backward Compatibility Quick Reference. Chapter 15. Overview of Peripheral Buses The PCI Interface A Look Back: ISA PC/104 and PC/104+ Other PC Buses SBus NuBus External Buses Backward Compatibility Quick Reference. Chapter 16. Physical Layout of the Kernel Source Booting the Kernel Before Booting The init Process The kernel Directory The fs Directory The mm Directory The net directory ipc and lib include and arch Drivers. Glossary. Index
549 citations
26 Jul 2009
TL;DR: PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM, and a low overhead hybrid hardware-software solution for managing it is proposed.
Abstract: In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges involved in incorporating PRAM into the main memory hierarchy of computing systems, and proposes a low overhead hybrid hardware-software solution for managing it. Our experimental results indicate that our solution is able to achieve average energy savings of 30% at negligible overhead over conventional memory architectures.
547 citations
18 Aug 2010
TL;DR: This paper proposes a new approach for measuring memory power and demonstrating its applicability to a novel power limiting algorithm and shows that it achieves up to 40% lower performance impact when compared to the state-of-art baseline across the power limiting range.
Abstract: The drive for higher performance and energy efficiency in data-centers has influenced trends toward increased power and cooling requirements in the facilities. Since enterprise servers rarely operate at their peak capacity, efficient power capping is deemed as a critical component of modern enterprise computing environments. In this paper we propose a new power measurement and power limiting architecture for main memory. Specifically, we describe a new approach for measuring memory power and demonstrate its applicability to a novel power limiting algorithm. We implement and evaluate our approach in the modern servers and show that we achieve up to 40% lower performance impact when compared to the state-of-art baseline across the power limiting range.
533 citations
TL;DR: An overview of distributed shared memory issues covers memory coherence, design choices, and implementation methods, and algorithms that support process synchronization and memory management are discussed.
Abstract: An overview of distributed shared memory (DSM) issues is presented. Memory coherence, design choices, and implementation methods are included. The discussion of design choices covers structure and granularity, coherence semantics, scalability, and heterogeneity. Implementation issues concern data location and access, the coherence protocol, replacement strategy, and thrashing. Algorithms that support process synchronization and memory management are discussed. >
524 citations