Memory management

About: Memory management is a research topic. Over the lifetime, 16743 publications have been published within this topic receiving 312028 citations. The topic is also known as: memory allocation.

Memory semantic storage I/O

Abstract: A mechanism for initiating and completing one or more I/O transactions using memory semantic messages is disclosed. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than the simple transmission of a message.

Makalu: fast recoverable allocation of non-volatile memory

Abstract: Byte addressable non-volatile memory (NVRAM) is likely to supplement, and perhaps eventually replace, DRAM. Applications can then persist data structures directly in memory instead of serializing them and storing them onto a durable block device. However, failures during execution can leave data structures in NVRAM unreachable or corrupt. In this paper, we present Makalu, a system that addresses non-volatile memory management. Makalu offers an integrated allocator and recovery-time garbage collector that maintains internal consistency, avoids NVRAM memory leaks, and is efficient, all in the face of failures. We show that a careful allocator design can support a less restrictive and a much more familiar programming model than existing persistent memory allocators. Our allocator significantly reduces the per allocation persistence overhead by lazily persisting non-essential metadata and by employing a post-failure recovery-time garbage collector. Experimental results show that the resulting online speed and scalability of our allocator are comparable to well-known transient allocators, and significantly better than state-of-the-art persistent allocators.

Mirrored memory dual controller disk storage system

Abstract: A disk storage control system includes dual controllers having real-time, synchronous, mirrored memory therebetween to provide immediate, accurate, and reliable failover in the event of controller failure. Non-volatile random access memory provides retention of data during a loss of power and during the manipulation of hardware for purposes of repair. A communication path is established within the mirrored memory between the controllers to monitor and coordinate their activities. The state of the mirrored memory is continuously monitored for accuracy of the mirror and failure detection. Concurrent and ready access by a host computer to the same disk storage control data set from each controller is provided without need for extra manipulation or extra direct memory access (DMA) activity to satisfy host requests. Accordingly, either controller can provide immediate and reliable failover control for the disk storage system. Furthermore, either controller can be hot swapped in the event of failure without the need for preparatory intervention. Finally, a secondary controller can recover a mirror image from a failed stand alone controller memory to provide continued operations thereby so long as the mirrored memory was not the failing component.

Defensive heap memory management

Abstract: A data structure, method and system are provided incorporating a general purpose memory allocator and defensive heap memory manager. This provides an ability to reliably detect various types of memory errors, dynamically enable or disable memory debugging, enhance success of read and write operations using various memory verification techniques. Further, through separation of control information associated with allocated and free chunks of memory from the chunks themselves (separation of metadata from actual data), enhanced protection of vital information about the heap memory layout in general is provided. The heap memory manager uses read, write, and execute protected heap header walls and pool header walls and may, for each pool and memory block, separately use hidden front and back Memory Debug Information Areas (MDIAs) with checksums and well-known signature fields thereby enhancing overall memory management.

Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings

Abstract: Efficient use of an optimized custom memory hierarchy to exploit temporal locality in the data accesses can have a very large impact on the power consumption in data dominated applications. In the past, experiments have demonstrated that this task is crucial in a complete low-power memory management methodology. But effective formalized techniques to deal with this specific task have not been addressed yet. In this paper, the surprisingly large design freedom available for the basic problem is explored in-depth and the outline of a systematic solution methodology is proposed. The efficiency of the methodology is illustrated on a real-life motion estimation application. The results obtained for this application show power reductions of about 85% for the memory subsystem compared to the case without a custom memory hierarchy. These large gains justify that data reuse and memory hierarchy decisions should be taken early in the design flow.