Showing papers on "Memristor published in 2011"
TL;DR: This work demonstrates a TaO(x)-based asymmetric passive switching device with which it was able to localize resistance switching and satisfy all aforementioned requirements, and eliminates any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.
Abstract: Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.
1,900 citations
TL;DR: The memristor is a 2-terminal nonvolatile memory device that exhibits a pinched hysteresis loop confined to the first and third quadrants of the v-i plane whose contour shape in general changes with both the amplitude and frequency of any periodic sine-wave-like input voltage source, or current source as mentioned in this paper.
Abstract: All 2-terminal non-volatile memory devices based on resistance switching are memristors, regardless of the device material and physical operating mechanisms. They all exhibit a distinctive “fingerprint” characterized by a pinched hysteresis loop confined to the first and the third quadrants of the v–i plane whose contour shape in general changes with both the amplitude and frequency of any periodic “sine-wave-like” input voltage source, or current source. In particular, the pinched hysteresis loop shrinks and tends to a straight line as frequency increases. Though numerous examples of voltage vs. current pinched hysteresis loops have been published in many unrelated fields, such as biology, chemistry, physics, etc., and observed from many unrelated phenomena, such as gas discharge arcs, mercury lamps, power conversion devices, earthquake conductance variations, etc., we restrict our examples in this tutorial to solid-state and/or nano devices where copious examples of published pinched hysteresis loops abound. In particular, we sampled arbitrarily, one example from each year between the years 2000 and 2010, to demonstrate that the memristor is a device that does not depend on any particular material, or physical mechanism. For example, we have shown that spin-transfer magnetic tunnel junctions are examples of memristors. We have also demonstrated that both bipolar and unipolar resistance switching devices are memristors.
1,208 citations
TL;DR: This study shows experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems and confirms that not only the shape or the total number of stimuli is influential, but also the time interval between stimulation pulses plays a crucial role in determining the effectiveness of the transition.
Abstract: “Memory” is an essential building block in learning and decision-making in biological systems. Unlike modern semiconductor memory devices, needless to say, human memory is by no means eternal. Yet, forgetfulness is not always a disadvantage since it releases memory storage for more important or more frequently accessed pieces of information and is thought to be necessary for individuals to adapt to new environments. Eventually, only memories that are of significance are transformed from short-term memory into long-term memory through repeated stimulation. In this study, we show experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems. By stimulating the memristor with repeated voltage pulses, we observe an effect analogous to memory transition in biological systems with much improved retention time accompanied by additional structural changes in the memristor. We verify that not only the shape or the total number of stimuli is i...
810 citations
TL;DR: Sub-nanosecond switching of a metal-oxide-metal memristor utilizing a broadband 20 GHz experimental setup developed to observe fast switching dynamics is reported.
Abstract: We report sub-nanosecond switching of a metal?oxide?metal memristor utilizing a broadband 20?GHz experimental setup developed to observe fast switching dynamics. Set and reset operations were successfully performed in the tantalum oxide memristor using pulses with durations of 105 and 120?ps, respectively. Reproducibility of the sub-nanosecond switching was also confirmed as the device switched over consecutive cycles.
632 citations
TL;DR: Structural and chemical analysis of the channel combined with temperature-dependent transport measurements indicate a unique resistance switching mechanism in a resistive random access memory device.
Abstract: By employing a precise method for locating and directly imaging the active switching region in a resistive random access memory (RRAM) device, a nanoscale conducting channel consisting of an amorphous Ta(O) solid solution surrounded by nearly stoichiometric Ta(2) O(5) is observed. Structural and chemical analysis of the channel combined with temperature-dependent transport measurements indicate a unique resistance switching mechanism.
387 citations
TL;DR: In this paper, a nonlinear dopant drift model was proposed that resolves boundary issues existing in previously reported models that can be easily adjusted to match the dynamics of distinct memristive elements.
Abstract: The need for reliable models that take into account the nonlinear kinetics of dopants is nowadays of paramount importance, particularly with the physical dimensions of electron devices shrinking to the deep nanoscale range and the development of emerging nanoionic systems such as the memristor. In this paper, we present a novel nonlinear dopant drift model that resolves the boundary issues existing in previously reported models that can be easily adjusted to match the dynamics of distinct memristive elements. With the aid of this model, we examine switching mechanisms, current-voltage characteristics, and the collective ion transport in two terminal memristive devices, providing new insights on memristive behavior.
379 citations
TL;DR: In this article, the memristive behavior is attributed to the migration of oxygen vacancies upon bias which modulates the interplay between Schottky barrier emission and tunneling at the WOX/electrode interface.
Abstract: Nanoscale memristive devices using tungsten oxide as the switching layer have been fabricated and characterized. The devices show the characteristics of a flux-controlled memristor such that the conductance change is governed by the history of the applied voltage signals, leading to synaptic behaviors including long-term potentiation and depression. The memristive behavior is attributed to the migration of oxygen vacancies upon bias which modulates the interplay between Schottky barrier emission and tunneling at the WOX/electrode interface. A physical model incorporating ion drift and diffusion effects using an internal state variable representing the area of the conductive region has been proposed to explain the observed memristive behaviors. A SPICE model has been further developed that can be directly incorporated into existing circuit simulators. This type of device can be fabricated with low-temperature processes and has potential applications in synaptic computations and as analog circuit components.
361 citations
TL;DR: In this paper, a memristor is used to implement programmable analog circuits, leveraging the memristors' fine-resolution programmable resistance without causing perturbations due to parasitic components.
Abstract: This paper demonstrates that memristors can be used to implement programmable analog circuits, leveraging memristor's fine-resolution programmable resistance without causing perturbations due to parasitic components. Fine-resolution programmable resistance is achieved by varying the amount of flux across memristors. The resistance programming can be achieved by controlling the input pulsewidth and its frequency. For demonstration, a memristor is designed for a pulse-programmable midband differential gain amplifier with fine resolution.
357 citations
TL;DR: A wide gamut of complex dynamic behaviors, including chaos, is observed even in a simple network of memristor oscillators, proposed here as a good candidate for the realization of oscillatory associative and dynamic memories.
Abstract: A thorough investigation of the nonlinear dynamics of networks of memristor oscillators is a key step towards the design of systems based upon them, such as neuromorphic circuits and dense nonvolatile memories. A wide gamut of complex dynamic behaviors, including chaos, is observed even in a simple network of memristor oscillators, proposed here as a good candidate for the realization of oscillatory associative and dynamic memories. A detailed study of number and stability of all periodic and nonperiodic oscillations appearing in the network may not leave aside a preliminary deep understanding of the local and global behavior of the basic oscillator. Depending on two bifurcation parameters, controlling memristor nonlinearity, the oscillator exhibits different dynamic behaviors, analyzed here through application of state-of-the-art techniques from the theory of nonlinear dynamics to the oscillator model.
308 citations
TL;DR: By starting from basicmemristor device equations, a comprehensive set of properties and design equations for memristor based memories are developed, specifically targeting key electrical memristOr device characteristics relevant to memory operations.
Abstract: Novel nonvolatile universal memory technology is essential for providing required storage for nanocomputing. As a potential contender for the next-generation memory, the recently found "the missing fourth circuit element," memristor, has drawn a great deal of research interests. In this paper, by starting from basic memristor device equations, we develop a comprehensive set of properties and design equations for memristor based memories. Our analyses are specifically targeting key electrical memristor device characteristics relevant to memory operations. Using our derived properties, we investigate the design of read and write circuits and analyze important data integrity and noise-tolerance is sues.
294 citations
TL;DR: This letter identifies significant discrepancies between the existing models and published device characterization data and proposes a new mathematical model that allows modeling of memristor-based neuromorphic systems.
Abstract: This letter proposes a new mathematical model for memristor devices. It builds on existing models and is correlated against several published device characterizations. This letter identifies significant discrepancies between the existing models and published device characterization data. The proposed model addresses these discrepancies. In particular, it allows modeling of memristor-based neuromorphic systems.
TL;DR: This paper describes the development of NOR type flexible resistive random access memory (RRAM) with a one transistor-one memristor structure (1T-1M) by integration of a high-performance single crystal silicon transistor with a titanium oxide based Memristor without any electrical interference from adjacent cells.
Abstract: The demand for flexible electronic systems such as wearable computers, E-paper, and flexible displays has recently increased due to their advantages over present rigid electronic systems. Flexible memory is an essential part of electronic systems for data processing, storage, and communication and thus a key element to realize such flexible electronic systems. Although several emerging memory technologies, including resistive switching memory, have been proposed, the cell-to-cell interference issue has to be overcome for flexible and high performance nonvolatile memory applications. This paper describes the development of NOR type flexible resistive random access memory (RRAM) with a one transistor–one memristor structure (1T-1M). By integration of a high-performance single crystal silicon transistor with a titanium oxide based memristor, random access to memory cells on flexible substrates was achieved without any electrical interference from adjacent cells. The work presented here can provide a new appr...
TL;DR: A new approach towards the design and modeling of Memory resistor (Memristor)-based CAM using a combination of memristor MOS devices to form the core of a memory/compare logic cell that forms the building block of the CAM architecture is provided.
Abstract: Large-capacity content addressable memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore's Law for a few more years. This paper provides a new approach towards the design and modeling of Memory resistor (Memristor)-based CAM (MCAM) using a combination of memristor MOS devices to form the core of a memory/compare logic cell that forms the building block of the CAM architecture. The non-volatile characteristic and the nanoscale geometry together with compatibility of the memristor with CMOS processing technology increases the packing density, provides for new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power dissipation, and has scope for speed improvement as the technology matures.
14 Mar 2011
TL;DR: This work study the memristor-based RRAM array design and focus on the choices of different peripherals to achieve the best trade-off among performance, energy, and area.
Abstract: Emerging non-volatile memory (NVM) technologies are getting mature in recent years. These emerging NVM technologies have demonstrated great potentials for the universal memory hierarchy design. Among all the technology candidates, resistive random-access memory (RRAM) is considered to be the most promising as it operates faster than phase-change memory (PCRAM), and it has simpler and smaller cell structure than magnetic memory (MRAM or STT-RAM). In contrast to a conventional MOS-accessed memory cell, memristor-based RRAM has the potential of forming a cross-point structure without using access devices, achieving ultra high density. The cross-point structure, however, brings extra challenges to the peripheral circuitry design. In this work, we study the memristor-based RRAM array design and focus on the choices of different peripherals to achieve the best trade-off among performance, energy, and area. In addition, a system-level model is built to estimate the performance, energy, and area values1.
TL;DR: A behavior model of a memristive soild-state device for simulation with a simulation program for integrated circuits emphasis (SPICE) compatible circuit simulator and a magnetic flux controlled memristor model.
Abstract: This paper introduces a behavior model of a memristive soild-state device for simulation with a simulation program for integrated circuits emphasis (SPICE) compatible circuit simulator. After showing the underlying functional mechanics and model equations of a memristor the SPICE equivalent circuit based on a charge controlled memristor is presented and discussed. Hereafter, a magnetic flux controlled memristor model is introduced including technical description and SPICE implementation. It is shown that the presented SPICE models meet the requirements for simulations of multi memristor circuits.
15 May 2011
TL;DR: A SPICE model for the titanium dioxide memristor device is presented from its modeling equations as described in [1] and the SPICE simulations to the experimental data are compared.
Abstract: In this paper we present a SPICE model for the titanium dioxide memristor device from its modeling equations as described in [1] and compare the SPICE simulations to the experimental data.
TL;DR: A new class of electrically functional devices composed entirely of soft, liquid-based materials that display memristor-like characteristics is presented, which may become the core of next generation memory devices because of their low energy consumption and high data density and performance.
Abstract: IO N We present a new class of electrically functional devices composed entirely of soft, liquid-based materials that display memristor-like characteristics. A memristor, or a “memory resistor”, is an electronic device that changes its resistive state depending on the current or voltage history through the device. Memristors may become the core of next generation memory devices because of their low energy consumption and high data density and performance. [ 1–3 ] Since the concept of memristors was theorized in 1971, [ 4 ] resistive switching memories have been fabricated from a variety of materials operating on magnetic, [ 5 ] thermal, [ 6 ] photonic, [ 7 ] electronic and ionic mechanisms. [ 3 , 8 , 9 ] Conventional memristive devices typically include metalinsulator-metal (M-I-M) junctions composed of rigid stacks of fi lms fabricated by multiple vacuum-deposition steps, often at high temperature. The most common “insulator” materials in M-I-M memristor junctions are inorganic metal oxides such as TiO 2 [ 10 ] and NiO. [ 11 ] Conducting pathways can form by current through such layers. Solid electrolytes between metal electrodes can also be used to create resistance switches (e.g., Ag/ Ag 2 S/Pt), in which conductive metal fi laments that bridge the two electrodes can be formed or annihilated on demand. [ 3 , 9 ] Memristive circuits composed of organic materials have some advantages over conventional metal oxides due to their ease of processing, light weight, and low cost. A variety of organic materials such as homogeneous polymers, small-molecule or nanoparticle doped polymers, and organic donor-acceptor complexes have been evaluated as components in memory switching devices. [ 12 ] We report new controllably bi-stable memristor-like devices fabricated entirely from liquid-based materials. These soft and fl exible devices are built from liquid metal and hydrogels that are used routinely in laboratories for hosting biological molecules and supporting cell growth. Hydrogels are soft, moldable and bio-compatible media similar to biological systems with high ion mobility due to the high water content ( > 90% water). [ 13 , 14 ] The ionic properties of the gels can be tuned by inclusion of polyelectrolytes that are immobilized via entanglement within the gel network. Hydrogels doped with polyelectrolytes have been utilized for fabricating electronic devices such as diodes and photovoltaic cells. [ 13 , 15 , 16 ] The electrodes of these devices, however, are rigid metals such as platinum and
TL;DR: A delay-dependent feedback controller is derived to achieve the exponential synchronization based on the drive-response concept, linear matrix inequalities (LMIs) and Lyapunov functional method.
TL;DR: Some novel transient transition behaviors with different time scales are found in the memristor circuit, both theoretically and numerically.
Abstract: A simple memristor-based chaotic circuit with an active flux-controlled memristor characterized by a smooth continuous cubic nonlinearity is designed. The proposed chaotic circuit can generate a 2-scroll chaotic attractor on a finite time scale and has an equilibrium set with its stability dependent on the initial state of the memristor. The complex dynamics of the proposed chaotic circuit under different initial state of the memristor are investigated both theoretically and numerically. In particular, some novel transient transition behaviors with different time scales are found in the memristor circuit. Experimental observations based on a universal circuit implementation platform are conducted to partially verify the numerical simulation results.
08 Jun 2011
TL;DR: This paper introduces a novel FPGA architecture with memristor-based reconfiguration (mrFPGA), based on the existing CMOS-compatible Memristor fabrication process, and proposes an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup.
Abstract: In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration (mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D die-stacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional FPGAs, the positions of inserted buffers in mrFPGA are optimized on demand. A complete CAD flow is provided for mrFPGA, with an advanced P&R tool named mrVPR that was developed for mrFPGA. The tool can deal with the novel routing structure of mrFPGA, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrFPGA based on the 20 largest MCNC benchmark circuits. Results show that mrFPGA achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrFPGA.
09 Oct 2011
TL;DR: The design and behavior of a memristive-based logic gate - an IMPLY gate - are presented and design issues such as the tradeoff between speed (fast write times) and correct logic behavior are described, as part of an overall design methodology.
Abstract: Memristors can be used as logic gates. No design methodology exists, however, for memristor-based combinatorial logic. In this paper, the design and behavior of a memristive-based logic gate - an IMPLY gate - are presented and design issues such as the tradeoff between speed (fast write times) and correct logic behavior are described, as part of an overall design methodology. A memristor model is described for determining the write time and state drift. It is shown that the widely used memristor model - a linear ion drift memristor - is impractical for characterizing an IMPLY logic gate, and a different memristor model is necessary such as a memristor with a current threshold.
TL;DR: This work reported direct observations in all three dimensions of the internal structure of titanium oxide memristors, resolving a single conducting channel that is made up of a reduced phase of the as-deposited titanium oxide.
Abstract: Memristors are memory resistors promising a rapid integration into future memory technologies. However, progress is still critically limited by a lack of understanding of the physical processes occurring at the nanoscale. Here we correlate device electrical characteristics with local atomic structure, chemistry and temperature. We resolved a single conducting channel that is made up of a reduced phase of the as-deposited titanium oxide. Moreover, we observed sufficient Joule heating to induce a crystallization of the oxide surrounding the channel, with a peculiar pattern that finite element simulations correlated with the existence of a hot spot close to the bottom electrode, thus identifying the switching location. This work reports direct observations in all three dimensions of the internal structure of titanium oxide memristors.
TL;DR: In this paper, a systematic study of chaotic behavior in memristor based chaotic circuits is performed with the help of nonlinear tools such as bifurcation diagrams, power spectrum analysis, and Lyapunov exponents.
Abstract: After the successful solid state implementation of memristors, a lot of attention has been drawn to the study of memristor based chaotic circuits. In this paper, a systematic study of chaotic behavior in such system is performed with the help of nonlinear tools such as bifurcation diagrams, power spectrum analysis, and Lyapunov exponents. In particular, a Twin-T notch filter feedback controller is designed and employed to control the chaotic behavior in the memristor based chaotic circuit. Both simulation and experiment results validate the proposed control method.
TL;DR: In this article, a practical equivalent circuit of an active flux-controlled memristor characterized by smooth piecewise-quadratic nonlinearity is designed and an experimental chaotic memristive circuit is implemented.
Abstract: In this paper, a practical equivalent circuit of an active flux-controlled memristor characterized by smooth piecewise-quadratic nonlinearity is designed and an experimental chaotic memristive circuit is implemented. The chaotic memristive circuit has an equilibrium set and its stability is dependent on the initial state of the memristor. The initial state-dependent and the circuit parameter-dependent dynamics of the chaotic memristive circuit are investigated via phase portraits, bifurcation diagrams and Lyapunov exponents. Both experimental and simulation results validate the proposed equivalent circuit realization of the active flux-controlled memristor.
TL;DR: Circuit realisations of emulators transforming memristive devices into effective floating memcapacitive and meminductive systems are suggested.
Abstract: Suggested are circuit realisations of emulators transforming memristive devices into effective floating memcapacitive and meminductive systems. The emulator's circuits are based on second generation current conveyors and involve either four single-output or two dual-output current conveyors. The equations governing the resulting memcapactive and meminductive systems are presented.
25 Jan 2011
TL;DR: The recent progress on the development of two-terminal resistive devices (memristors) is reviewed and devices with incremental resistance changes have been demonstrated and can be used to emulate synaptic functions in hardware based neuromorphic circuits.
Abstract: We review the recent progress on the development of two-terminal resistive devices (memristors). Devices based on solid-state electrolytes (e.g. a-Si) have been shown to possess a number of promising performance metrics such as yield, on/off ratio, switching speed, endurance and retention suitable for memory or reconfigurable circuit applications. In addition, devices with incremental resistance changes have been demonstrated and can be used to emulate synaptic functions in hardware based neuromorphic circuits. Device and SPICE modeling based on a properly chosen internal state variable have been carried out and will be useful for large-scale circuit simulations.
TL;DR: This paper proposes a new and simple method for performing analog arithmetic operations which in this scheme, signals are represented and stored through a memristance of the newly found circuit element, i.e. memristor, instead of voltage or current.
TL;DR: A closed-loop switching protocol is designed that dramatically narrows the time distribution, which can significantly improve memory circuit performance and reliability and proposed a simple analytical model based on the drift/diffusion equation and previously measured nonlinear drift behavior.
Abstract: We measured the switching time statistics for a TiO2 memristor and found that they followed a lognormal distribution, which is a potentially serious problem for computer memory and data storage applications. We examined the underlying physical phenomena that determine the switching statistics and proposed a simple analytical model for the distribution based on the drift/diffusion equation and previously measured nonlinear drift behavior. We designed a closed-loop switching protocol that dramatically narrows the time distribution, which can significantly improve memory circuit performance and reliability.
TL;DR: Sustained oscillation is reported for all types though oscillating resistance and time dependent poles are present and an analytical model is proposed to estimate the desired amplitude of oscillation before the oscillation starts.
08 Jun 2011
TL;DR: A neural learning method to implement Boolean functions in memristor NLB is described and its high robustness against most important device defects and variations, like static defects and Memristor voltage threshold variability is demonstrated.
Abstract: Neural networks are considered as promising candidates for implementing functions in memristor crossbar array with high tolerance to device defects and variations. Based on such arrays, Neural Logic Blocks (NLB) with learning capability can be built to replace Configurable Logic Block (CLB) in programmable logic circuits. In this article, we describe a neural learning method to implement Boolean functions in memristor NLB. By using Monte-Carlo simulation, we demonstrate its high robustness against most important device defects and variations, like static defects and memristor voltage threshold variability.