Showing papers on "Memristor published in 2012"

A ferroelectric memristor

Abstract: Memristors are devices whose dynamic properties are of interest because they can mimic the operation of biological synapses. The demonstration that ferroelectric domains in tunnel junctions behave like memristors suggests new approaches for designing neuromorphic circuits.

A Functional Hybrid Memristor Crossbar-Array/CMOS System for Data Storage and Neuromorphic Applications

Abstract: Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme.

Synaptic Learning and Memory Functions Achieved Using Oxygen Ion Migration/Diffusion in an Amorphous InGaZnO Memristor

Abstract: A single synaptic device with inherent learning and memory functions is demonstrated based on an amorphous InGaZnO (α-IGZO) memristor; several essential synaptic functions are simultaneously achieved in such a single device, including nonlinear transmission characteristics, spike-rate-dependent and spike-timing-dependent plasticity, long-term/short-term plasticity (LSP and STP) and “learning-experience” behavior. These characteristics bear striking resemblances to certain learning and memory functions of biological systems. Especially, a “learning-experience” function is obtained for the first time, which is thought to be related to the metastable local structures in α-IGZO. These functions are interrelated: frequent stimulation can cause an enhancement of LTP, both spike-rate-dependent and spike-timing-dependent plasticity is the same on this point; and, the STP-to-LTP transition can occur through repeated “stimulation” training. The physical mechanism of device operation, which does not strictly follow the memristor model, is attributed to oxygen ion migration/diffusion. A correlation between short-term memory and ion diffusion is established by studying the temperature dependence of the relaxation processes of STP and ion diffusion. The realization of important synaptic functions and the establishment of a dynamic model would promote more accurate modeling of the synapse for artificial neural network.

Anatomy of a Nanoscale Conduction Channel Reveals the Mechanism of a High-Performance Memristor

Abstract: By employing a precise method for locating and directly imaging the active switching region in a resistive random access memory (RRAM) device, a nanoscale conducting channel consisting of an amorphous Ta(O) solid solution surrounded by nearly stoichiometric Ta(2) O(5) is observed. Structural and chemical analysis of the channel combined with temperature-dependent transport measurements indicate a unique resistance switching mechanism.

Memristor Emulator for Memristor Circuit Applications

Abstract: A memristor emulator which imitates the behavior of a TiO2 memristor is presented. Our emulator is built from off-the-shelf solid state components. To develop real world memristor circuit applications, the emulator can be used for breadboard experiments in real time. Two or more memristor emulators can be connected in serial, in parallel, or in hybrid (serial and parallel combined) with identical or opposite polarities. With a simple change of connection, each memristor emulator can be switched between a decremental configuration or an incremental configuration. The hardware and spice simulation of the proposed emulator showed promising results that provides an alternative solution of hp TiO2 memristor model in real circuit.

Neural Synaptic Weighting With a Pulse-Based Memristor Circuit

Abstract: A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law (). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear memristor and window-based nonlinear memristor models.

Memristor Bridge Synapse-Based Neural Network and Its Learning

Abstract: Analog hardware architecture of a memristor bridge synapse-based multilayer neural network and its learning scheme is proposed. The use of memristor bridge synapse in the proposed architecture solves one of the major problems, regarding nonvolatile weight storage in analog neural network implementations. To compensate for the spatial nonuniformity and nonideal response of the memristor bridge synapse, a modified chip-in-the-loop learning scheme suitable for the proposed neural network architecture is also proposed. In the proposed method, the initial learning is conducted in software, and the behavior of the software-trained network is learned by the hardware network by learning each of the single-layered neurons of the network independently. The forward calculation of the single-layered neuron learning is implemented on circuit hardware, and followed by a weight updating phase assisted by a host computer. Unlike conventional chip-in-the-loop learning, the need for the readout of synaptic weights for calculating weight updates in each epoch is eliminated by virtue of the memristor bridge synapse and the proposed learning scheme. The hardware architecture along with the successful implementation of proposed learning on a three-bit parity network, and on a car detection network is also presented.

Ferroelectric tunnel memristor.

Abstract: Strong interest in resistive switching phenomena is driven by a possibility to develop electronic devices with novel functional properties not available in conventional systems. Bistable resistive devices are characterized by two resistance states that can be switched by an external voltage. Recently, memristors—electric circuit elements with continuously tunable resistive behavior—have emerged as a new paradigm for nonvolatile memories and adaptive electronic circuit elements. Employment of memristors can radically enhance the computational power and energy efficiency of electronic systems. Most of the existing memristor prototypes involve transition metal oxide resistive layers where conductive filaments formation and/or the interface contact resistance control the memristive behavior. In this paper, we demonstrate a new type of memristor that is based on a ferroelectric tunnel junction, where the tunneling conductance can be tuned in an analogous manner by several orders of magnitude by both the amplit...

Memristor Bridge Synapses

Abstract: In this paper, we propose a memristor bridge circuit consisting of four identical memristors that is able to perform zero, negative, and positive synaptic weightings. Together with three additional transistors, the memristor bridge weighting circuit is able to perform synaptic operation for neural cells. It is compact as both weighting and weight programming are performed in a memristor bridge synapse. It is power efficient, since the operation is based on pulsed input signals. Its input terminals are utilized commonly for applying both weight programming and weight processing signals via time sharing. In this paper, features of the memristor bridge synapses are investigated using the TiO memristor model via simulations.

Neuromorphic, Digital, and Quantum Computation With Memory Circuit Elements

Abstract: Memory effects are ubiquitous in nature and the class of memory circuit elements - which includes memristive, memcapacitive, and meminductive systems - shows great potential to understand and simulate the associated physical processes. Here, we show that such elements can also be used in electronic schemes mimicking biologically inspired computer architectures, performing digital logic and arithmetic operations, and can expand the capabilities of certain quantum computation schemes. In particular, we will discuss some examples where the concept of memory elements is relevant to the realization of associative memory in neuronal circuits, spike-timing-dependent plasticity (STDP) of synapses, and digital and field-programmable quantum computing.

A chaotic circuit based on Hewlett-Packard memristor.

Abstract: Memristors are gaining increasing attention as next generation electronic devices. They are also becoming commonly used as fundamental blocks for building chaotic circuits, although often arbitrary (typically piece-wise linear or cubic) flux-charge characteristics are assumed. In this paper, a chaotic circuit based on the mathematical realistic model of the HP memristor is introduced. The circuit makes use of two HP memristors in antiparallel. Numerical results showing some of the chaotic attractors generated by this circuit and the behavior with respect to changes in its component values are described.

Engineering nonlinearity into memristors for passive crossbar applications

Abstract: Although TaOx memristors have demonstrated encouraging write/erase endurance and nanosecond switching speeds, the linear current-voltage (I-V) characteristic in the low resistance state limits their applications in large passive crossbar arrays. We demonstrate here that a TiO2-x/TaOx oxide heterostructure incorporated into a 50 nm× 50 nm memristor displays a very large nonlinearity such that I(V/2) ≈ I(V)/100 for V ≈ 1 volt, which is caused by current-controlled negative differential resistance in the device.

Hardware realization of BSB recall function using memristor crossbar arrays

Abstract: The Brain-State-in-a-Box (BSB) model is an auto-associative neural network that has been widely used in optical character recognition and image processing. Traditionally, the BSB model was realized at software level and carried out on high-performance computing clusters. To improve computation efficiency and reduce resources requirement, we propose a hardware realization by utilizing memristor crossbar arrays. In this work, we explore the potential of a memristor crossbar array as an auto-associative memory. More specificly, the recall function of a multi-answer character recognition based on BSB model was realized. The robustness of the proposed BSB circuit was analyzed and evaluated based on massive Monte-Carlo simulations, considering input defects, process variations, and electrical fluctuations. The physical constrains when implementing a neural network with memristor crossbar array have also been discussed. Our results show that the BSB circuit has a high tolerance to random noise. Comparably, the correlations between memristor arrays introduces directional noise and hence dominates the quality of circuits.

CMOS and Memristor-Based Neural Network Design for Position Detection

Abstract: Most hardware neural networks have a basic competitive learning rule on top of a more involved processing algorithm. This work highlights two basic learning rules/behavior: winner-take-all (WTA) and spike-timing-dependent plasticity (STDP). It also gives a design example implementing WTA combined with STDP in a position detector. A complementary metal-oxide-semiconductor (CMOS) and a memristor-MOS technology (MMOST) design simulation results are compared on the bases of power, area, and noise handling capabilities. Design and layout were done in 130-nm IBM process for CMOS, and the HSPICE model files for the process were used to simulate the CMOS part of the MMOST design. CMOS consumes area, 55-W max power, and requires a 3-dB SNR. On the other hand, the MMOST design consumes , 15-W max power, and requires a 4.8-dB SNR. There is a potential to improve upon analog computing with the adoption of MMOST designs.

A Boundary Condition-Based Approach to the Modeling of Memristor Nanostructures

Abstract: A deep theoretical discussion proves that in Joglekar's and Biolek's models the memductance-flux relation of a memristor driven by a sign-varying voltage source may only exhibit single-valuedness and multi-valuedness respectively. This manuscript derives a novel boundary condition-based Model for memristor nanostructures. Unlike previous models, the proposed one allows for closed-form solutions. More importantly, subject to the nonlinear behavior under exam, this model enables a suitable tuning of boundary conditions, which may result in the detection of both single-valued and multi-valued memductance-flux relations under certain sign-varying inputs of interest. The large class of modeled dynamics include all behaviors reported in the legendary paper revealing the existence of memory-resistance at the nano scale.

Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications

Abstract: Many mobile SoC chips employ a “two-macro” approach including volatile and nonvolatile memory macros (i.e. SRAM and Flash), to achieve high-performance or low-voltage power-on operation with the capability of power-off nonvolatile data storage. However, the two-macro approach suffers from slow store/restore speeds due to word-by-word serial transfer of data between the volatile and nonvolatile memories. Slow store/restore speeds require long power-on/off time and leave the device vulnerable to sudden power failure . This study proposes a resistive memory (memristor) based nonvolatile SRAM (or memristor latch) cell to achieve fast bit-to-bit parallel store/restore operations, low store/restore energy consumption, and a compact cell area. This resistive nonvolatile 8T2R (Rnv8T) cell includes two fast-write memristor (RRAM) devices vertical-stacked over the 8T, and a novel 2T memristor-switch, which provides both memristor control and SRAM write-assist functions. The write assist feature enables the Rnv8T cell to use read favored transistor sizing to prevent read/write failure at lower VDDs. We also fabricated the first macro-level memristor-based (or RRAM-based) nonvolatile SRAM. This 16 Kb Rnv8T macro achieved the lowest store energy and R/W VDDmin (0.45 V) of any nonvolatile SRAM or two-macro solution.

Continuous Electrical Tuning of the Chemical Composition of TaOx-Based Memristors

Abstract: TaOx-based memristors have recently demonstrated both subnanosecond resistance switching speeds and very high write/erase switching endurance. Here we show that the physical state variable that enables these properties is the oxygen concentration in a conduction channel, based on the measurement of the thermal coefficient of resistance of different TaOx memristor states and a set of reference Ta–O films of known composition. The continuous electrical tunability of the oxygen concentration in the channel, with a resolution of a few percent, was demonstrated by controlling the write currents with a one transistor-one memristor (1T1M) circuit. This study demonstrates that solid-state chemical kinetics is important for the determination of the electrical characteristics of this relatively new class of device.

On the simplest fractional-order memristor-based chaotic system

Abstract: In 1695, G. Leibniz laid the foundations of fractional calculus, but mathematicians revived it only 300 years later. In 1971, L.O. Chua postulated the existence of a fourth circuit element, called memristor, but Williams’s group of HP Labs realized it only 37 years later. By looking at these interdisciplinary and promising research areas, in this paper, a novel fractional-order system including a memristor is introduced. In particular, chaotic behaviors in the simplest fractional-order memristor-based system are shown. Numerical integrations (via a predictor–corrector method) and stability analysis of the system equilibria are carried out, with the aim to show that chaos can be found when the order of the derivative is 0.965. Finally, the presence of chaos is confirmed by the application of the recently introduced 0-1 test.

Neural Learning Circuits Utilizing Nano-Crystalline Silicon Transistors and Memristors

Abstract: Properties of neural circuits are demonstrated via SPICE simulations and their applications are discussed. The neuron and synapse subcircuits include ambipolar nano-crystalline silicon transistor and memristor device models based on measured data. Neuron circuit characteristics and the Hebbian synaptic learning rule are shown to be similar to biology. Changes in the average firing rate learning rule depending on various circuit parameters are also presented. The subcircuits are then connected into larger neural networks that demonstrate fundamental properties including associative learning and pulse coincidence detection. Learned extraction of a fundamental frequency component from noisy inputs is demonstrated. It is then shown that if the fundamental sinusoid of one neuron input is out of phase with the rest, its synaptic connection changes differently than the others. Such behavior indicates that the system can learn to detect which signals are important in the general population, and that there is a spike-timing-dependent component of the learning mechanism. Finally, future circuit design and considerations are discussed, including requirements for the memristive device.

Memristive Device Fundamentals and Modeling: Applications to Circuits and Systems Simulation

Abstract: The nonvolatile memory property of a memristor enables the realization of new methods for a variety of computational engines ranging from innovative memristive-based neuromorphic circuitry through to advanced memory applications. The nanometer-scale feature of the device creates a new opportunity for realization of innovative circuits that in some cases are not possible or have inefficient realization in the present and established design domain. The nature of the boundary, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces challenges in modeling, characterization, and simulation of future circuits and systems. Here, a deeper insight is gained in understanding the device operation, leading to the development of practical models that can be implemented in current computer-aided design (CAD) tools.

A Novel Design and Modeling Paradigm for Memristor-Based Crossbar Circuits

Abstract: Over 30 years ago L. Chua proposed the existence of a new class of passive circuit elements, which he called memristors and memristive devices. The unique electrical characteristics associated with them, along with the advantages of crossbar structures, have the potential to revolutionize computing architectures. A well-defined and effective memristor model for circuit design combined with a design paradigm based on well-understood underlying logic design principles would certainly accelerate research on nanoscale circuits and systems. Toward this goal, we propose a memristor crossbar circuit design paradigm in which memristors are modeled using the quantum mechanical phenomenon of tunneling. We use this circuit model to design and simulate various logic circuit designs capable of universal computation. Finally, we develop and present a new design paradigm for memristor-based crossbar circuits.

Memristor-based reservoir computing

Abstract: As feature-size scaling and "Moore's Law" in integrated CMOS circuits further slows down, attention is shifting to computing by non-von Neumann and non-Boolean computing models. Reservoir computing (RC) is a new computing paradigm that allows to harness the intrinsic dynamics of a "reservoir" to perform useful computations. The reservoir, or compute core, must only provide sufficiently rich dynamics that are then mapped onto a low-dimensional space by an readout layer. One of the key advantages of this approach is that only the readout layer needs to be adapted to perform the desired computation. The reservoir itself remains unchanged. In this paper we use for the first time memristive components as reservoir building blocks that are assembled into device networks. Memristive components are particularly interesting for this purpose because of their non-linear and memory characteristics. In addition, they can be integrated very densely and provide rich dynamics with a few components only. We use pattern recognition and associative memory tasks to illustrate the memristive reservoir computing approach. For that purpose, we have built a software framework that allows to create valid memristor networks, to simulate and evaluate them in Ngspice, and to train the readout layer by means of a Genetic Algorithm (GA). Our results show that we can efficiently and robustly classify temporal patterns. The approach presents a promising new computing paradigm that harnesses the non-linear, time-dependent, and highly-variable properties of current memristive components for solving computational tasks.

Hyperchaos in a memristor-based modified canonical chua's circuit

Abstract: After the successful solid state implementation of the memristor, memristor-based circuits have received a lot of attention. In this paper, a memristor with cubic nonlinear characteristics is employed in the modified canonical Chua's circuit. A systematic study of hyperchaotic behavior in this circuit is performed with the help of nonlinear tools such as Lyapunov exponents, phase portraits and bifurcation diagrams. In particular, an imitative memristor circuit is examined to reveal the construction of hyperchaotic attractors.

Electrically tailored resistance switching in silicon oxide.

Abstract: Resistive switching in a metal-free silicon-based material offers a compelling alternative to existing metal oxide-based resistive RAM (ReRAM) devices, both in terms of ease of fabrication and of enhanced device performance. We report a study of resistive switching in devices consisting of non-stoichiometric silicon-rich silicon dioxide thin films. Our devices exhibit multi-level switching and analogue modulation of resistance as well as standard two-level switching. We demonstrate different operational modes that make it possible to dynamically adjust device properties, in particular two highly desirable properties: nonlinearity and self-rectification. This can potentially enable high levels of device integration in passive crossbar arrays without causing the problem of leakage currents in common line semi-selected devices. Aspects of conduction and switching mechanisms are discussed, and scanning tunnelling microscopy (STM) measurements provide a more detailed insight into both the location and the dimensions of the conductive filaments.

Nano-PPUF: A Memristor-Based Security Primitive

Abstract: CMOS devices have been used to build hardware security primitives such as physical unclonable functions. Since MOS devices are relatively easy to model and simulate, CMOS-based security primitives are increasingly prone to modeling attacks. We propose memristor-based Public Physical Unclonable Functions (nano-PPUFs), they have complex models that are difficult to simulate. We leverage sneak path currents, process variations, and computationally intensive SPICE models as features to build the nano-PPUF. With just a few hundreds of memristors, we construct a time-bounded authentication protocol that will take several years for an attacker to compromise.

Memristor model and its application for chaos generation

Abstract: This paper contributes to the understanding of memristor operation and its possible application fields through: (a) derivation of a complete mathematical model for the HP memristor which takes into consideration the inter-dependence between memristance, charge and flux along with the boundary and initial conditions of operation; (b) an introduction of detailed charge- and flux-controlled SPICE memristor models realizing the proposed mathematical memristor model; (c) The incorporation of the memristor model in the SPICE realization of a third-order chaotic system where a single HP memristor acts as the nonlinear part of the system. Simulation results are provided to validate the mathematical model and the synthesis and operation of the third-order chaotic system.