Showing papers on "Memristor published in 2013"

TEAM: ThrEshold Adaptive Memristor Model

Abstract: Memristive devices are novel devices, which can be used in applications ranging from memory and logic to neuromorphic systems. A memristive device offers several advantages: nonvolatility, good scalability, effectively no leakage current, and compatibility with CMOS technology, both electrically and in terms of manufacturing. Several models for memristive devices have been developed and are discussed in this paper. Digital applications such as memory and logic require a model that is highly nonlinear, simple for calculations, and sufficiently accurate. In this paper, a new memristive device model is presented-TEAM, ThrEshold Adaptive Memristor model. This model is flexible and can be fit to any practical memristive device. Previously published models are compared in this paper to the proposed TEAM model. It is shown that the proposed model is reasonably accurate and computationally efficient, and is more appropriate for circuit simulation than previously published models.

Integration of nanoscale memristor synapses in neuromorphic computing architectures

Abstract: Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic computing approaches that can best exploit the properties of memristor and scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault tolerant by design.

Nanobatteries in redox-based resistive switches require extension of memristor theory

Abstract: Redox-based nanoionic resistive memory cells are one of the most promising emerging nanodevices for future information technology with applications for memory, logic and neuromorphic computing. Recently, the serendipitous discovery of the link between redox-based nanoionic-resistive memory cells and memristors and memristive devices has further intensified the research in this field. Here we show on both a theoretical and an experimental level that nanoionic-type memristive elements are inherently controlled by non-equilibrium states resulting in a nanobattery. As a result, the memristor theory must be extended to fit the observed non-zero-crossing I-V characteristics. The initial electromotive force of the nanobattery depends on the chemistry and the transport properties of the materials system but can also be introduced during redox-based nanoionic-resistive memory cell operations. The emf has a strong impact on the dynamic behaviour of nanoscale memories, and thus, its control is one of the key factors for future device development and accurate modelling.

Three Fingerprints of Memristor

Abstract: This paper illustrates that for a device to be a memristor it should exhibit three characteristic fingerprints: 1) When driven by a bipolar periodic signal the device must exhibit a “pinched hysteresis loop” in the voltage-current plane, assuming the response is periodic. 2) Starting from some critical frequency, the hysteresis lobe area should decrease monotonically as the excitation frequency increases, and 3) the pinched hysteresis loop should shrink to a single-valued function when the frequency tends to infinity. Examples of memristors exhibiting these three fingerprints, along with non-memristors exhibiting only a subset of these fingerprints are also presented. In addition, two different types of pinched hysteresis loops; the transversal (self-crossing) and the non-transversal (tangential) loops exhibited by memristors are also discussed with its identification criterion.

STDP and STDP variations with memristors for spiking neuromorphic learning systems.

Abstract: In this paper we review several ways of realizing asynchronous Spike-Timing-Dependent-Plasticity (STDP) using memristors as synapses. Our focus is on how to use individual memristors to implement synaptic weight multiplications, in a way such that it is not necessary to (a) introduce global synchronization and (b) to separate memristor learning phases from memristor performing phases. In the approaches described, neurons fire spikes asynchronously when they wish and memristive synapses perform computation and learn at their own pace, as it happens in biological neural systems. We distinguish between two different memristor physics, depending on whether they respond to the original “moving wall” or to the “filament creation and annihilation” models. Independent of the memristor physics, we discuss two different types of STDP rules that can be implemented with memristors: either the pure timing-based rule that takes into account the arrival time of the spikes from the pre- and the post-synaptic neurons, or a hybrid rule that takes into account only the timing of pre-synaptic spikes and the membrane potential and other state variables of the post-synaptic neuron. We show how to implement these rules in cross-bar architectures that comprise massive arrays of memristors, and we discuss applications for artificial vision.

Ultrafast Synaptic Events in a Chalcogenide Memristor

Abstract: Compact and power-efficient plastic electronic synapses are of fundamental importance to overcoming the bottlenecks of developing a neuromorphic chip. Memristor is a strong contender among the various electronic synapses in existence today. However, the speeds of synaptic events are relatively slow in most attempts at emulating synapses due to the material-related mechanism. Here we revealed the intrinsic memristance of stoichiometric crystalline Ge2Sb2Te5 that originates from the charge trapping and releasing by the defects. The device resistance states, representing synaptic weights, were precisely modulated by 30 ns potentiating/depressing electrical pulses. We demonstrated four spike-timing-dependent plasticity (STDP) forms by applying programmed pre- and postsynaptic spiking pulse pairs in different time windows ranging from 50 ms down to 500 ns, the latter of which is 105 times faster than the speed of STDP in human brain. This study provides new opportunities for building ultrafast neuromorphic computing systems and surpassing Von Neumann architecture.

Stochastic memristive devices for computing and neuromorphic applications

Abstract: Nanoscale resistive switching devices (memristive devices or memristors) have been studied for a number of applications ranging from non-volatile memory, logic to neuromorphic systems. However a major challenge is to address the potentially large variations in space and time in these nanoscale devices. Here we show that in metal-filament based memristive devices the switching can be fully stochastic. While individual switching events are random, the distribution and probability of switching can be well predicted and controlled. Rather than trying to force high switching probabilities using excess voltage or time, the inherent stochastic nature of resistive switching allows these binary devices to be used as building blocks for novel error-tolerant computing schemes such as stochastic computing and provides the needed “analog” feature for neuromorphic applications. To verify such potential, we demonstrated memristor-based stochastic bitstreams in both time and space domains, and show that an array of binary memristors can act as a multi-level “analog” device for neuromorphic applications.

Nanoscale resistive switching devices: mechanisms and modeling

Abstract: Resistive switching devices (also termed memristive devices or memristors) are two-terminal nonlinear dynamic electronic devices that can have broad applications in the fields of nonvolatile memory, reconfigurable logic, analog circuits, and neuromorphic computing. Current rapid advances in memristive devices in turn demand better understanding of the switching mechanism and the development of physics-based as well as simplified device models to guide future device designs and circuit-level applications. In this article, we review the physical processes behind resistive switching (memristive) phenomena and discuss the experimental and modeling efforts to explain these effects. In this article three categories of devices, in which the resistive switching effects are driven by cation migration, anion migration, and electronic effects, will be discussed. The fundamental driving forces and the stochastic nature of resistive switching will also be discussed.

Synaptic plasticity and learning behaviours mimicked through Ag interface movement in an Ag/conducting polymer/Ta memristive system

Abstract: In this study, a memristor with the simple structure Ag/poly(3,4-ethylenedioxythiophene):poly (styrenesulphonate) (PEDOT:PSS)/Ta was fabricated. Essential synaptic plasticity and learning behaviours were emulated using this memristor, including short-term plasticity, long-term plasticity, spike-timing-dependent plasticity and spike-rate-dependent plasticity. Important time constants were extracted from these synaptic modifications, which are associated with brain learning and memory functions. It was clearly demonstrated that the movement of the Ag interface upon the initiation of a redox reaction accounts for the resistive switching mechanism of our memristor. The conducting path in the polymer layer and the elastic effect of the polymer matrix were suggested to be considered in the memory and learning processes. Moreover, the energy band diagram of our memristor was drawn after the cross-sectional transmission electron microscopy images were analysed. It was found that a natural p–n junction in the PEDOT:PSS/Ta compound was formed. This resulted in rectifying, high resistance and low power consumption. Our device structure may be considered a feasible prototype for integrating memristors into a large-scale neuromorphic circuit.

Compound synchronization of four memristor chaotic oscillator systems and secure communication

Abstract: In this paper, a novel kind of compound synchronization among four chaotic systems is investigated, where the drive systems have been conceptually divided into two categories: scaling drive systems and base drive systems. Firstly, a sufficient condition is obtained to ensure compound synchronization among four memristor chaotic oscillator systems based on the adaptive technique. Secondly, a secure communication scheme via adaptive compound synchronization of four memristor chaotic oscillator systems is presented. The corresponding theoretical proofs and numerical simulations are given to demonstrate the validity and feasibility of the proposed control technique. The unpredictability of scaling drive systems can additionally enhance the security of communication. The transmitted signals can be split into several parts loaded in the drive systems to improve the reliability of communication.

Generalized Memristive Device SPICE Model and its Application in Circuit Design

Abstract: This paper presents a SPICE model for memristive devices. It builds on existing models and is correlated against several published device characterization data with an average error of 6.04%. When compared to existing alternatives, the proposed model can more accurately simulate a wide range of published memristors. The model is also tested in large circuits with up to 256 memristors, and was less likely to cause convergence errors when compared to other models. We show that the model can be used to study the impact of memristive device variation within a circuit. We examine the impact of nonuniformity in device state variable dynamics and conductivity on individual memristors as well as a four memristor read/write circuit. These studies show that the model can be used to predict how variation in a memristor wafer may impact circuit performance.

Memristor, Hodgkin-Huxley, and edge of chaos.

Abstract: From a pedagogical point of view, the memristor is defined in this tutorial as any 2-terminal device obeying a state-dependent Ohm’s law. This tutorial also shows that from an experimental point of view, the memristor can be defined as any 2-terminal device that exhibits the fingerprints of “pinched” hysteresis loops in the v–i plane. It also shows that memristors endowed with a continuum of equilibrium states can be used as non-volatile analog memories. This tutorial shows that memristors span a much broader vista of complex phenomena and potential applications in many fields, including neurobiology. In particular, this tutorial presents toy memristors that can mimic the classic habituation and LTP learning phenomena. It also shows that sodium and potassium ion-channel memristors are the key to generating the action potential in the Hodgkin-Huxley equations, and that they are the key to resolving several unresolved anomalies associated with the Hodgkin-Huxley equations. This tutorial ends with an amazing new result derived from the new principle of local activity, which uncovers a minuscule life-enabling Goldilocks zone, dubbed the edge of chaos, where complex phenomena, including creativity and intelligence, may emerge. From an information processing perspective, this tutorial shows that synapses are locally-passive memristors, and that neurons are made of locally-active memristors.

Memristor Model Comparison

Abstract: Since the 2008-dated discovery of memristor behavior at the nano-scale, Hewlett Packard is credited for, a large deal of efforts have been spent in the research community to derive a suitable model able to capture the nonlinear dynamics of the nano-scale structures. Despite a considerable number of models of different complexity have been proposed in the literature, there is an ongoing debate over which model should be universally adopted for the investigation of the unique opportunities memristors may offer in integrated circuit design. In order to shed some light into this passionate discussion, this paper compares some of the most noteworthy memristor models present in the literature. The strength of the Pickett?s model stands in its experiment-based development and in its ability to describe some physical mechanism at the origin of memristor dynamics. Since its parameter values depend on the excitation of the memristor and/or on the circuit employing the memristor, it may be assumed as a reference for comparison only in those scenarios for which its parameters were reported in the literature. In this work various noteworthy memristor models are fitted to the Pickett's model under one of such scenarios. This study shows how three models, Biolek's model, the Boundary Condition Memristor model and the Threshold Adaptive Memristor model, outperform the others in the replica of the dynamics observed in the Pickett's model. In the second part of this work the models are used in a couple of basic circuits to study the variance between the dynamical behaviors they give rise to. This analysis intends to make the circuit designers aware of the different behaviors which may occur in memristor-based circuits according to the memristor model under use.

Programmable CMOS/Memristor Threshold Logic

Abstract: This paper proposes a hybrid CMOS/memristor implementation of a programmable threshold logic gate. In this gate, memristive devices implement ratioed diode-resistor logic, while CMOS circuitry is used for signal amplification and inversion. Due to the excellent scaling prospects and nonvolatile analog memory of memristive devices, the proposed threshold logic is in-field configurable and potentially very compact. The concept is experimentally verified by implementing a 4-input symmetric linear threshold gate with an integrated circuit CMOS flip-flop, silicon diodes, and Ag/a-Si/Pt memristive devices.

Logic computation in phase change materials by threshold and memory switching.

Abstract: Memristors, namely hysteretic devices capable of changing their resistance in response to applied electrical stimuli, may provide new opportunities for future memory and computation, thanks to their scalable size, low switching energy and nonvolatile nature. We have developed a functionally complete set of logic functions including NOR, NAND and NOT gates, each utilizing a single phase-change memristor (PCM) where resistance switching is due to the phase transformation of an active chalcogenide material. The logic operations are enabled by the high functionality of nanoscale phase change, featuring voltage comparison, additive crystallization and pulse-induced amorphization. The nonvolatile nature of memristive states provides the basis for developing reconfigurable hybrid logic/memory circuits featuring low-power and high-speed switching.

Ferroelectric memristor based on Pt/BiFeO3/Nb-doped SrTiO3 heterostructure

Abstract: We report a continuously tunable resistive switching behavior in Pt/BiFeO3/Nb-doped SrTiO3 heterostructure for ferroelectric memristor application. The resistance of this memristor can be tuned up to 5 × 105% by applying voltage pulses at room temperature, which exhibits excellent retention and anti-fatigue characteristics. The observed memristive behavior is attributed to the modulation effect of the ferroelectric polarization reversal on the width of depletion region and the height of potential barrier of the p-n junction formed at the BiFeO3/Nb-doped SrTiO3 interface.

Nanoscale plasmonic memristor with optical readout functionality.

Abstract: We experimentally demonstrate for the first time a nanoscale resistive random access memory (RRAM) electronic device integrated with a plasmonic waveguide providing the functionality of optical readout. The device fabrication is based on silicon on insulator CMOS compatible approach of local oxidation of silicon, which enables the realization of RRAM and low optical loss channel photonic waveguide at the same fabrication step. This plasmonic device operates at telecom wavelength of 1.55 μm and can be used to optically read the logic state of a memory by measuring two distinct levels of optical transmission. The experimental characterization of the device shows optical bistable behavior between these levels of transmission in addition to well-defined hysteresis. We attribute the changes in the optical transmission to the creation of a nanoscale absorbing and scattering metallic filament in the amorphous silicon layer, where the plasmonic mode resides.

A light incident angle switchable ZnO nanorod memristor: reversible switching behavior between two non-volatile memory devices.

Abstract: A light incident angle selectivity of a memory device is demonstrated As a model system, the ZnO resistive switching device has been selected Electrical signal is reversibly switched between memristor and resistor behaviors by modulating the light incident angle on the device Moreover, a liquid passivation layer is introduced to achieve stable and reversible exchange between the memristor and WORM behaviors

Manipulated transformation of filamentary and homogeneous resistive switching on ZnO thin film memristor with controllable multistate.

Abstract: A bias polarity-manipulated transformation from filamentary to homogeneous resistive switching was demonstrated on a Pt/ZnO thin film/Pt device. Two types of switching behaviors, exhibiting different resistive switching characteristics and memory performances were investigated in detail. The detailed transformation mechanisms are systematically proposed. By controlling different compliance currents and RESET-stop voltages, controllable multistate resistances in low resistance states and a high resistance states in the ZnO thin film metal–insulator–metal structure under the homogeneous resistive switching were demonstrated. We believe that findings would open up opportunities to explore the resistive switching mechanisms and performance memristor with multistate storage.

A Simple Model of Double-Loop Hysteresis Behavior in Memristive Elements

Abstract: This brief investigates the double-loop hysteresis behavior in memristive elements. Here, we propose a very simple dimensionless equation to model the double-loop behavior and then show how physical voltage- and current-controlled memristor models can be derived. Furthermore, we introduce the incremental/decremental positive/negative memristance/transmemristance and present circuit emulators which are capable of emulating these devices. Experimental results are given.

Emulating the paired-pulse facilitation of a biological synapse with a NiOx-based memristor

Abstract: We study the paired-pulse-induced response of a NiOx-based memristor. The behavior of the memristor is surprisingly similar to the paired-pulse facilitation of a biological synapse. When the memristor is stimulated with a pair of electrical pulses, the current of the memristor induced by the second pulse is larger than that by the first pulse. In addition, the magnitude of the facilitation decreases with the pulse interval, while it increases with the pulse magnitude or pulse width.

Memristor PUFs: a new generation of memory-based physically unclonable functions

Abstract: Memristors are emerging as a potential candidate for next-generation memory technologies, promising to deliver non-volatility at performance and density targets which were previously the domain of SRAM and DRAM. Silicon Physically Unclonable Functions (PUFs) have been introduced as a relatively new security primitive which exploit manufacturing variation resulting from the IC fabrication process to uniquely fingerprint a device instance or generate device-specific cryptographic key material. While silicon PUFs have been proposed which build on traditional memory structures, in particular SRAM, in this paper we present a memristor-based PUF which utilizes a weak-write mechanism to obtain cell behaviour which is influenced by process variation and hence usable as a PUF response. Using a model-based approach we evaluate memristor PUFs under random process variations and present results on the performance of this new PUF variant.

Sneak-path constraints in memristor crossbar arrays

Abstract: In a memristor crossbar array, a memristor is positioned on each row-column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this work, we study the sneak path problem in crossbars arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method we match a constraint on the array content that guarantees sneak-path free readout, and calculate the resulting capacity.

Atomic-level quantized reaction of HfOx memristor

Abstract: In this study, we have observed dynamic switching behaviors in a memristive device. There are only a few atoms in the resistive switching reaction which enables the high-speed resistive switching characteristics, which was analyzed dynamically by real-time analyzing tools. From fundamental conductance considerations, the resistance of the conductive path in HfOx memristor is found to be due to barriers which are atomically incremented during the RESET process. Simultaneously, we have demonstrated the quantized switching phenomena at ultra-cryogenic temperature (4 K), which are attributed to the atomic-level reaction in metallic filament.

Memristor SPICE model and crossbar simulation based on devices with nanosecond switching time

Abstract: This paper presents a memristor SPICE model that is able to reproduce current-voltage relationships of previously published memristor devices. This SPICE model shows a stronger correlation to various published device data when compared to existing SPICE models. Furthermore, switching characteristics of published memristor devices with switching times in the nanosecond scale were modeled. Therefore, this model can be used to accurately simulate neural systems based on these high-speed memristors. This paper also demonstrates how this model can be used to accurately calculate switching energy of these high-speed devices, leading to more accurate power calculations in memristor based neural systems. Memristor crossbar circuits provide a potential method for developing very high density neural classifiers. This model was able to simulate crossbar circuits containing up to 256 memristors. It is significantly less likely to cause convergence errors when operating in the nanosecond switching regime with a large number of devices when compared with existing SPICE models.

A Single‐Device Universal Logic Gate Based on a Magnetically Enhanced Memristor

Abstract: Memristors are one of the most promising candidates for future information and communications technology (ICT) architectures. Two experimental proofs of concept are presented based on the intermixing of spintronic and memristive effects into a single device, a magnetically enhanced memristor (MEM). By exploiting the interaction between the memristance and the giant magnetoresistance (GMR), a universal implication (IMP) logic gate based on a single MEM device is realized.