Showing papers on "Memristor published in 2019"

Resistance Switching Memories are Memristors.

Abstract: All 2-terminal non-volatile memory devices based on resistance switching are memristors, regardless of the device material and physical operating mechanisms. They all exhibit a distinctive “fingerprint” characterized by a pinched hysteresis loop confined to the first and the third quadrants of the v–i plane whose contour shape in general changes with both the amplitude and frequency of any periodic “sine-wave-like” input voltage source, or current source. In particular, the pinched hysteresis loop shrinks and tends to a straight line as frequency increases. Though numerous examples of voltage vs. current pinched hysteresis loops have been published in many unrelated fields, such as biology, chemistry, physics, etc., and observed from many unrelated phenomena, such as gas discharge arcs, mercury lamps, power conversion devices, earthquake conductance variations, etc., we restrict our examples in this tutorial to solid-state and/or nano devices where copious examples of published pinched hysteresis loops abound. In particular, we sampled arbitrarily, one example from each year between the years 2000 and 2010, to demonstrate that the memristor is a device that does not depend on any particular material, or physical mechanism. For example, we have shown that spin-transfer magnetic tunnel junctions are examples of memristors. We have also demonstrated that both bipolar and unipolar resistance switching devices are memristors.

A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations

Abstract: Memristors and memristor crossbar arrays have been widely studied for neuromorphic and other in-memory computing applications. To achieve optimal system performance, however, it is essential to integrate memristor crossbars with peripheral and control circuitry. Here, we report a fully functional, hybrid memristor chip in which a passive crossbar array is directly integrated with custom-designed circuits, including a full set of mixed-signal interface blocks and a digital processor for reprogrammable computing. The memristor crossbar array enables online learning and forward and backward vector-matrix operations, while the integrated interface and control circuitry allow mapping of different algorithms on chip. The system supports charge-domain operation to overcome the nonlinear I–V characteristics of memristor devices through pulse width modulation and custom analogue-to-digital converters. The integrated chip offers all the functions required for operational neuromorphic computing hardware. Accordingly, we demonstrate a perceptron network, sparse coding algorithm and principal component analysis with an integrated classification layer using the system. A programmable neuromorphic computing chip based on passive memristor crossbar arrays integrated with analogue and digital components and an on-chip processor enables the implementation of neuromorphic and machine learning algorithms.

Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension.

Abstract: The memristor1,2 is a promising building block for next-generation non-volatile memory3, artificial neural networks4-7 and bio-inspired computing systems8,9. Organizing small memristors into high-density crossbar arrays is critical to meet the ever-growing demands in high-capacity and low-energy consumption, but this is challenging because of difficulties in making highly ordered conductive nanoelectrodes. Carbon nanotubes, graphene nanoribbons and dopant nanowires have potential as electrodes for discrete nanodevices10-14, but unfortunately these are difficult to pack into ordered arrays. Transfer printing, on the other hand, is effective in generating dense electrode arrays15 but has yet to prove suitable for making fully random accessible crossbars. All the aforementioned electrodes have dramatically increased resistance at the nanoscale16-18, imposing a significant barrier to their adoption in operational circuits. Here we demonstrate memristor crossbar arrays with a 2-nm feature size and a single-layer density up to 4.5 terabits per square inch, comparable to the information density achieved using three-dimensional stacking in state-of-the-art 64-layer and multilevel 3D-NAND flash memory19. Memristors in the arrays switch with tens of nanoamperes electric current with nonlinear behaviour. The densely packed crossbar arrays of individually accessible, extremely small functional memristors provide a power-efficient solution for information storage and processing.

If It's Pinched It's a Memristor.

Abstract: This chapter consists of two parts. Part I gives a circuit-theoretic foundation for the first four elementary nonlinear 2-terminal circuit elements, namely, the resistor, the capacitor, the inductor, and the memristor. Part II consists of a collection of colorful “Vignettes” with carefully articulated text and colorful illustrations of the rudiments of the memristor and its characteristic fingerprints and signatures. It is intended as a self-contained pedagogical primer for beginners who have not heard of memristors before.

Long short-term memory networks in memristor crossbar arrays

Abstract: Recent breakthroughs in recurrent deep neural networks with long short-term memory (LSTM) units have led to major advances in artificial intelligence. However, state-of-the-art LSTM models with significantly increased complexity and a large number of parameters have a bottleneck in computing power resulting from both limited memory capacity and limited data communication bandwidth. Here we demonstrate experimentally that the synaptic weights shared in different time steps in an LSTM can be implemented with a memristor crossbar array, which has a small circuit footprint, can store a large number of parameters and offers in-memory computing capability that contributes to circumventing the ‘von Neumann bottleneck’. We illustrate the capability of our crossbar system as a core component in solving real-world problems in regression and classification, which shows that memristor LSTM is a promising low-power and low-latency hardware platform for edge inference. Deep neural networks are increasingly popular in data-intensive applications, but are power-hungry. New types of computer chips that are suited to the task of deep learning, such as memristor arrays where data handling and computing take place within the same unit, are required. A well-used deep learning model called long short-term memory, which can handle temporal sequential data analysis, is now implemented in a memristor crossbar array, promising an energy-efficient and low-footprint deep learning platform.

Vertical MoS2 Double-Layer Memristor with Electrochemical Metallization as an Atomic-Scale Synapse with Switching Thresholds Approaching 100 mV

Abstract: Atomically thin two-dimensional (2D) materials-such as transition metal dichalcogenide (TMD) monolayers and hexagonal boron nitride (hBN)-and their van der Waals layered preparations have been actively researched to build electronic devices such as field-effect transistors, junction diodes, tunneling devices, and, more recently, memristors. Two-dimensional material memristors built in lateral form, with horizontal placement of electrodes and the 2D material layers, have provided an intriguing window into the motions of ions along the atomically thin layers. On the other hand, 2D material memristors built in vertical form with top and bottom electrodes sandwiching 2D material layers may provide opportunities to explore the extreme of the memristive performance with the atomic-scale interelectrode distance. In particular, they may help push the switching voltages to a lower limit, which is an important pursuit in memristor research in general, given their roles in neuromorphic computing. In fact, recently Akinwande et al. performed a pioneering work to demonstrate a vertical memristor that sandwiches a single MoS2 monolayer between two inert Au electrodes, but it could neither attain switching voltages below 1 V nor control the switching polarity, obtaining both unipolar and bipolar switching devices. Here, we report a vertical memristor that sandwiches two MoS2 monolayers between an active Cu top electrode and an inert Au bottom electrode. Cu ions diffuse through the MoS2 double layers to form atomic-scale filaments. The atomic-scale thickness, combined with the electrochemical metallization, lowers switching voltages down to 0.1-0.2 V, on par with the state of the art. Furthermore, our memristor achieves consistent bipolar and analogue switching, and thus exhibits the synapse-like learning behavior such as the spike-timing dependent plasticity (STDP), the very first STDP demonstration among all 2D-material-based vertical memristors. The demonstrated STDP with low switching voltages is promising not only for low-power neuromorphic computing, but also from the point of view that the voltage range approaches the biological action potentials, opening up a possibility for direct interfacing with mammalian neuronal networks.

PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference

Abstract: Memristor crossbars are circuits capable of performing analog matrix-vector multiplications, overcoming the fundamental energy efficiency limitations of digital logic. They have been shown to be effective in special-purpose accelerators for a limited set of neural network applications. We present the Programmable Ultra-efficient Memristor-based Accelerator (PUMA) which enhances memristor crossbars with general purpose execution units to enable the acceleration of a wide variety of Machine Learning (ML) inference workloads. PUMA's microarchitecture techniques exposed through a specialized Instruction Set Architecture (ISA) retain the efficiency of in-memory computing and analog circuitry, without compromising programmability. We also present the PUMA compiler which translates high-level code to PUMA ISA. The compiler partitions the computational graph and optimizes instruction scheduling and register allocation to generate code for large and complex workloads to run on thousands of spatial cores. We have developed a detailed architecture simulator that incorporates the functionality, timing, and power models of PUMA's components to evaluate performance and energy consumption. A PUMA accelerator running at 1 GHz can reach area and power efficiency of 577 GOPS/s/mm 2 and 837~GOPS/s/W, respectively. Our evaluation of diverse ML applications from image recognition, machine translation, and language modelling (5M-800M synapses) shows that PUMA achieves up to 2,446× energy and 66× latency improvement for inference compared to state-of-the-art GPUs. Compared to an application-specific memristor-based accelerator, PUMA incurs small energy overheads at similar inference latency and added programmability.

Vacancy-Induced Synaptic Behavior in 2D WS 2 Nanosheet-Based Memristor for Low-Power Neuromorphic Computing.

Abstract: Memristors with nonvolatile memory characteristics have been expected to open a new era for neuromorphic computing and digital logic. However, existing memristor devices based on oxygen vacancy or metal-ion conductive filament mechanisms generally have large operating currents, which are difficult to meet low-power consumption requirements. Therefore, it is very necessary to develop new materials to realize memristor devices that are different from the mechanisms of oxygen vacancy or metal-ion conductive filaments to realize low-power operation. Herein, high-performance and low-power consumption memristors based on 2D WS2 with 2H phase are demonstrated, which show fast ON (OFF) switching times of 13 ns (14 ns), low program current of 1 µA in the ON state, and SET (RESET) energy reaching the level of femtojoules. Moreover, the memristor can mimic basic biological synaptic functions. Importantly, it is proposed that the generation of sulfur and tungsten vacancies and electron hopping between vacancies are dominantly responsible for the resistance switching performance. Density functional theory calculations show that the defect states formed by sulfur and tungsten vacancies are at deep levels, which prevent charge leakage and facilitate the realization of low-power consumption for neuromorphic computing application.

Self‐Assembled Networked PbS Distribution Quantum Dots for Resistive Switching and Artificial Synapse Performance Boost of Memristors

Abstract: With the advent of the era of big data, resistive random access memory (RRAM) has become one of the most promising nanoscale memristor devices (MDs) for storing huge amounts of information. However, the switching voltage of the RRAM MDs shows a very broad distribution due to the random formation of the conductive filaments. Here, self-assembled lead sulfide (PbS) quantum dots (QDs) are used to improve the uniformity of switching parameters of RRAM, which is very simple comparing with other methods. The resistive switching (RS) properties of the MD with the self-assembled PbS QDs exhibit better performance than those of MDs with pure-Ga2 O3 and randomly distributed PbS QDs, such as a reduced threshold voltage, uniformly distributed SET and RESET voltages, robust retention, fast response time, and low power consumption. This enhanced performance may be attributed to the ordered arrangement of the PbS QDs in the self-assembled PbS QDs which can efficiently guide the growth direction for the conducting filaments. Moreover, biosynaptic functions and plasticity, are implemented successfully in the MD with the self-assembled PbS QDs. This work offers a new method of improving memristor performance, which can significantly expand existing applications and facilitate the development of artificial neural systems.

In situ training of feed-forward and recurrent convolutional memristor networks

Abstract: The explosive growth of machine learning is largely due to the recent advancements in hardware and architecture. The engineering of network structures, taking advantage of the spatial or temporal translational isometry of patterns, naturally leads to bio-inspired, shared-weight structures such as convolutional neural networks, which have markedly reduced the number of free parameters. State-of-the-art microarchitectures commonly rely on weight-sharing techniques, but still suffer from the von Neumann bottleneck of transistor-based platforms. Here, we experimentally demonstrate the in situ training of a five-level convolutional neural network that self-adapts to non-idealities of the one-transistor one-memristor array to classify the MNIST dataset, achieving similar accuracy to the memristor-based multilayer perceptron with a reduction in trainable parameters of ~75% owing to the shared weights. In addition, the memristors encoded both spatial and temporal translational invariance simultaneously in a convolutional long short-term memory network—a memristor-based neural network with intrinsic 3D input processing—which was trained in situ to classify a synthetic MNIST sequence dataset using just 850 weights. These proof-of-principle demonstrations combine the architectural advantages of weight sharing and the area/energy efficiency boost of the memristors, paving the way to future edge artificial intelligence. Memristive devices can provide energy-efficient neural network implementations, but they must be tailored to suit different network architectures. Wang et al. develop a trainable weight-sharing mechanism for memristor-based CNNs and ConvLSTMs, achieving a 75% reduction in weights without compromising accuracy.

CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors

Abstract: Non-volatile computing-in-memory (nvCIM) could improve the energy efficiency of edge devices for artificial intelligence applications. The basic functionality of nvCIM has recently been demonstrated using small-capacity memristor crossbar arrays combined with peripheral readout circuits made from discrete components. However, the advantages of the approach in terms of energy efficiency and operating speeds, as well as its robustness against device variability and sneak currents, have yet to be demonstrated experimentally. Here, we report a fully integrated memristive nvCIM structure that offers high energy efficiency and low latency for Boolean logic and multiply-and-accumulation (MAC) operations. We fabricate a 1 Mb resistive random-access memory (ReRAM) nvCIM macro that integrates a one-transistor–one-resistor ReRAM array with control and readout circuits on the same chip using an established 65 nm foundry complementary metal–oxide–semiconductor (CMOS) process. The approach offers an access time of 4.9 ns for three-input Boolean logic operations, a MAC computing time of 14.8 ns and an energy efficiency of 16.95 tera operations per second per watt. Applied to a deep neural network using a split binary-input ternary-weighted model, the system can achieve an inference accuracy of 98.8% on the MNIST dataset. A 1 Mb non-volatile computing-in-memory system, which integrates a resistive memory array with control and readout circuits using an established 65 nm foundry CMOS process, can offer high energy efficiency and low latency for Boolean logic and multiply-and-accumulation operations.

Memristor, Hodgkin-Huxley, and Edge of Chaos.

Abstract: From a pedagogical point of view, the memristor is defined in this tutorial as any 2-terminal device obeying a state-dependent Ohm’s law. This tutorial also shows that from an experimental point of view, the memristor can be defined as any 2-terminal device that exhibits the fingerprints of “pinched” hysteresis loops in the v–i plane. It also shows that memristors endowed with a continuum of equilibrium states can be used as non-volatile analog memories. This tutorial shows that memristors span a much broader vista of complex phenomena and potential applications in many fields, including neurobiology. In particular, this tutorial presents toy memristors that can mimic the classic habituation and LTP learning phenomena. It also shows that sodium and potassium ion-channel memristors are the key to generating the action potential in the Hodgkin-Huxley equations, and that they are the key to resolving several unresolved anomalies associated with the Hodgkin-Huxley equations. This tutorial ends with an amazing new result derived from the new principle of local activity, which uncovers a minuscule life-enabling Goldilocks zone, dubbed the edge of chaos, where complex phenomena, including creativity and intelligence, may emerge. From an information processing perspective, this tutorial shows that synapses are locally-passive memristors, and that neurons are made of locally-active memristors.

A universal emulator for memristor, memcapacitor, and meminductor and its chaotic circuit.

Abstract: In this paper, a universal charge-controlled mem-elements (including memristor, memcapacitor, and meminductor) emulator consisting of off-the-shelf devices is proposed. With the unchanged topology of the circuit, the emulator can realize memristor, memcapacitor, and meminductor, respectively. The proposed emulation circuit has a simple mathematical relationship and is constructed with few active devices and passive components, which not only reduces the cost but also facilitates reproduction and facilitates future application research. The grounding and floating forms of the circuit are demonstrated, and Multisim circuit simulation and breadboard experiments validate the emulator's effectiveness. Furthermore, a universal mem-elements chaotic circuit is designed by using the proposed mem-elements emulator and other circuit elements, which is a deformation circuit of Chua's dual circuit. In this circuit, no matter whether the mem-element is memristor, memcapacitor, or meminductor, the chaotic circuit structure does not change, and all can generate hyper-chaos.

Memristor Cellular Automata and Memristor Discrete-Time Cellular Neural Networks.

Abstract: In this paper, we design a cellular automaton and a discrete-time cellular neural network (DTCNN) using nonlinear passive memristors. They can perform a number of applications, such as logical operations, image processing operations, complex behaviors, higher brain functions, etc. By modifying the characteristics of nonlinear memristors, the memristor DTCNN can perform almost all functions of memristor cellular automaton. Furthermore, it can perform more than one function at the same time, that is, it allows multitasking.

A New Memristor with 2D Ti 3 C 2 T x MXene Flakes as an Artificial Bio-Synapse

Abstract: Two-dimensional (2D) materials have attracted extensive research interest in academia due to their excellent electrochemical properties and broad application prospects. Among them, 2D transition metal carbides (Ti3 C2 Tx ) show semiconductor characteristics and are studied widely. However, there are few academic reports on the use of 2D MXene materials as memristors. In this work, reported is a memristor based on MXene Ti3 C2 Tx flakes. After electroforming, Al/Ti3 C2 Tx /Pt devices exhibit repeatable resistive switching (RS) behavior. More interestingly, the resistance of this device can be continuously modulated under the pulse sequence with 10 ns pulse width, and the pulse width of 10 ns is much lower than that in other reported work. Moreover, on the nanosecond scale, the transition from short-term plasticity to long-term plasticity is achieved. These two properties indicate that this device is favorable for ultrafast biological synapse applications and high-efficiency training of neural networks. Through the exploration of the microstructure, Ti vacancies and partial oxidation are proposed as the origins of the physical mechanism of RS behavior. This work reveals that 2D MXene Ti3 C2 Tx flakes have excellent potential for use in memristor devices, which may open the door for more functions and applications.

A Unified Capacitive-Coupled Memristive Model for the Nonpinched Current-Voltage Hysteresis Loop.

Abstract: The concept of the memristor, a resistor with memory, was proposed by Chua in 1971 as the fourth basic element of electric circuitry. Despite a significant amount of effort devoted to the understanding of memristor theory, our understanding of the nonpinched current–voltage (I–V) hysteresis loop in memristors remains incomplete. Here we propose a physical model of a memristor, with a capacitor connected in parallel, which explains how the nonpinched I–V hysteresis behavior originates from the capacitive-coupled memristive effect. Our model replicates eight types of characteristic nonlinear I–V behavior, which explains all observed nonpinched I–V curves seen in experiments. Furthermore, a reversible transition from a nonpinched I–V hysteresis loop to an ideal pinched I–V hysteresis loop is found, which explains the experimental data obtained in C15H11O6-based devices when subjected to an external stimulus (e.g., voltage, moisture, or temperature). Our results provide the vital physics models and materials ...

Polymer Analog Memristive Synapse with Atomic-Scale Conductive Filament for Flexible Neuromorphic Computing System.

Abstract: With the advent of artificial intelligence (AI), memristors have received significant interest as a synaptic building block for neuromorphic systems, where each synaptic memristor should operate in an analog fashion, exhibiting multilevel accessible conductance states. Here, we demonstrate that the transition of the operation mode in poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (pV3D3)-based flexible memristor from conventional binary to synaptic analog switching can be achieved simply by reducing the size of the formed filament. With the quantized conductance states observed in the flexible pV3D3 memristor, analog potentiation and depression characteristics of the memristive synapse are obtained through the growth of atomically thin Cu filament and lateral dissolution of the filament via dominant electric field effect, respectively. The face classification capability of our memristor is evaluated via simulation using an artificial neural network consisting of pV3D3 memristor synapses. These resu...

Adjusting Learning Rate of Memristor-Based Multilayer Neural Networks via Fuzzy Method

Abstract: Back propagation (BP) based on stochastic gradient descent is the prevailing method to train multilayer neural networks (MNNs) with hidden layers. However, the existence of the physical separation between memory arrays and arithmetic module makes it inefficient and ineffective to implement BP in conventional digital hardware. Although CMOS may alleviate some problems of the hardware implementation of MNNs, synapses based on CMOS cost too much power and areas in very large scale integrated circuits. As a novel device, memristor shows promises to overcome this shortcoming due to its ability to closely integrate processing and memory. This paper proposes a novel circuit for implementing a synapse based on a memristor and two MOSFET tansistors (p-type and n-type). Compared with a CMOS-only circuit, the proposed one reduced the area consumption by 92%–98%. In addition, we develop a fuzzy method for the adjustment of the learning rates of MNNs, which increases the learning accuracy by 2%–3% compared with a constant learning rate. Meanwhile, the fuzzy adjustment method is robust and insensitive to parameter changes due to the approximate reasoning. Furthermore, the proposed methods can be extended to memristor-based multilayer convolutional neural network for complex tasks. The novel architecture behaves in a human-liking thinking process.

PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference

Abstract: Memristor crossbars are circuits capable of performing analog matrix-vector multiplications, overcoming the fundamental energy efficiency limitations of digital logic. They have been shown to be effective in special-purpose accelerators for a limited set of neural network applications. We present the Programmable Ultra-efficient Memristor-based Accelerator (PUMA) which enhances memristor crossbars with general purpose execution units to enable the acceleration of a wide variety of Machine Learning (ML) inference workloads. PUMA's microarchitecture techniques exposed through a specialized Instruction Set Architecture (ISA) retain the efficiency of in-memory computing and analog circuitry, without compromising programmability. We also present the PUMA compiler which translates high-level code to PUMA ISA. The compiler partitions the computational graph and optimizes instruction scheduling and register allocation to generate code for large and complex workloads to run on thousands of spatial cores. We have developed a detailed architecture simulator that incorporates the functionality, timing, and power models of PUMA's components to evaluate performance and energy consumption. A PUMA accelerator running at 1 GHz can reach area and power efficiency of $577~GOPS/s/mm^2$ and $837~GOPS/s/W$, respectively. Our evaluation of diverse ML applications from image recognition, machine translation, and language modelling (5M-800M synapses) shows that PUMA achieves up to $2,446\times$ energy and $66\times$ latency improvement for inference compared to state-of-the-art GPUs. Compared to an application-specific memristor-based accelerator, PUMA incurs small energy overheads at similar inference latency and added programmability.

Perovskite-related (CH3NH3)3Sb2Br9 for forming-free memristor and low-energy-consuming neuromorphic computing

Abstract: Organic–inorganic halide perovskite materials exhibit excellent memristive properties, such as a high on/off ratio and low switching voltage. However, most studies have focused on Pb-based perovskites. Here, we report on the resistive switching and neuromorphic computing properties of Pb-free perovskite-related MA3Sb2Br9 (MA = CH3NH3). The Ag/PMMA/MA3Sb2Br9/ITO devices show forming-free characteristics due to a self-formed conducting filament induced by metallic Sb present in the as-prepared MA3Sb2Br9 layer. An MA3Sb2Br9-based memristor exhibits a reliable on/off ratio (∼102), an endurance of 300 cycles, a retention time of ∼104 s and multilevel storage characteristics. Furthermore, synaptic characteristics, such as short-term potentiation, short-term depression and long-term potentiation, are revealed along with a low energy-consumption of 117.9 fJ μm−2, which indicates that MA3Sb2Br9 is a promising material for neuromorphic computing.

Gate-Tunable and Multidirection-Switchable Memristive Phenomena in a Van Der Waals Ferroelectric

Abstract: Memristive devices have been extensively demonstrated for applications in nonvolatile memory, computer logic, and biological synapses. Precise control of the conducting paths associated with the resistance switching in memristive devices is critical for optimizing their performances including ON/OFF ratios. Here, gate tunability and multidirectional switching can be implemented in memristors for modulating the conducting paths using hexagonal α-In2 Se3 , a semiconducting van der Waals ferroelectric material. The planar memristor based on in-plane (IP) polarization of α-In2 Se3 exhibits a pronounced switchable photocurrent, as well as gate tunability of the channel conductance, ferroelectric polarization, and resistance-switching ratio. The integration of vertical α-In2 Se3 memristors based on out-of-plane (OOP) polarization is demonstrated with a device density of 7.1 × 109 in.-2 and a resistance-switching ratio of well over 103 . A multidirectionally operated α-In2 Se3 memristor is also proposed, enabling the control of the OOP (or IP) resistance state directly by an IP (or OOP) programming pulse, which has not been achieved in other reported memristors. The remarkable behavior and diverse functionalities of these ferroelectric α-In2 Se3 memristors suggest opportunities for future logic circuits and complex neuromorphic computing.

Artificial and wearable albumen protein memristor arrays with integrated memory logic gate functionality

Abstract: Ultra-flexible egg albumen paper with a permittivity of 15–21, which is an improvement of nearly 300% compared with native egg albumen, is synthesized. Wearable protein-based memristor arrays exhibit excellent memory behavior and memory logic gate functionality under dual photoelectric control.

Robust Ag/ZrO2/WS2/Pt Memristor for Neuromorphic Computing

Abstract: The development of the information age has made resistive random access memory (RRAM) a critical nanoscale memristor device (MD). However, due to the randomness of the area formed by the conductive filaments (CFs), the RRAM MD still suffers from a problem of insufficient reliability. In this study, the memristor of Ag/ZrO2/WS2/Pt structure is proposed for the first time, and a layer of two-dimensional (2D) WS2 nanosheets was inserted into the MD to form 2D material and oxide double-layer MD (2DOMD) to improve the reliability of single-layer devices. The results indicate that the electrochemical metallization memory cell exhibits a highly stable memristive switching and concentrated ON- and OFF-state voltage distribution, high speed (∼10 ns), and robust endurance (>109 cycles). This result is superior to MDs with a single-layer ZrO2 or WS2 film because two layers have different ion transport rates, thereby limiting the rupture/rejuvenation of CFs to the bilayer interface region, which can greatly reduce the randomness of CFs in MDs. Moreover, we used the handwritten recognition dataset (i.e., the Modified National Institute of Standards and Technology (MNIST) database) for neuromorphic simulations. Furthermore, biosynaptic functions and plasticity, including spike-timing-dependent plasticity and paired-pulse facilitation, have been successfully achieved. By incorporating 2D materials and oxides into a double-layer MD, the practical application of RRAM MD can be significantly enhanced to facilitate the development of artificial synapses for brain-enhanced computing systems in the future.