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Showing papers on "Memristor published in 2020"


Journal ArticleDOI
29 Jan 2020-Nature
TL;DR: The fabrication of high-yield, high-performance and uniform memristor crossbar arrays for the implementation of CNNs and an effective hybrid-training method to adapt to device imperfections and improve the overall system performance are proposed.
Abstract: Memristor-enabled neuromorphic computing systems provide a fast and energy-efficient approach to training neural networks1–4. However, convolutional neural networks (CNNs)—one of the most important models for image recognition5—have not yet been fully hardware-implemented using memristor crossbars, which are cross-point arrays with a memristor device at each intersection. Moreover, achieving software-comparable results is highly challenging owing to the poor yield, large variation and other non-ideal characteristics of devices6–9. Here we report the fabrication of high-yield, high-performance and uniform memristor crossbar arrays for the implementation of CNNs, which integrate eight 2,048-cell memristor arrays to improve parallel-computing efficiency. In addition, we propose an effective hybrid-training method to adapt to device imperfections and improve the overall system performance. We built a five-layer memristor-based CNN to perform MNIST10 image recognition, and achieved a high accuracy of more than 96 per cent. In addition to parallel convolutions using different kernels with shared inputs, replication of multiple identical kernels in memristor arrays was demonstrated for processing different inputs in parallel. The memristor-based CNN neuromorphic system has an energy efficiency more than two orders of magnitude greater than that of state-of-the-art graphics-processing units, and is shown to be scalable to larger networks, such as residual neural networks. Our results are expected to enable a viable memristor-based non-von Neumann hardware solution for deep neural networks and edge computing. A fully hardware-based memristor convolutional neural network using a hybrid training method achieves an energy efficiency more than two orders of magnitude greater than that of graphics-processing units.

1,033 citations


Journal ArticleDOI
TL;DR: This paper proposes a novel ‘Simultaneous Logic in-Memory’ (SLIM) methodology which is complementary to existing LIM approaches in literature and demonstrates novel SLIM bitcells comprising non-filamentary bilayer analog OxRAM devices with NMOS transistors.
Abstract: von Neumann architecture based computers isolate computation and storage (i.e. data is shuttled between computation blocks (processor) and memory blocks). The to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the Memory wall. Logic in-Memory (LIM)/In-Memory Computing (IMC) approaches aim to address this bottleneck by directly computing inside memory units thereby eliminating energy-intensive and time-consuming data movement. Several recent works in literature, propose realization of logic function(s) directly using arrays of emerging resistive memory devices (example- memristors, RRAM/ReRAM, PCM, CBRAM, OxRAM, STT-MRAM etc.), rather than using conventional transistors for computing. The logic/embedded-side of digital systems (like processors, micro-controllers) can greatly benefit from such LIM realizations. However, the pure storage-side of digital systems (example SSDs, enterprise storage etc.) will not benefit much from such LIM approaches as when memory arrays are used for logic they lose their core functionality of storage. Thus, there is the need for an approach complementary to existing LIM techniques, that's more beneficial for the storage-side of digital systems; one that gives compute capability to memory arrays not at the cost of their existing stored states. Fundamentally, this would require memory nanodevice arrays that are capable of storing and computing simultaneously. In this paper, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology which is complementary to existing LIM approaches in literature. Through extensive experiments we demonstrate novel SLIM bitcells (1T-1R/2T-1R) comprising non-filamentary bilayer analog OxRAM devices with NMOS transistors. Proposed bitcells are capable of implementing both Memory and Logic operations simultaneously. Detailed programming scheme, array level implementation, and controller architecture are also proposed. Furthermore, to study the impact of proposed SLIM approach for real-world implementations, we performed analysis for two applications: (i) Sobel Edge Detection, and (ii) Binary Neural Network- Multi layer Perceptron (BNN-MLP). By performing all computations in SLIM bitcell array, huge Energy Delay Product (EDP) savings of ≈75× for 1T-1R (≈40× for 2T-1R) SLIM bitcell were observed for edge-detection application while EDP savings of ≈3.5× for 1T-1R (≈1.6× for 2T-1R) SLIM bitcell were observed for BNN-MLP application respectively, in comparison to conventional computing. EDP savings owing to reduction in data transfer between CPU ↔ memory is observed to be ≈780× (for both SLIM bitcells).

633 citations


Journal ArticleDOI
TL;DR: A technology-agnostic approach, committee machines, is demonstrated, which increases the inference accuracy of memristive neural networks that suffer from device variability, faulty devices, random telegraph noise and line resistance.
Abstract: Artificial neural networks are notoriously power- and time-consuming when implemented on conventional von Neumann computing systems. Consequently, recent years have seen an emergence of research in machine learning hardware that strives to bring memory and computing closer together. A popular approach is to realise artificial neural networks in hardware by implementing their synaptic weights using memristive devices. However, various device- and system-level non-idealities usually prevent these physical implementations from achieving high inference accuracy. We suggest applying a well-known concept in computer science—committee machines—in the context of memristor-based neural networks. Using simulations and experimental data from three different types of memristive devices, we show that committee machines employing ensemble averaging can successfully increase inference accuracy in physically implemented neural networks that suffer from faulty devices, device-to-device variability, random telegraph noise and line resistance. Importantly, we demonstrate that the accuracy can be improved even without increasing the total number of memristors. Designing reliable and energy-efficient memristor-based artificial neural networks remains a challenge. Here, the authors demonstrate a technology-agnostic approach, committee machines, which increases the inference accuracy of memristive neural networks that suffer from device variability, faulty devices, random telegraph noise and line resistance.

221 citations


Journal ArticleDOI
01 Jul 2020
TL;DR: A memristor-based annealing system that uses an analogue neuromorphic architecture based on a Hopfield neural network can solve non-deterministic polynomial-time (NP)-hard max-cut problems in an approach that is potentially more efficient than current quantum, optical and digital approaches.
Abstract: To tackle important combinatorial optimization problems, a variety of annealing-inspired computing accelerators, based on several different technology platforms, have been proposed, including quantum-, optical- and electronics-based approaches. However, to be of use in industrial applications, further improvements in speed and energy efficiency are necessary. Here, we report a memristor-based annealing system that uses an energy-efficient neuromorphic architecture based on a Hopfield neural network. Our analogue–digital computing approach creates an optimization solver in which massively parallel operations are performed in a dense crossbar array that can inject the needed computational noise through the analogue array and device errors, amplified or dampened by using a novel feedback algorithm. We experimentally show that the approach can solve non-deterministic polynomial-time (NP)-hard max-cut problems by harnessing the intrinsic hardware noise. We also use experimentally grounded simulations to explore scalability with problem size, which suggest that our memristor-based approach can offer a solution throughput over four orders of magnitude higher per power consumption relative to current quantum, optical and fully digital approaches. A memristor-based annealing system that uses an analogue neuromorphic architecture based on a Hopfield neural network can solve non-deterministic polynomial (NP)-hard max-cut problems in an approach that is potentially more efficient than current quantum, optical and digital approaches.

174 citations


Journal ArticleDOI
TL;DR: An overview of the latest advances in the structures, mechanisms, and memristive characteristics of 2D material-based memristor-based artificial synapses is presented and the potentials and challenges of these emerging materials for future neuromorphic electronics are discussed.
Abstract: The memristor, a composite word of memory and resistor, has become one of the most important electronic components for brain-inspired neuromorphic computing in recent years. This device has the ability to control resistance with multiple states by memorizing the history of previous electrical inputs, enabling it to mimic a biological synapse in the neural network of the human brain. Among many candidates for memristive materials, including metal oxides, organic materials, and low-dimensional nanomaterials, 2D layered materials have been widely investigated owing to their outstanding physical properties and electrical tunability, low-power-switching capability, and hetero-integration compatibility. Hence, a large number of experimental demonstrations on 2D material-based memristors have been reported showing their unique memristive characteristics and novel synaptic functionalities, distinct from traditional bulk-material-based systems. Herein, an overview of the latest advances in the structures, mechanisms, and memristive characteristics of 2D material-based memristors is presented. Additionally, novel strategies to modulate and enhance the synaptic functionalities of 2D-memristor-based artificial synapses are summarized. Finally, as a foreseeing perspective, the potentials and challenges of these emerging materials for future neuromorphic electronics are also discussed.

168 citations


Journal ArticleDOI
TL;DR: It is demonstrated that the sensitive extreme multistability phenomenon becomes detectable in the flux–charge domain, which is efficient for exploring the inner mechanisms and further seeking possible applications of this special phenomenon.
Abstract: In this paper, from a new perspective of flux and charge, we present in-depth analyses of two ideal memristor emulators and the fifth-order memristive Chua's circuit constructed based on them. The constitutive flux–charge relations of the two adopted memristor emulators are first formulated, and their initial-dependent characteristics are numerically revealed and experimentally verified. Thereafter, with these two constitutive relations, a third-order dimensionality decreasing flux–charge model for the fifth-order memristive Chua's circuit is constructed, in which five extra constant system parameters are introduced to indicate the initial states of the five dynamic elements. Numerical simulations confirm that this newly constructed model possesses several determined equilibria and maintains the initial-dependent dynamics of the original voltage–current model. Thus, the complex and sensitive initial state-related extreme multistability phenomenon can be deeply explored through theoretical analyses and hardware measurements. It is demonstrated that the sensitive extreme multistability phenomenon becomes detectable in the flux–charge domain, which is efficient for exploring the inner mechanisms and further seeking possible applications of this special phenomenon.

153 citations


Journal ArticleDOI
TL;DR: An artificial neuron based on NbO x volatile memristor is demonstrated that not only realizes traditional all-or-nothing, threshold-driven spiking and spatiotemporal integration, but also enables dynamic logic including XOR function that is not linearly separable and multiplicative gain modulation among different dendritic inputs, therefore surpassing neuronal functions described by a simple point neuron model.
Abstract: As a key building block of biological cortex, neurons are powerful information processing units and can achieve highly complex nonlinear computations even in individual cells Hardware implementation of artificial neurons with similar capability is of great significance for the construction of intelligent, neuromorphic systems Here, we demonstrate an artificial neuron based on NbOx volatile memristor that not only realizes traditional all-or-nothing, threshold-driven spiking and spatiotemporal integration, but also enables dynamic logic including XOR function that is not linearly separable and multiplicative gain modulation among different dendritic inputs, therefore surpassing neuronal functions described by a simple point neuron model A monolithically integrated 4 × 4 fully memristive neural network consisting of volatile NbOx memristor based neurons and nonvolatile TaOx memristor based synapses in a single crossbar array is experimentally demonstrated, showing capability in pattern recognition through online learning using a simplified δ-rule and coincidence detection, which paves the way for bio-inspired intelligent systems Designing energy efficient and scalable artificial networks for neuromorphic computing remains a challenge Here, the authors demonstrate online learning in a monolithically integrated 4 × 4 fully memristive neural network consisting of volatile NbOx memristor neurons and nonvolatile TaOx memristor synapses

153 citations


Journal ArticleDOI
TL;DR: The discovery of an alloyed memristor with alloyed conduction channels enables stable and controllable device operation with high switching uniformity and allows the fabrication of large-scale crossbar arrays that feature a high device yield and accurate analogue programming capability.
Abstract: A memristor1 has been proposed as an artificial synapse for emerging neuromorphic computing applications2,3. To train a neural network in memristor arrays, changes in weight values in the form of device conductance should be distinct and uniform3. An electrochemical metallization (ECM) memory4,5, typically based on silicon (Si), has demonstrated a good analogue switching capability6,7 owing to the high mobility of metal ions in the Si switching medium8. However, the large stochasticity of the ion movement results in switching variability. Here we demonstrate a Si memristor with alloyed conduction channels that shows a stable and controllable device operation, which enables the large-scale implementation of crossbar arrays. The conduction channel is formed by conventional silver (Ag) as a primary mobile metal alloyed with silicidable copper (Cu) that stabilizes switching. In an optimal alloying ratio, Cu effectively regulates the Ag movement, which contributes to a substantial improvement in the spatial/temporal switching uniformity, a stable data retention over a large conductance range and a substantially enhanced programmed symmetry in analogue conductance states. This alloyed memristor allows the fabrication of large-scale crossbar arrays that feature a high device yield and accurate analogue programming capability. Thus, our discovery of an alloyed memristor is a key step paving the way beyond von Neumann computing.

139 citations


Journal ArticleDOI
TL;DR: A high performance memristor based on a Ag/BaTiO3 /Nb:SrTiO 3 ferroelectric tunnel junction with the fastest operation speed (600 ps) and the highest number of states (32 states or 5 bits) per cell among the reported FTJs.
Abstract: Next-generation non-volatile memories with ultrafast speed, low power consumption, and high density are highly desired in the era of big data. Here, we report a high performance memristor based on a Ag/BaTiO3/Nb:SrTiO3 ferroelectric tunnel junction (FTJ) with the fastest operation speed (600 ps) and the highest number of states (32 states or 5 bits) per cell among the reported FTJs. The sub-nanosecond resistive switching maintains up to 358 K, and the write current density is as low as 4 × 103 A cm−2. The functionality of spike-timing-dependent plasticity served as a solid synaptic device is also obtained with ultrafast operation. Furthermore, it is demonstrated that a Nb:SrTiO3 electrode with a higher carrier concentration and a metal electrode with lower work function tend to improve the operation speed. These results may throw light on the way for overcoming the storage performance gap between different levels of the memory hierarchy and developing ultrafast neuromorphic computing systems. Memristor devices based on ferroelectric tunnel junctions are promising, but suffer from quite slow switching times. Here, the authors report on ultrafast switching times at and above room temperature of 600ps in Ag/BaTiO3/Nb:SrTiO3 based ferroelectric tunnel junctions.

133 citations


Journal ArticleDOI
TL;DR: A wide range of memristors and memristive-related devices for artificial synapses and neurons is highlighted and the device structures, switching principles, and the applications of essential synaptic and neuronal functionalities are sequentially presented.
Abstract: Memristors have recently attracted significant interest due to their applicability as promising building blocks of neuromorphic computing and electronic systems. The dynamic reconfiguration of memristors, which is based on the history of applied electrical stimuli, can mimic both essential analog synaptic and neuronal functionalities. These can be utilized as the node and terminal devices in an artificial neural network. Consequently, the ability to understand, control, and utilize fundamental switching principles and various types of device architectures of the memristor is necessary for achieving memristor-based neuromorphic hardware systems. Herein, a wide range of memristors and memristive-related devices for artificial synapses and neurons is highlighted. The device structures, switching principles, and the applications of essential synaptic and neuronal functionalities are sequentially presented. Moreover, recent advances in memristive artificial neural networks and their hardware implementations are introduced along with an overview of the various learning algorithms. Finally, the main challenges of the memristive synapses and neurons toward high-performance and energy-efficient neuromorphic computing are briefly discussed. This progress report aims to be an insightful guide for the research on memristors and neuromorphic-based computing.

130 citations


Journal ArticleDOI
TL;DR: A type of diffusive memristor, fabricated from the protein nanowires harvested from the bacterium Geobacter sulfurreducens, is demonstrated that functions at the biological voltages of 40-100 mV, and the potential of using the Memristor to directly process biosensing signals is demonstrated.
Abstract: Memristive devices are promising candidates to emulate biological computing. However, the typical switching voltages (0.2-2 V) in previously described devices are much higher than the amplitude in biological counterparts. Here we demonstrate a type of diffusive memristor, fabricated from the protein nanowires harvested from the bacterium Geobacter sulfurreducens, that functions at the biological voltages of 40-100 mV. Memristive function at biological voltages is possible because the protein nanowires catalyze metallization. Artificial neurons built from these memristors not only function at biological action potentials (e.g., 100 mV, 1 ms) but also exhibit temporal integration close to that in biological neurons. The potential of using the memristor to directly process biosensing signals is also demonstrated. Designing energy efficient systems capable to directly process signals at biological voltages remains a challenge. Here, the authors propose a bio-compatible memristor device based on protein-nanowire dielectric, harvested from the bacterium Geobactor sulfurreducens, working at biological voltages.

Journal ArticleDOI
TL;DR: The time delay is considered, in order to form associative memory when the food stimulus lags behind the ring stimulus for a certain period of time, and provides a reference for further development of the brain-like systems.
Abstract: Most memristor-based Pavlov associative memory neural networks strictly require that only simultaneous food and ring appear to generate associative memory. In this article, the time delay is considered, in order to form associative memory when the food stimulus lags behind the ring stimulus for a certain period of time. In addition, the rate of learning can be changed with the length of time between the ring stimulus and food stimulus. A memristive neural network circuit that can realize Pavlov associative memory with time delay is designed and verified by the simulation results. The designed circuit consists of a synapse module, a voltage control module, and a time-delay module. The functions, such as learning, forgetting, fast learning, slow forgetting, and time-delay learning, are implemented by the circuit. The Pavlov associative memory neural network with time-delay learning provides a reference for further development of the brain-like systems.

Journal ArticleDOI
TL;DR: It is reported that robust ferroelectric tunnel junctions can be employed to design high‐performance electronic synapses that show an excellent memristor function with many reproducible states through gradual ferroElectric domain switching.
Abstract: Neuromorphic computing consisting of artificial synapses and neural network algorithms provides a promising approach for overcoming the inherent limitations of current computing architecture. Developments in electronic devices that can accurately mimic the synaptic plasticity of biological synapses, have promoted the research boom of neuromorphic computing. It is reported that robust ferroelectric tunnel junctions can be employed to design high-performance electronic synapses. These devices show an excellent memristor function with many reproducible states (≈200) through gradual ferroelectric domain switching. Both short- and long-term plasticity can be emulated by finely tuning the applied pulse parameters in the electronic synapse. The analog conductance switching exhibits high linearity and symmetry with small switching variations. A simulated artificial neural network with supervised learning built from these synaptic devices exhibited high classification accuracy (96.4%) for the Mixed National Institute of Standards and Technology (MNIST) handwritten recognition data set.

Journal ArticleDOI
TL;DR: A mathematical memristor model with multistability is constructed using standard nonlinear theory as well as circuit and system theory to simulate a synaptic connection in a Hopfield neural network.
Abstract: Nowadays, there is a lot of study on memristor-based systems with multistability. However, there is no study on memristor with multistability. This brief constructs a mathematical memristor model with multistability. The origin of the multi-stable dynamics is revealed using standard nonlinear theory as well as circuit and system theory. Moreover, the multi-stable memristor is applied to simulate a synaptic connection in a Hopfield neural network. The memristive neural network successfully generates infinitely many coexisting chaotic attractors unobserved in previous Hopfield-type neural networks. The results are also confirmed in analog circuits based on commercially available electronic elements.

Journal ArticleDOI
TL;DR: A new chaotic system generated from the simplest memristor chaotic circuit by introducing a simple nonlinear feedback control input that has infinitely many equilibria and abundant coexisting attractors is reported.

Journal ArticleDOI
TL;DR: A memristor-based artificial dendrite enables the neural network to perform high-accuracy computation tasks with reduced power consumption and shows the potential of substantial overall performance improvement.
Abstract: In the nervous system, dendrites, branches of neurons that transmit signals between synapses and soma, play a critical role in processing functions, such as nonlinear integration of postsynaptic signals The lack of these critical functions in artificial neural networks compromises their performance, for example in terms of flexibility, energy efficiency and the ability to handle complex tasks Here, by developing artificial dendrites, we experimentally demonstrate a complete neural network fully integrated with synapses, dendrites and soma, implemented using scalable memristor devices We perform a digit recognition task and simulate a multilayer network using experimentally derived device characteristics The power consumption is more than three orders of magnitude lower than that of a central processing unit and 70 times lower than that of a typical application-specific integrated circuit chip This network, equipped with functional dendrites, shows the potential of substantial overall performance improvement, for example by extracting critical information from a noisy background with significantly reduced power consumption and enhanced accuracy A memristor-based artificial dendrite enables the neural network to perform high-accuracy computation tasks with reduced power consumption

Journal ArticleDOI
TL;DR: A type of spike-rate-dependent plasticity based on a triplet learning scheme in a WO 3−x -based second-order memristor network for spatiotemporal patterns is demonstrated and rate-based orientation selectivity is demonstrated in a simulated feedforward memristive network with this generalized Bienenstock-Cooper-Munro framework.
Abstract: The close replication of synaptic functions is an important objective for achieving a highly realistic memristor-based cognitive computation. The emulation of neurobiological learning rules may allow the development of neuromorphic systems that continuously learn without supervision. In this work, the Bienenstock-Cooper-Munro learning rule, as a typical case of spike-rate-dependent plasticity, is mimicked using a generalized triplet-spike-timing-dependent plasticity scheme in a WO3-x memristive synapse. It demonstrates both presynaptic and postsynaptic activities and remedies the absence of the enhanced depression effect in the depression region, allowing a better description of the biological counterpart. The threshold sliding effect of Bienenstock-Cooper-Munro rule is realized using a history-dependent property of the second-order memristor. Rate-based orientation selectivity is demonstrated in a simulated feedforward memristive network with this generalized Bienenstock-Cooper-Munro framework. These findings provide a feasible approach for mimicking Bienenstock-Cooper-Munro learning rules in memristors, and support the applications of spatiotemporal coding and learning using memristive networks.

Journal ArticleDOI
TL;DR: Theoretical analysis and simulation results indicate that the simple chaotic circuit with a memristor, a memcapacitor and a linear inductor in parallel has very rich dynamical characteristics.
Abstract: In this paper, we focus on a novel simple chaotic circuit with a memristor, a memcapacitor and a linear inductor in parallel. Then we establish the circuit’s dimensionless mathematical model. Nineteen types of different chaotic attractors are found in the circuit. The chaotic system’s equilibrium point and stability are analyzed by using the traditional dynamic analysis methods, and the dynamical behaviors with three varying parameters of this circuit are analyzed in detail. Furthermore, some special phenomena such as state transition, chaos degradation and the multiple coexisting attractors are discovered. Finally, we implement this circuit through the DSP platform and the results illustrate the validity of the theoretical analysis. Theoretical analysis and simulation results indicate that the simple chaotic circuit has very rich dynamical characteristics.

Journal ArticleDOI
TL;DR: This work provides the opportunity of exploring the novel application for the development of next-generation neuromorphic computing based on lead-free halide perovskites by employing the ultra-thin polymethylmethacrylate layer in Ag/PMMA/Cs3Cu2I5/ITO memristor.
Abstract: Recently, several types of lead halide perovskites have been demonstrated as active layers in resistive switching memory or artificial synaptic devices for neuromorphic computing applications. However, the thermal instability and toxicity of lead halide perovskites severely restricted their further practical applications. Herein, the environmentally friendly and uniform Cs3Cu2I5 perovskite films are introduced to act as the active layer in the Ag/Cs3Cu2I5/ITO memristor. Generally, the Ag ions could react with iodide ions and form AgIx compounds easily, so the Ag/PMMA/Cs3Cu2I5/ITO memristor was designed by employing the ultrathin polymethylmethacrylate (PMMA) layer to avoid the direct contact between the top Ag electrode and Cs3Cu2I5 perovskite films. After optimization, the obtained memristor demonstrated bipolar resistive switching with low operating voltage ( 104 s). Additionally, biological synaptic behaviors including long-term potentiation and long-term depression have been investigated. By using the MNIST handwritten recognition data set, the handwritten recognition rate based on experimental data could reach 94%. In conclusion, our work provides the opportunity of exploring the novel application for the development of next-generation neuromorphic computing based on lead-free halide perovskites.

Journal ArticleDOI
11 May 2020
TL;DR: In this article, a nonlinear ferroelectric tunnel junction memristors can be used to perform linear vector-matrix multiplication operations at ultralow currents and achieve energy efficiencies above 100 tera-operations per second per watt.
Abstract: Analogue in-memory computing using memristors could alleviate the performance constraints imposed by digital von Neumann systems in data-intensive tasks. Conventional linear memristors typically operate at high currents, potentially limiting power efficiency and scalability in practical applications. Here, we show that nonlinear ferroelectric tunnel junction memristors can perform linear computation at ultralow currents. Using logarithmic line drivers, we demonstrate that analogue-voltage-amplitude vector–matrix multiplication (VMM) can be performed in selectorless ferroelectric tunnel junction crossbars by exploiting a device nonlinearity factor that remains constant for multiple conductive states. We also show that our ferroelectric tunnel junction crossbars have the attributes required to scale analogue VMM-intensive applications, such as neural inference engines, towards energy efficiencies above 100 tera-operations per second per watt. Nonlinear ferroelectric tunnel junction memristors can be used to perform linear vector–matrix multiplication operations at ultralow currents.

Journal ArticleDOI
TL;DR: By constructing a ring network of memristor synapse-coupled neuron network, several types of collective behaviors including incoherent, coherent, imperfect synchronization, and chimeraStates are disclosed numerically, which indicate that the chimera states arisen in the ring network are dependent on the memristOr coupling coefficient and sub-network coupling strength.
Abstract: Memristor synapse can be used to characterize the electromagnetic induction effect between two neurons that induces an action current by their membrane potential difference. This paper proposes a memristor synapse-coupled neuron network with no equilibrium, which is achieved using a memristor synapse to connect the membrane potentials of two identical three-dimensional memristive Hindmarsh–Rose neurons. Exponential synchronization is proved theoretically, and synchronous activities are discussed numerically. The theoretical and numerical results illustrate that the synchronicities of memristor synapse-coupled neuron network are related to the memristor coupling coefficient and especially related to the initial states of memristor synapse and coupling neurons. Furthermore, by constructing a ring network of memristor synapse-coupled neuron network, several types of collective behaviors including incoherent, coherent, imperfect synchronization, and chimera states are disclosed numerically, which indicate that the chimera states arisen in the ring network are dependent on the memristor coupling coefficient and sub-network coupling strength.

Journal ArticleDOI
TL;DR: A flexible three-layer crossbar memristor arrays based on HfAlOx film deposited by controlled growth of low-temperature atomic layer deposition is presented, exhibiting the multilevel information transmission functionality with the power consumption of 4.28 aJ and the speed of 50 ns in per synaptic event.
Abstract: To construct an artificial intelligence system with high efficient information integration and computing capability like the human brain, it is necessary to realize the biological neurotransmission and information processing in artificial neural network (ANN), rather than a single electronic synapse as most reports. Because the power consumption of single synaptic event is ∼10 fJ in biology, designing an intelligent memristors-based 3D ANN with energy consumption lower than femtojoule-level (e.g., attojoule-level) and faster operating speed than millisecond-level makes it possible for constructing a higher energy efficient and higher speed computing system than the human brain. In this paper, a flexible 3D crossbar memristor array is presented, exhibiting the multilevel information transmission functionality with the power consumption of 4.28 aJ and the response speed of 50 ns per synaptic event. This work is a significant step toward the development of an ultrahigh efficient and ultrahigh-speed wearable 3D neuromorphic computing system.

Journal ArticleDOI
TL;DR: The stability of the closed-loop system is proven via a fractional version of the Lyapunov stability theorem and Barbalat's lemma and the developed control technique on the uncertain fractional-order hyperchaotic memristor oscillator is investigated.

Journal ArticleDOI
TL;DR: In this paper, an energy band-based physical model is proposed to comprehend the evolution process of memristor, which gives an insight into the moisture effect on the resistive switching behaviors.

Journal ArticleDOI
TL;DR: This paper introduces a non-ideal flux-controlled memristor model into a Hopfield neural network (HNN), a novel memristive HNN model with multi-double-scroll attractors that has excellent randomness and is suitable for image encryption application.
Abstract: Memristors are widely considered to be promising candidates to mimic biological synapses. In this paper, by introducing a non-ideal flux-controlled memristor model into a Hopfield neural network (HNN), a novel memristive HNN model with multi-double-scroll attractors is constructed. The parity of the number of double scrolls can be flexibly controlled by the internal parameters of the memristor. Through theoretical analysis and numerical simulation, various coexisting attractors and amplitude control are observed. Particularly, the interesting and rare phenomenon of the memristor initial offset boosting coexisting dynamics is discovered, in which the initial offset boosting coexisting double-scroll attractors with banded attraction basins are distributed in a line along the boosting route with the variation of the memristor initial condition. In addition, it is also found that the number of the initial offset boosting coexisting double-scroll attractors is closely related to the total number of scrolls and ultimately tends to infinity with increasing the total number of scrolls, meaning the emergence of extreme multistability. Then, the random performance of the initial offset boosting coexisting double-scroll attractors is tested by the NIST test suite. Moreover, an encryption scheme based on them is also proposed. The obtained results show that they have excellent randomness and are suitable for image encryption application. Finally, numerical simulation results are well demonstrated by circuit experiments, showing the feasibility of the designed memristive multi-double-scroll HNN model.

Journal ArticleDOI
TL;DR: The three fingerprints characteristics are proved for this model according to the definition of the generalized memristor, and this discrete model is applied to Henon map, and a new chaotic map is designed called the discrete Memristor-based Henonmap.
Abstract: The realization of real memristor makes it be a very popular topic in recent years. However, the topic about discrete memristor model is rarely discussed. In this paper, a discrete memristor model is proposed based on the difference theory, and the three fingerprints characteristics are proved for this model according to the definition of the generalized memristor. This discrete model is applied to Henon map, and we designed a new chaotic map called the discrete memristor-based Henon map. Its dynamical behaviors are analyzed by attractor phase diagram, bifurcation diagram, Lyapunov exponent spectrum, and spectral entropy complexity algorithm. Simulation results show the performance of Henon map is improved by applying the discrete memristor.

Journal ArticleDOI
TL;DR: A memristor-based reservoir computing (RC) system that can potentially analyze neural signals in real-time and can be directly driven by emulated neural spikes, where the Memristor state reflects temporal features in the neural spike train.
Abstract: The ability to efficiently analyze the activities of biological neural networks can significantly promote our understanding of neural communications and functionalities. However, conventional neural signal analysis approaches need to transmit and store large amounts of raw recording data, followed by extensive processing offline, posing significant challenges to the hardware and preventing real-time analysis and feedback. Here, we demonstrate a memristor-based reservoir computing (RC) system that can potentially analyze neural signals in real-time. We show that the perovskite halide-based memristor can be directly driven by emulated neural spikes, where the memristor state reflects temporal features in the neural spike train. The RC system is successfully used to recognize neural firing patterns, monitor the transition of the firing patterns, and identify neural synchronization states among different neurons. Advanced neuroelectronic systems with such memristor networks can enable efficient neural signal analysis with high spatiotemporal precision, and possibly closed-loop feedback control.

Journal ArticleDOI
19 May 2020
TL;DR: The concept of the sneak-path current issue and solutions proposed to solve it are presented, and some typical and promising devices are selected, and their structures and properties are presented in detail.
Abstract: Since the emergence of memristors (or memristive devices), how to integrate them into arrays has been widely investigated. After years of research, memristor crossbar arrays have been proposed and realized with potential applications in nonvolatile memory, logic and neuromorphic computing systems. Despite the promising prospects of memristor crossbar arrays, one of the main obstacles for their development is the so-called sneak-path current causing cross-talk interference between adjacent memory cells and thus may result in misinterpretation which greatly influences the operation of memristor crossbar arrays. Solving the sneak-path current issue, the power consumption of the array will immensely decrease, and the reliability and stability will simultaneously increase. In order to suppress the sneak-path current, various solutions have been provided. So far, some reviews have considered some of these solutions and established a sophisticated classification, including 1D1M, 1T1M, 1S1M (D: diode, M: memristor, T: transistor, S: selector), self-selective and self-rectifying memristors. Recently, a mass of studies have been additionally reported. This review thus attempts to provide a survey on these new findings, by highlighting the latest research progress realized for relieving the sneak-path issue. Here, we first present the concept of the sneak-path current issue and solutions proposed to solve it. Consequently, we select some typical and promising devices, and present their structures and properties in detail. Then, the latest research activities focusing on single-device structures are introduced taking into account the mechanisms underlying these devices. Finally, we summarize the properties and perspectives of these solutions.

Journal ArticleDOI
TL;DR: This paper aims to design a memristor-based sparse compact convolutional neural network (MSCCNN) to reduce the number of memristors and achieves superior accuracy rates while greatly reducing the scale of the hardware circuit.
Abstract: Memristor has been widely studied for hardware implementation of neural networks due to the advantages of nanometer size, low power consumption, fast switching speed and functional similarity to biological synapse. However, it is difficult to realize memristor-based deep neural networks for there exist a large number of network parameters in general structures such as LeNet, FCN, etc. To mitigate this problem, this paper aims to design a memristor-based sparse compact convolutional neural network (MSCCNN) to reduce the number of memristors. We firstly use an average pooling and $1\times 1$ convolutional layer to replace fully connected layers. Meanwhile, depthwise separation convolution is utilized to replace traditional convolution to further reduce the number of parameters. Furthermore, a network pruning method is adopted to remove the redundant memristor crossbars for depthwise separation convolutional layers. Therefore, a more compact network structure is obtained while the recognition accuracy remaining unchanged. Simulation results show that the designed model achieves superior accuracy rates while greatly reducing the scale of the hardware circuit. Compared with traditional designs of memristor-based CNN, our proposed model has smaller area and lower power consumption.

Journal ArticleDOI
TL;DR: Atomic layer deposited HfO2-based memristor synaptic arrays are fabricated and successfully emulate paired-pulse facilitation (PPF), post-tetanic potentiation (PTP), spike-timing-dependent plasticity (STDP), short-term potentation (STP), long-term potency (LTP), and transition from STP to LTP with rehearsals.
Abstract: The development of bioinspired electronic devices that can mimic the biological synapses is an essential step towards the development of efficient neuromorphic systems to simulate the functions of the human brain. Among various materials that can be utilized to attain electronic synapses, the existing semiconductor industry-compatible conventional materials are more favorable due to their low cost, easy fabrication and reliable switching properties. In this work, atomic layer deposited HfO2-based memristor synaptic arrays are fabricated. The coexistence of threshold switching (TS) and memory switching (MS) behaviors is obtained by modulating the device current. The TS characteristics are exploited to emulate essential synaptic functions. The Ag diffusive dynamics of our electronic synapses, analogous to the Ca2+ dynamics in biological synapses, is utilized to emulate synaptic functions. Electronic synapses successfully emulate paired-pulse facilitation (PPF), post-tetanic potentiation (PTP), spike-timing-dependent plasticity (STDP), short-term potentiation (STP), long-term potentiation (LTP) and transition from STP to LTP with rehearsals. The psychological memorization model of short-term memory (STM) to long-term memory (LTM) transition is mimicked by image memorization in crossbar array devices. Reliable and repeatable bipolar MS behaviors with a low operating voltage are obtained by a higher compliance current for energy-efficient nonvolatile memory applications.