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Metal gate

About: Metal gate is a research topic. Over the lifetime, 12512 publications have been published within this topic receiving 184228 citations.


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01 Jan 1987
TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO-TERMINAL MOS STRUCTURE 3. THE THREE-TERMINAL MOS STRUCTURE 4. THE FOUR-TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION-IMPLANTED CHANNELS 6. SMALL-DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION - LARGE-SIGNAL MODELING 8. SMALL-SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH-FREQUENCY SMALL-SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION

3,156 citations

Patent
20 Oct 2008
TL;DR: In this article, a method for fabricating an AMOLED pixel includes forming a transparent semiconductor layer on a substrate and forming a first channel layer of the switch TFT, a lower electrode of a storage capacitor and a second channel of a driving TFT.
Abstract: A method for fabricating an AMOLED pixel includes forming a transparent semiconductor layer on a substrate and forming a first channel layer of the switch TFT, a lower electrode of a storage capacitor and a second channel layer of a driving TFT. A first dielectric layer is formed over the substrate. A first opaque metal gate of the switch TFT, a second opaque metal gate of the driving TFT and a scan line are formed on the first dielectric layer. A first source and a first drain of the switch TFT are formed in the first channel layer and a second source and a second drain of the switch TFT are formed in the second channel layer. A patterned transparent metal layer is formed on the first dielectric layer. A data line is formed over the substrate. An OLED is formed over the substrate.

1,016 citations

Proceedings ArticleDOI
01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

973 citations

Journal ArticleDOI
TL;DR: In this paper, an MOS transistor with 10−nm silicon dioxide as gate insulator and 10 −nm palladium as gate electrode was fabricated and the threshold voltage of this transistor was found to be a function of the partial pressure of hydrogen in the ambient atmosphere.
Abstract: An MOS transistor in silicon with 10−nm silicon dioxide as gate insulator and 10−nm palladium as gate electrode was fabricated. The threshold voltage of this transistor was found to be a function of the partial pressure of hydrogen in the ambient atmosphere. At a device temperature of 150 °C it was possible to detect 40 ppm hydrogen gas in air with response times less than 2 min.

707 citations

Journal ArticleDOI
Hon-Sum Philip Wong1
TL;DR: In this paper, the authors focus on approaches to continue CMOS scaling by introducing new device structures and new materials, including high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET and strained-silicon FET.
Abstract: This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

644 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202318
202260
202194
2020140
2019214
2018211