Minimum weight

About: Minimum weight is a research topic. Over the lifetime, 2002 publications have been published within this topic receiving 28244 citations.

Using genetic algorithm for the optimization of seismic behavior of steel planar frames with semi-rigid connections

Abstract: Beam-column connections have a significant role in the results of the analysis and the design of steel frames. In this paper, a genetic algorithm has been used for the non-linear analysis and design of steel frames. For minimizing the weight of frames, while satisfying the applied constraints and restraints such as the limits of normal and combined stresses, criteria such as target displacement(s) and the number and locations of plastic hinges were used. To analyze and design the frame elements, I and box-shaped standard sections were used for beams and columns, respectively. Finally, some clues for finding optimizing semi-rigid connection stiffness values for beam-to-column connections have been obtained. The degrees of these rigidities are obtained by a genetic algorithm during the procedure of optimization in order to reach a frame with the minimum weight. SAP2000 structural analysis program was used to perform modal analysis and linear and non-linear static solutions as well as the design of the elements. A MATLAB program was written for the process of optimization. The procedure of optimization was based on a weight minimization carried out for 9 steel frames. Thus, the optimum connection stiffness could be obtained for minimizing the weight of the structure. The results show that the non-linear analysis gives less weight for short period frames with semi-rigid connections compared to those of linear ones. However, by increasing the periods of frames, much less weights are obtained in the case of non-linear analysis with semi-rigid connections.

Arithmetic logic units with high error detection rates to counteract fault attacks

Abstract: Modern security-aware embedded systems need protection against fault attacks. These attacks rely on intentionally induced faults. Such intentional faults have not only a different origin, but also a different nature than errors that fault-tolerant systems usually have to face. For instance an adversary who attacks the circuit with two lasers can potentially induce two errors at different positions. Such errors can not only defeat simple double modular redundancy schemes, but as we show, also naive schemes based on any linear code over GF(2). In this article, we describe arithmetic logic units (ALUs) which provide high error detection rates even in the presence of such errors. The contribution in this article is threefold. First, we show that the minimum weight of an undetected error is no longer defined by the code distance when certain arithmetic and logic operations are applied to the codewords. As a result, additional hardware is needed to preserve the minimum error weight for a given code. Second, we show that for multi-residue codes, these delicate operations are rare in typical smart card applications. This allows for an efficient time-area trade-off for checking the codewords and thus to significantly reduce the hardware costs for such a protected ALU. Third, we implement the proposed architectures and study the influence of the register file and a multiplier on the area and on the critical path.