Topic
Mixed-signal integrated circuit
About: Mixed-signal integrated circuit is a research topic. Over the lifetime, 8329 publications have been published within this topic receiving 138967 citations. The topic is also known as: mixed-signal circuit & mixed-signal system.
Papers published on a yearly basis
Papers
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01 Aug 2006
TL;DR: During the presentations making part of this tutorial, more attention will be paid to integrated filters (Switched-Capacitor and continuous-time), integrated A/D and D/A converters, and PLLs.
Abstract: What to test and what does test need for a complex mixed-signal ASIC are the two main issues this tutorial will try to focus. It will account for several factors: Stimuli generation. An efficient test procedure would use a single signal especially a signal that is easily supplied to a selected input or generated on-chip. Sufficient access. It is preferable to have access to several internal nodes that the tester can read either sequentially or in parallel. Such access permits selection of convenient test points. Single test output. The output should contain all the information required to interpret test signals. Having the information digitally encoded would also reduce tester requirements. Simple measurement set. This set must contain sufficient information about the circuit under test's operational status. System-level decomposition. An efficient test procedure will employ a system-level strategy for decomposing the ASIC into meaningful parts. This decomposition permits testing of each part using a common procedure. These issues are worth attention for specific circuit classes, since there is no universal method valid for any kind of analog and/or mixed-signal function. These factors and their application for solving testing problems in general or for specific circuits will be presented and discussed. In particular, during the presentations making part of this tutorial, more attention will be paid to integrated filters (Switched-Capacitor and continuous-time), integrated A/D and D/A converters, and PLLs.
02 Sep 2001
TL;DR: A novel technique is illustrated to implement fault-tolerant circuits using on-line testing and a reconfiguration technique to by-pass the erroneous unit and a maximum of 40% is saved from the area required for integration, while 33% power reduction is achieved.
Abstract: In this paper, a novel technique is illustrated to implement fault-tolerant circuits. On-line testing is used to detect errors and a reconfiguration technique is applied to by-pass the erroneous unit. The main characteristics of this technique are the reduced power dissipation compared to formal implementations and the minimum required time to perform the reconfiguration process. Application of this technique on FIRs is illustrated and a maximum of 40% is saved from the area required for integration, while 33% power reduction is achieved.
Patent•
NEC1
TL;DR: In this paper, a semi-conductor integrated circuit device is implemented in the test mode of the internal circuit due to the fact that it permits a part of region belonging to the integrated circuit devices to allocate to outer memory space.
Abstract: In a semi-conductor integrated circuit device, a memory space provided with the integrated circuit device is not occupied by space for testing the integrated circuit device as the testing memory space. In the test mode of the semi-conductor integrated circuit device, test of internal circuit is capable of being implemented due to the fact that it permits a part of region belonging to the integrated circuit device to allocate to outer memory space. While in a normal operation mode, degree of freedom of design of the integrated circuit device is increased by releasing the testing memory space.
01 Jan 2018
TL;DR: This article proposes a novel formal method for computing the coverage of architectural power states for power management logic having analog components like LDOs and PLLs and the efficacy has been shown using an industry level case-study.
Abstract: Due to the increasing complexity in the power management logic of low-power designs, formal validation of the architectural power intent, comprising of both digital and analog power management features, is becoming a crucial task. Consequently, the formal verification frontier has also been extended, in recent times, to ensure the correctness for analog as well as digital power intent. The quality of verification can be evaluated by formal coverage analysis which can be determined from the reachability of safe global power states by the power manager. This article proposes a novel formal method for computing the coverage of architectural power states for power management logic having analog components like LDOs and PLLs. The efficacy of the proposed method has been shown using an industry level case-study.
18 Oct 2004
TL;DR: A 5V 8b 40Msamples/s pipelined A/D converter contains seven stages and each stage realizes a resolution of 1.5bit to reduce both linear and nonlinear errors in ADC design.
Abstract: In this paper, a 5V 8b 40Msamples/s pipelined A/D converter is presented The A/D converter contains seven stages and each stage realizes a resolution of 15bit To reduce both linear and nonlinear errors, bottom-plate sampling, bootstrap and digital correction techniques are applied in ADC design Accurate clocks are necessary for those techniques Experiment results are obtained, with 1MHz input signal, the ADC acquired SNDR of 482dB SFDR of 582dB and 78 ENOB The chip is fabricated in 035 /spl mu/m N-well CMOS technology and occupies an area of 4 mm/sup 2/