ModelSim

About: ModelSim is a research topic. Over the lifetime, 1331 publications have been published within this topic receiving 5029 citations.

FPGA-Based Sensorless PMSM Speed Control Using Reduced-Order Extended Kalman Filters

Abstract: This paper presents the design and implementation of a field-programmable gate array (FPGA)-based architecture for the speed control of sensorless permanent-magnet synchronous motor (PMSM) drives For the reduction of computation resources, as well as accuracy improvement in the rotor position estimation, a parallel reduced-order extended Kalman filter (EKF) is proposed in this work Compared with an EKF, the system order is reduced and the iteration process is greatly simplified, resulting in significant savings of resource utility, while maintaining high estimation performance The whole control system includes a current-control-and-coordinate-transformation unit, a proportional-integral (PI) speed controller, and other accessory modules, all implemented in a single FPGA chip A hardware description language is adopted to describe advantageous features of the proposed control system Moreover, the finite-state-machine method is applied with the purpose to reduce logic elements used in the FPGA chip The validity of the approach is verified through simulation based on the Modelsim/Simulink cosimulation method Finally, experimental results are obtained on an FPGA platform with an inverter-fed PMSM to show the feasibility and effectiveness of the proposed system-on-programmable-chip for PMSM drives

Architectural-space exploration of approximate multipliers

Abstract: This paper presents an architectural-space exploration methodology for designing approximate multipliers. Unlike state-of-the-art, our methodology generates various design points by adapting three key parameters: (1) different types of elementary approximate multiply modules, (2) different types of elementary adder modules for summing the partial products, and (3) selection of bits for approximation in a wide-bit multiplier design. Generation and exploration of such a design space enables a wide-range of multipliers with varying approximation levels, each exhibiting distinct area, power, and output quality, and thereby facilitates approximate computing at higher abstraction levels. We synthesized our designs using Synopsys Design Compiler with a TSMC 45nm technology library and verified using ModelSim gate-level simulations. Power and quality evaluations for various designs are performed using PrimeTime and behavioral models, respectively. The selected designs are then deployed in a JPEG application. For reproducibility and to facilitate further research and development at higher abstraction layers, we have released the RTL and behavioral models of these approximate multipliers and adders as an open-source library at https://sourceforge.net/projects/lpaclib/.

FPGA implementation of AES encryption and decryption

Abstract: Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). ModelSim SE PLUS 5.7g software is used for simulation and optimization of the synthesizable VHDL code. Synthesizing and implementation (i.e. Translate, Map and Place and Route) of the code is carried out on Xilinx - Project Navigator, ISE 8.2i suite. All the transformations of both Encryption and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. Xilinx XC3S400 device of Spartan Family is used for hardware evaluation. This paper proposes a method to integrate the AES encrypter and the AES decrypter. This method can make it a very low-complexity architecture, especially in saving the hardware resource in implementing the AES (Inv) Sub Bytes module and (Inv) Mix columns module etc. Most designed modules can be used for both AES encryption and decryption. Besides, the architecture can still deliver a high data rate in both encryption/decryption operations. The proposed architecture is suited for hardware-critical applications, such as smart card, PDA, and mobile phone, etc.

Hardware Implementation of RFID Mutual Authentication Protocol

Abstract: Radio-frequency identification (RFID) is a wireless technology that utilizes radio communication to identify objects with a unique electrical identity. The widespread deployment of RFID technologies may generate new threats to security and user privacy. One of the main drawbacks of RFID technology is the weak authentication systems between a reader and a tag. In general, ?weak? authentication systems that either leak the password directly over the network or leak sufficient information while performing authentication allow intruders to deduce or guess the password. In this paper, we study the RFID tag-reader mutual authentication scheme. A hardware implementation of the mutual authentication protocol for the RFID system is proposed. The proposed system was simulated using Modelsim XE II and synthesized using Xilinx synthesis technology. The system has been successfully implemented in hardware using an Altera DE2 board that included an Altera Cyclone II field-programmable gate array (FPGA). Finally, the output waveforms from the FPGA were displayed on the 16702A logic analysis system for real-time verification.