Showing papers on "MOSFET published in 1970"

Stabilized complementary micro-power square wave oscillator

Abstract: A square wave oscillator is shown utilizing a P channel and an N channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) in combination with a quartz crystal for generating a frequency stabilized square wave signal suitable for use in a wristwatch.

Complementary mosfet integrated circuit memory

Abstract: A random access nondestructive voltage readout complementary MOSFET memory fabricated on a single integrated circuit ''''chip, '''' including not only a plurality of identical memory cells arranged in a matrix array, but also the digital address decoding logic circuitry as well as the input/output buffer circuitry including data line driver circuits insulating the memory cell array from external data lines and input/output control logic circuits insulating the address decoding logic circuitry and the data line driver circuits from external read/write control and strobe input sources. Both N-channel and P-channel MOSFETS are fabricated adjacent to one another as complementary pairs on the same ''''chip'''' with the exclusion of at least one guard ring diffusion region between adjacent drain diffusion regions of the complementary pairs by the inclusion of a relatively thick oxide layer (15-20 KA.) which operates to minimize internal interconnection line capacitance and parasitic surface channels. The data line drivers are bidirectional to provide nondestructive readout, fast readout response, noisy immunity and low-input capacitance. Each memory cell is comprised of two pairs of complementary MOSFETS coupled together as cross-coupled inverter circuits. Additionally, each cell is provided with a pair of parallely connected complementary MOSFETS acting as an input/output transmission switch and are coupled to a common input/output internal data line and operated by separate address command signals from the address decoding logic circuit. Another pair of parallely connected complementary MOSFETS are coupled to the memory cell as a feedback transmission switch and are operated by still other separate address command signals from the address decoding logic circuit. The address command logic utilized to operate the parallely connected pairs comprising the input/output transmission switch and the feedback transmission switch is timed to permit nondestructive readout of the memory cell.

Diffusion guarded metal-oxide-silicon field effect transistors

Abstract: Metal-oxide-silicon field effect transistors (MOSFET) are shown utilizing diffusion guarding of the gate electrode of a MOSFET device and utilizing the drain of one MOSFET device as the source of the next integrally formed MOSFET device. Other types of isolation shown include the surrounding of a functional unit with a source diffusion area, and/or permanently connecting a gate electrode to a potential level for preventing signal flow past such a gate.

Complementary enhancement and depletion mosfets with common gate and channel region, the depletion mosfet also being a jfet

Abstract: A semiconductor device comprising a pair of FET''s having a common electrode has operating characteristics similar to paired complementary FET''s. In one embodiment of the invention the device functions as paired IGFET''s, having a common gate electrode, and in a second embodiment the device functions to couple an IGFET to a JGFET.

Mosfet level detector

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) circuit of a type that can be constructed on a single semiconductor substrate. The circuit detects which of three possible conditions is applied to a single input. The circuit will provide a two-bit digital output signal indicative of the input condition. The circuit includes two MOSFET inverters and a MOSFET resistor divider network.

Mosfet decoder topology

Abstract: The internal capacitance of parallel-gate IGFET structures such as FARMOST NOR gates is substantially reduced by giving the gated area of the substrate a U-shaped configuration so that each gate electrode extends from one leg of the source or drain diffusion to the other leg of the same diffusion across the other diffusion and two gated substrate areas, forming in effect a pair of parallel-connected IGFETS. The reduced capacitance permits the use of much smaller devices requiring much less drive current for the same output current.

MOSFET antiparasitic layer

Abstract: A semiconductor device which is provided, for the purpose of eliminating parasitic MOSFETs formed between at least two circuit elements (such as MOSFET, TRANSISTOR, RESISTOR, and the like) on a semiconductor substrate, with a high impurity concentration layer of the same conduction type as the substrate in a manner such that the layer is not only in the semiconductor substrate between said circuit elements but is also partially overlapped by the circuit element regions.

Mos memory decode

Abstract: A digital decoding system for decoding multi-bit parallel channel digital input signals utilizing a cascaded (series) MOSFET switching circuit of one channel type, a cascoded (parallel) MOSFET switching circuit of the same channel type interconnected to produce a first output when the digital input is at a predetermined value and to produce a second output when the digital input is at all other values. This system provides relatively high speed operation and relatively low power consumption by virtue of complementary circuitry between the cascaded MOSFET switching circuits.

Ion-implanted microwave MOSFET's

Abstract: One-µm n-channel silicon MOSFET's have been fabricated using ion-implantation techniques. The gate structures are self-aligned, with negligible overlapping capacitance. Because of low-temperature aspects of the ion-implantation and post-implantation annealing processes, they can be incorporated at any stage of the conventional silicon technology. The devices exhibit characteristics consistent with the inversion layer electron velocity saturation model. The transconductance in the saturation region is independent of the gate voltage and the channel length. For

Gigahertz p-channel enhancement silicon MOSFET with nonoverlapping gate

Abstract: The technological and electrical parameters of p-channel enhancement silicon m.o.s.f.e.t.s with recessed gates are presented and compared with conventional structures fabricated in a similar manner. In the instance of the nonoverlapping gate the gain-bandwidth product is increased by a factor of about 3. The maximum frequency, as obtained by extrapolation of measurements up to 1 GHz, is f/SUB max//spl ap/3 GHz. If the depletion region of the drain contact is too short to overlap with the gate field, the static characteristics follow a space-charge-limited current-voltage relation. When higher source-drain voltages are applied the normal enhancement-type behavior results but with reverse transconductance y/SUB r/ strongly reduced (by a factor of 8-12 at 1 GHz). A higher circuit stability is obtainable, whereas the parameters y/SUB i/,y/SUB 0/, and y/SUB f/ are only slightly influenced.

Mosfet comparator circuit

Abstract: A metal oxide semiconductor field-effect transistor (MOSFET) digital comparator circuit of a type that can be constructed on a single semiconductor substrate. The circuit includes a series of exclusive OR gates, each of which accepts one bit from each of the binary words being compared. The exclusive OR gates provide an output signal when the bits being compared are not the same. The output signals from each of the exclusive OR gates are applied to a MOSFET NOR gate which will provide an output signal when all of the bits compare.

Field Effect Transistors

Abstract: The field effect transistor is a unipolar (one type carrier) semiconductor device. This device existed as a laboratory device from 1952 to 1962. This is because semiconductor device technology has recently been able to produce that degree of refinement necessary for the production of a thin, lightly doped layer between two more heavily doped layers of opposite type. The fundamental feature? of the FET are presented in this article. MOST or MOSFET is also introduced.

Mosfet asynchronous dynamic binary counter

Abstract: A dynamic binary counter which operates in an asynchronous manner and which can be constructed on a single semiconductor substrate with metal oxide semiconductor field effect transistor (MOSFET) techniques. The counter stages are constructed from three MOSFET inverters and associated gating MOSFET''s to take advantage of the capacitance characteristics of the gates of the MOSFET transistors.

Mosfet FM Tuner Design

Abstract: Dual-gate MOSFETs in an FM tuner provide many advantages over bipolar, junction field-effect, and single-gate MOS field-effect transistors. RF amplification and mixing are aided by use of a low-feedback-capacitance transistor with low noise figure and large dynamic range. A second gate is available for either AGC or local oscillator injection. High stable RF and conversion gains are easily obtained with inexpensive, commercially available coils and without need for neutralization. This paper presents test data and design tips which can be used to design with the SFB8970* dual-gate MOSFET at 100 MHz. The SFB8970 is an N-channel, depletion mode, dual-gate, MOS transistor with integral back-to-back zener diodes between both gates and the source to eliminate the need for special precautionary handling procedures.