Showing papers on "MOSFET published in 1973"

MOS power-on reset circuit

Abstract: An automatic power-on reset circuit adapted for use on complementary MOS integrated circuit semiconductor dies is provided. The circuit includes a voltage reference stage followed by an amplifier stage. A PN diode is coupled in series with a diode-connected MOSFET and a low current MOSFET device to provide a slight overdrive to the P-channel MOSFET of a CMOS inverter, which determines the initial output level thereof. As the voltage applied to the power supply conductor increases, the switching point of the amplifier-inverter stage varies until the output thereof assumes the opposite logic level. This transition of the output of the amplifier inverter stage is applied to wave shaping circuitry and an output circuit which reliably produces the desired reset signal.

Mosbip switching circuit

Abstract: A MOSFET-bipolar switching circuit is disclosed which exhibits the characteristics of impedance mismatch between input and output, simple biasing requirements, high speed, and low standby power. In one embodiment, an N channel MOSFET is connected to provide a shunt feedback path from the collector to the base of an NPN bipolar transistor. A similar circuit results in the combination of a PNP bipolar transistor and a P channel MOSFET. In another embodiment, a pair of complementary MOSFET''s are employed to drive a pair of complementary bipolar transistors. The circuit can be used either as a driver or for logic and may be fabricated in high density, integrated circuits.

Solid state components

Abstract: There is disclosed a method of making a metal-oxide silicon field-effect transistor (MOSFET) capable of delivering substantial power (5 to 10 watts) in the microwave frequency range (about 5 Gigahertz) and operating as an amplifier over a wide bandwidth through a reasonably high input impedance exceeding about 5 ohms. The method is practiced with a layered blank of silicon having, say, an N+ substrate on which is a Player; there is a second N+ layer on the P-layer. Regions, each having a surface for deposit of a drain, are prepared on the second layer. Grooves are etched undercutting these regions so that they overhang the grooves. The gate and drain electrodes are deposited simultaneously by linear beams of vapor at supplementary angles to the prepared surfaces. The angles and the length of the overhangs are such that the gate electrodes extend only along the projections of the edges of the contiguous Players which extend along the groove, minimizing the capacitance between the gate electrode and the other electrodes. There is also disclosed a MOSFET produced in the practice of this invention.

Method of making a planar graded channel MOS transistor

Abstract: The method of fabrication of a planar narrow channel metal oxide semiconductor field effect transistor (MOSFET) by a double diffusion through a self-aligned silicon gate wherein a first type dopant is diffused into the same self-aligned window of the source diffusion already diffused with a second type dopant. The diffused source and drains are self-aligned by means of the silicon gate, thus permitting narrow gate lengths. The diffusion profile is such that the impurity concentration near the source is higher than that near the drain. When a reverse bias is applied between, for example, an n-type drain and a p-type diffused region, the depletion layer cannot widen as much toward the source as a uniform channel because of the impurity concentration profile. Thus a narrow channel length can be used withoout drain-source punch-through at low voltages. Meanwhile, the self-aligned silicon gate permits a close spacing between the source and drain contacts, thus reducing the feedback capacitance between the drain and the gate.

Comparison of MOSFET logic circuits

Abstract: Linear load, depletion-mode load, four-phase dynamic, and complementary MOSFET logic circuits are compared on the basis of power, delay, and density for two specific master slice layouts. The circuits were designed in a common technology base, and normalized power and delay characteristics were calculated by simulation. Chips of 1280 circuits were designed in images having one and two layers of metal, and power versus delay curves were calculated. The effect of an insulating substrate was also considered.

Method of simultaneously making a sigfet and a mosfet

Abstract: A method comprising providing a gate electrode layer of polycrystalline silicon for a SIGFET, depositing a layer of silicon dioxide doped with an impurity of opposite conductivity type on the gate electrode layer and on the surface of the single crystal layer except where the channel of a MOSFET is to be located, diffusing dopant from the doped oxide layer into the gate electrode layer, and into the single crystal layer to form source and drain regions of the transistors, depositing a layer of gate insulating material on the channel region of the MOSFET, and depositing metal on the source and drain regions and on the gates of both transistors.

Mosfet dynamic circuit

Abstract: An integrated complementary MOS transistor circuit is used to divide an input frequency by a factor or two, and similar circuits may be used as counters or shift registers. The circuit is dynamic, low in power consumption, and is based upon one or more inverters which operate in the pulsed power mode.

Distributed mosfet amplifier using microstrip

Abstract: Viewing the input capacitance of a mosfet amplifier stage as an integral part of a microstrip transmission line, leads to a distributed amplifier of simple design. With today's mosfets, a bandwidth in excess of 500 MHz can be achieved ; it will be possible to extend this bandwidth substantially in the future by the use of mosfets with lower input capacitance. In addition, some data are given on transmission lines employing substrates of high dielectric permittivity.

MOSFET circuitry for integrated chips interfacing with higher voltage devices

Abstract: An output terminal of a MOSFET chip is biased to a voltage in excess of the breakdown voltage of a MOSFET; a control transistor and a biased transistor are connected inside of the chip between the terminal and ground, so that for the nonconductive state of the control transistor only a reduced bias is effective across its main electrodes. The output terminal is connected, e.g., to the control circuit for a discharge device and for operating the control circuit between a relatively high firing voltage and a somewhat lower level.

Mosfet devices with trapezoidal gates: I–V characteristics and magnetic sensitivity

Abstract: MOSFET transistors may be fabricated with a variety of channel geometries. The trapezoidal shape for the gate provides useful I – V characteristics. Channel probes are diffused for sensing Hall voltages developed across the device channel. This paper matches experimental and theoretical results for trapezoidal-gate, p -channel, enhancement-mode MOSFET devices. A nonparabolic variation of drain current with gate bias is observed. An optimum gate bias for maximum magnetic sensitivity is obtained for MAGFETs. Devices are fabricated with substrates oriented along the (100) and (111) crystallographic planes. A mobility variation with gage bias is required to accurately match the experimental measurements.

N-channel ion-implanted enhancement/depletion MOSFET's

Abstract: The fabrication and performance of n-channel ion-implanted, TTL compatible, enhancement/depletion MOSFET devices and circuits are described. A speed-power product of 10.0 pJ/pF has been experimentally observed.

Simple MOSFET modeling for digital applications

Abstract: The charge-control concept provides a common base for the modeling of both the MOSFET and the bipolar transistor in digital applications. The dominating characteristics of common MOSFET digital circuits are contained in simple device models.

An analytical expression for MOSFET gate leakage current

Abstract: Integral expressions for the gate leakage current in a MOSFET are derived on the basis of Schottky emission across the gate insulator and on the internal self-heating due to device power dissipation. Computer evaluation of these integrals yields gate leakage current curves that exhibit the same characteristics observed experimentally.

N-Channel MOSFET field protection by nonmasked boron ion implantation

Abstract: A boron ion implant protects the thick-oxide field regions of n-channel MOSFETs by penetrating the thick oxide and increasing the doping at the silicon interface. Active devices, with thin oxide in their gate regions, are not greatly affected because the implant lies buried beneath their channels. The method is compatible with standard four-mask FET processing, adding no new masking steps. Measurements of field properties were made on FET devices with thick oxides in their gate regions. Measurements are also reported for normal thin-oxide devices. The implant effect is characterized by the difference in properties between implanted and unimplanted devices on the same wafers. the degree of protection as a function of both implant dose and energy is reported over a wide range. The results are compared with calculations that accurately account for the nonuniform profile, with good agreement. Field protection, as measured by the thick-oxide threshold voltage, has a sharp peak at a well-defined energy. At energies below the peak, too many ions stop in the oxide; above the peak, they lie too deep in the silicon. Threshold voltages and transconductance of thin-oxide devices are unaffected, but the threshold voltage sensitivity to substrate bias is increased somewhat.

Estimation of the impurity redistribution in silicon substrates from MOSFET characteristics

Abstract: The impurity redistribution in silicon substrates of MOSFET's is estimated from the measurement of dc voltage-current characteristics using the exact theory of the effect of substrate bias. The usefulness of the present method depends upon the acceptability of substituting the Fermi potential before thermal treatments for that after thermal treatments, which then allows for the direct calculation of the impurity concentration. The accuracy of the present method is given theoretically by the discussion of relative errors.

Three-mask self-aligned MOS technology

Abstract: A three-mask process has been developed which permits one to fabricate MOSFET or integrated circuits with self-aligned gate, reduce capacitance, and flatter surface topology. Ion implantation and silicon nitride layers were employed in this process.

MOSFET surface wave detectors for high frequency signal processing

Abstract: The piezoresistance effect in Si-MOSFET structures is used for the detection of Rayleigh surface waves launched on a silicon substrate. The semiconductor devices are MOSFET N and P-channel inversion layers, the channel length is along the direction of the wave propagation and many elementary detectors have been disposed along the propagation path in order to realize tapped delay lines. Theoretical and experimental results are given for the conversion efficiency, bandwidth, sensitivity and dynamic range for a single N or P channel device. Results are presented also for an array of detectors operating as a variable delay line and as a correlator for a 50 MHz bit rate waveform.