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Showing papers on "MOSFET published in 1974"


Journal ArticleDOI
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Abstract: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.

3,008 citations


Patent
John K. Buchanan1
03 Jun 1974
TL;DR: In this article, a MOSFET voltage booster circuit generates a stepped up DC voltage from a lower magnitude supply voltage and a periodic input signal using free-running oscillator circuits.
Abstract: A MOSFET voltage booster circuit generates a stepped up DC voltage from a lower magnitude supply voltage and a periodic input signal. A plurality of such MOSFET voltage booster circuits, which are formed only from components integrated in the MOSFET integrated circuit chip, may be formed on the chip near corresponding sections of circuitry requiring a high DC bias signal. A free-running oscillator circuit may provide the required periodic input signal.

50 citations


Patent
Minoru Fujita1
08 Aug 1974
TL;DR: In this paper, a multi-level voltage supply for liquid crystal display devices employs complementary metal-oxide-semiconductor field effect transistors, which are connected in series with each other.
Abstract: A multi-level voltage supply for liquid crystal display devices employs complementary metal-oxide-semiconductor field-effect transistors. The supply circuit proper includes a p type and an n type MOSFET which are connected in series with each other. A plurality of n-type MOSFETs are grouped together in pairs with their source and gate electrodes connected together and being connected in parallel with the first-mentioned n-type MOSFET. A plurality of voltage levels are applied to the circuit, the lowest of which is applied to the first-mentioned n-type MOSFET. Intermediate voltage levels are applied to the plural parts of n-type MOSFETs. Multi-level voltages for driving the liquid crystal display devices are provided at the connection point of the P-type MOSFET and the N-type MOSFETs of the plurality. As a result, it is possible to prevent the flow of a D.C. current between the lowest level voltage source and the intermediate level voltage source.

33 citations


Journal ArticleDOI
TL;DR: In this article, a MOSFET model that is capable of handling drain current above 10-10A within the temperature range of 220-340 K is proposed, where surface potentials at source and pinchoff points are used for the purpose of obtaining a smooth connection between the current solutions in the tail and the saturation regions.
Abstract: A MOSFET model that is capable of handling the drain current above 10-10A within the temperature range of 220-340 K is proposed. The key feature of the model is that surface potentials at source and pinchoff points are used for the purpose of obtaining a smooth connection between the current solutions in the tail and the saturation regions. Comparison of the model with experiments has been carried out using n-channel MOSFET's with 7 × 1013, 7 × 1014, and 4 × 1015cm-3substrate impurity concentration and 675-, 1470-, and 5030-A gate-oxide thickness. The theoretical calculations are in excellent agreement with the experimental measurements. It is shown that low-level current has a strong influence on the low-voltage static inverter circuit and dynamic memory.

32 citations


Patent
06 Sep 1974
TL;DR: In this article, a polycrystalline silicon current limiting resistor is connected between the drain of the pull-up MOSFET and the supply voltage conductor to provide a closer tolerance output current than is normally feasible for state-of-the-art MOS-FET manufacturing processes.
Abstract: An MOS push-pull driver circuit includes a pull up MOSFET and a pull-down MOSFET coupled to an output node A polycrystalline silicon current limiting resistor is connected between the drain of the pull-up MOSFET and the supply voltage conductor to provide a closer tolerance output current than is normally feasible for state-of-the-art MOSFET manufacturing processes

31 citations


Patent
Watrous Willis George1
13 Mar 1974
TL;DR: An n-channel MOSFET transistor which includes doping of previously formed source and drain elements with a heavy diffusion of phosphorous or arsenic creating n + + regions in the source.
Abstract: An n channel MOSFET transistor which includes doping of previously formed source and drain elements with a heavy diffusion of phosphorous or arsenic creating n + + regions in the source and drain. The extra diffusion step is preferably accomplished just prior to contact metalization.

26 citations


Journal ArticleDOI
TL;DR: In this article, a design for an infrared sensing MOSFET (IRFET) is described, which is ideal for infrared imaging and target tracking applications employing a large-scale integrated array.
Abstract: A design is described for an infrared sensing MOSFET (IRFET). The high-gain high-resolution dc or static readout and inherent integrating and memory characteristics of the infrared sensing MOSFET should make it ideal for infrared imaging and target tracking applications employing a large-scale integrated array. The devices are based on silicon MOSFET technology where large-scale integrated arrays are routinely fabricated.

23 citations


Patent
11 Apr 1974
TL;DR: In this paper, a bootstrap inverter is cascaded with a push-pull amplifier through a MOSFET, interconnecting particularly the output mode of the inverter with one input node of the pushpull amplifier, the output nodes of both amplifiers swing between ground and voltage larger than Vg.
Abstract: A bootstrap inverter is cascaded with a bootstrapping push-pull amplifier through a MOSFET, interconnecting particularly the output mode of the inverter with one input node of the push-pull amplifier, the output nodes of both amplifiers swing between ground and Vg, the input node of the push-pull stage swings between near ground and a voltage larger than Vg. The MOSFETs in the amplifiers have capacitive source-to-gate coupling for bootstrap action and conduction at below saturation current levels in the steady state. Two such buffer circuits can be combined to establish a two phase, buffered clock.

23 citations


Proceedings ArticleDOI
01 Dec 1974
TL;DR: In this article, a short-channel ion-implanted MOSFET with relatively deep junctions is considered and four device parameters are considered: threshold and transconductance reduction, sub-threshold turn-on, and punch-through.
Abstract: This paper discusses design considerations for short-channel ion-implanted MOSFET devices with relatively deep junctions. Four device parameters are considered: threshold and transconductance reduction, sub-threshold turn-on, and punch-through. Channel-length variations affect power and performance tolerances of enhancement/ depletion logic NOR gates in two ways: first, down-level current is inversely proportional to channel length; second, short-channel physical effects cause variations in transconductance and threshold voltage. It will be demonstrated that threshold and transconductance variations in short-channel devices tend to offset one another so their net contributions to tolerances on such circuit parameters as switching speed, down-level power and down-level voltage are negligible. Dual-energy ion implantation is used in the channel regions — a shallow implant to control threshold voltage, and a deep implant to control punch-through voltage. Hence high-resistivity (15 ohm-cm) substrates can be used to reduce junction capacitance. These implants are shown to have little effect on short-channel properties other than punch-through because the doses are low. Low channel doping and the relatively deep junctions contribute to a desirable, steep device turn-on characteristic. We concluded that short-channel effects do not have to be avoided in the design of small MOSFET devices. Using ion implantation and careful design, circuit tolerances can be maintained allowing parameters such as junction depth to be optimized for other criteria such as metallurgy compatibility.

19 citations


Proceedings ArticleDOI
01 Dec 1974
TL;DR: In this article, a novel form of integrated injection logic is described which has significant advantages over its conventional counterpart in packing density and power-delay product, and a viable technology for Schottky Barrier Diodes has been demonstrated and an optimised structure has been designed.
Abstract: A novel form of integrated injection logic is described which has significant advantages over its conventional counterpart in packing density and power-delay product. The structure is formed from two epitaxial layers on a heavily doped p type sub-strate. The p type epitaxial layer, which forms the base of the npn transistor, is lightly doped, allowing the fabrication of Schottky contacts. This gives rise to an extremely powerful multi-input, multi-output logic element on a single base land. The fundamental SFL structure has been successfully demonstrated. Gates and a ring oscillator have been operated and a reduction in power-delay product has been shown. A viable technology for Schottky Barrier Diodes has been demonstrated and an optimised structure has been designed.

18 citations


Patent
Larry R. Hite1
12 Sep 1974
TL;DR: In this article, a four quadrant multiplier with a pair of MOSFET differential amplifiers formed with MOS-FET current sources for both amplifiers is considered, where current through one FET and a second FET of each amplifier are modulated in response to second multiplier input voltages 180° out of phase.
Abstract: A four quadrant multiplier in which a semiconductor chip has a pair of MOSFET differential amplifiers formed with MOSFET current sources for both amplifiers. Currents through the differential amplifiers are modulated 180° out of phase in response to first multiplier input voltages. Currents through one FET of each said amplifier and a second FET of each said amplifier are modulated in response to second multiplier input voltages 180° out of phase. Active MOSFETs form a load connected to the drains of the first FET of both amplifiers while other active MOSFETs form a load connected to the drain of the second FET of both amplifiers to produce a product voltage across at least one of the load FETs.

Proceedings ArticleDOI
J. Tihanyi1, H. Schlotterer1
01 Dec 1974
TL;DR: The specific current voltage characteristics of ESFI MOS transistors are discussed in this paper, where the I D -U D -characteristics could be simulated by a computer model based on the physical effects.
Abstract: The specific current voltage characteristics of ESFI (or SOS) MOS Transistors are shown and explained. The ESFI MOSTs are produced on silicon islands: in most applications the electrical substrate is at floating potential. This results two effects: At first a threshold voltage change occurs with increasing drain voltage producing a kink in the current curve; if the drain voltage further increases a parasitic bipolar transistor begins to work and effects another kink or bend in the curve. The finite volume and charge below the gate causes a reduced influence of the substrate on the charge in the channel; therefore at higher substrate doping ESFI MOSTs show a higher transconductance than the corresponding bulk transistors. All these effects are described theoretically; the I D -U D -characteristics could be simulated by a computer model based on the physical effects.

Journal ArticleDOI
Toshiaki Masuhara1, J. Etoh
TL;DR: In this paper, low-level currents in MOSFETs with single and double layer implanted impurities are discussed, and double-layer implantation, which consists of a phosphorus layer just below the surface of silicon and an equal dose of boron layer inside the silicon substrate, causes less steep log n SF -V G curves with negligible threshold shift.
Abstract: Low-level currents in ion-implanted MOSFET are of special importance in the design of low-voltage MOSFET circuits. In this paper, low-level currents in MOSFET with single and double layer implanted impurities are discussed. A single boron layer in n-channel MOSFET causes positive threshold shift and less steep log n SF (surface electron density)-V G (gate voltage) curves compared with unimplanted MOSFET. Single phosphorus implantation gives rise to negative-threshold shift, but residual current occurs. By compensating for the distribution tail of the main impurity by the opposite type impurity, the log n SF -V G curves shift in an almost parallel manner. Double-layer implantation, which consists of a phosphorus layer just below the surface of silicon and an equal dose of boron layer inside the silicon substrate, causes less steep log n SF -V G curves with negligible threshold shift.

Proceedings ArticleDOI
01 Jan 1974
TL;DR: In this article, the use of an impurity doped silicon MOSFET as an infrared detector (IRFET) has been proposed, which is an integrating static read only memory element whose conductance is modulated by infrared radiation.
Abstract: Summary form only given, as follows. The use of an impurity doped silicon MOSFET as an infrared detector (IRFET) has recently been proposed. (1) This report will give a description of the operation of this new type of infrared detector and provide experimental verification of the design. The IRFET is an integrating static read only memory element whose conductance is modulated by infrared radiation. Operation has been observed and characterized using the gold acceptor level and gold donor level in the near infrared wavelength range from 1.0 to 3.0 microns. It will be shown from pulsed capacitance measurements on MOS capacitors and from measurement of the IRFET response that the characteristics of the gold impurity center in the surface space charge region correspond to the results observed previously for the center in bulk silicon. Operation of the IRFET can then be described on the basis of a simple model where the change in charge state of the impurity center in the surface space charge region due to photoionization modulates the threshold voltage of the MOSFET and thus conductance of the device. The IRFET has a very high gain and responsivities of 10 milliwatts/microjoule are easily achieved. Standard silicon MOSFET technology is employed and it should be possible to use other impurity centers to extend the response out to a wavelength of 14 microns. Applications in large scale integrated infrared imaging and target tracking arrays are anticipated.

Journal ArticleDOI
TL;DR: In this paper, the threshold voltage of a MOSFET at 4.2 K is affected by the particular bias condition present while the device is being cooled, and the model based on stored bulk-charge is used.
Abstract: The threshold voltage of a MOSFET at 4.2 K is affected by the particular bias condition present while the device is being cooled. Measurements disagree with a simple model based upon stored bulk-charge.

Patent
23 Dec 1974
TL;DR: In this paper, a static logic circuit utilizing transistors of the MOSFET type includes a high resistance load transistor, a low resistance logic network having a large selfloading capacitance, and a gating transistor connected in series between the network and the load device.
Abstract: A static logic circuit utilizing transistors of the MOSFET type includes a high resistance load transistor, a low resistance logic network having a large self-loading capacitance, and a gating transistor connected in series between the network and the load device. The logic network controls the output voltage across a load capacitor by grounding the load transistor output for selected input data, and the gating transistor is biased to turn OFF when the voltage across the large self-loading capacitance exceeds a predetermined level, thereafter isolating the input network from the load capacitor and speeding up the output transition by decreasing the time required to charge the load capacitor.

Patent
Rodney H. Orgill1
03 Jun 1974
TL;DR: An MOS input latch circuit as discussed by the authors includes cross-coupled logic gates and MOSFETs coupled between the set and reset inputs of the latch circuit formed by the crosscouple logic gates.
Abstract: An MOS input latch circuit includes cross-coupled logic gates and MOSFETs coupled between the set and reset inputs of the latch circuit formed by the cross-coupled logic gates. An output MOSFET connected between an output of the MOSFET latch circuit and an output of one of the logic gates. Each of the logic gates has a MOSFET coupled between its two inputs having its gate electrode coupled to phi 1. The input MOSFETs have their gate electrodes coupled to phi 2 conductor and one of their main electrodes of each is connected to complementary input signal conductors.

Proceedings ArticleDOI
01 Dec 1974
TL;DR: In this paper, a MOS digital capacitor capable of operation at VHF and UHF frequencies is described, made up of a parallel combination of MOS capacitors on a single chip each of which can be individually switched and statically maintained at two distinct RF capacitance values, the maximum binary state being the high frequency MOS inversion capacity and the minimum being that of a deep depletion MOS device.
Abstract: A MOS digital capacitor capable of operation at VHF and UHF frequencies is described. This new device is made up of a parallel combination of MOS capacitors on a single chip each of which can be individually switched and statically maintained at two distinct RF capacitance values, the maximum binary state being the high frequency MOS inversion capacity and the minimum being that of a deep depletion MOS device. Switching is accomplished by on chip MOSFETs.

Proceedings ArticleDOI
01 Dec 1974
TL;DR: In this article, a voltage dependent shift in the I D -V G curves is shown to be a direct consequence of hole degeneracy, which is due to the inadequacy of the conventional depletion load device model.
Abstract: The increased use in production LSI circuits of ion implantation, in particular, the use of the depletion load transistor, has prompted re-examination of conventional MOS theory. For enhancement/depletion mode circuits, discrepancies between measured and predicted characteristics appear due to the inadequacy of the conventional depletion load device model. Calculations are described for p-channel depletion load transistors. Comparison of I D -V G characteristics to experiment are given for several energies and doses. A voltage dependent shift in the I D -V G curves is shown to be a direct consequence of hole degeneracy.

Proceedings ArticleDOI
01 Dec 1974
TL;DR: The drain current versus gate voltage characteristics of ion-implanted buried-channel MOS transistors were measured and compared with a theory based on the in-depth impurity, mobile carrier, potential and mobility distribution.
Abstract: The drain current versus gate voltage characteristics of ion-implanted buried-channel MOS transistors were measured and compared with a theory based on the in-depth impurity, mobile carrier, potential and mobility distribution. In more heavily implanted transistors, a characteristic sub-threshold current almost independent of gate voltage is obtained both experimentally and theoretically. For these cases, a new definition of threshold voltage is suggested. According to their potential distribution at threshold, implanted transistors are classified into three groups. The depths and widths of buried channels fall into the transition region from surface to bulk carrier mobility. Models for the mobility distribution including surface and impurity scattering as well as field dependence were used to calculate the active-region conductance.

Proceedings ArticleDOI
01 Dec 1974
TL;DR: In this paper, a model based on the depletion approximation has been found to be in good agreement with the solution of the Poisson's equation and the experimental results in both the depletion and the inversion regions.
Abstract: The JIGFET is a novel type of depletion MOS transistor formed by the implantation of a channel between source and drain. Because of its high bulk-transconductance, its linearity and low noise, the JIGFET has been thoroughly studied and modelled for linear applications. The model based on the depletion approximation has been found to be in good agreement with the solution of the Poisson's equation and the experimental results in both the depletion and the inversion regions.

Journal ArticleDOI
C Mabilde1
TL;DR: A mosfet voltage follower is described for the use with ultra-microelectrodes and details are given concerning response time, input current and stability.
Abstract: A mosfet voltage follower is described for the use with ultra-microelectrodes. Details are given concerning response time, input current and stability.

01 Mar 1974
TL;DR: A new technique for computing the nonlinear transfer functions of an interacting cascade of nonlinear networks is discussed, and an example of its use given.
Abstract: : A new technique for computing the nonlinear transfer functions of an interacting cascade of nonlinear networks is discussed, and an example of its use given. Experimentally determined nonlinear parameters of a MOSFET tetrode are given, and an equivalent circuit is shown for the device. The programming of some of the software for deriving the parameters of a charge-control bipolar transistor is presented. (Author)

Proceedings ArticleDOI
01 Dec 1974
TL;DR: In this paper, Boron ions are inserted into the channel region of the driver transistors of an n-channel MOS transistor in order to shift the tresbold voltage of the transistors to positive values.
Abstract: In order to obtain enhancement type n-channel MOS transistors in an enhancement-depletion system it is possible to shift the tresbold voltage of the driver transistors to positive values by implanting Boron ions into the channel region of the devices. In this way the advantages of a low bulk doping level are conserved (low parasitic capacitances, low bulk effect …), while the power dissipation-delay product of the circuits is reduced due to the load which is of the current source type.

Journal ArticleDOI
TL;DR: The radiation damage of commercially available n-channel depletion MOSFET's (3N128) up to a dose of 6 Mrad (SiO 2 ) Co-60 γ-rays was investigated in this paper.
Abstract: The radiation damage of commercially available n-channel depletion MOSFET's (3N128) is investigated up to a dose of 6 Mrad (SiO 2 ) Co-60 γ-rays. The upper bound of admissible radiation dose for these devices is about 100 krad (SiO 2 ) owing to the decrease of forward transconductance. The change of the turn-on-voltage is less than 1 V C-V-characteristics obtained by measuring the MOS charging current in response to a linear voltage ramp point to the growth of interface states with a monoenergietic level below the conduction band of Si.

Proceedings ArticleDOI
01 Oct 1974
TL;DR: In this article, the effect of process variations on threshold voltage (V T ) of a metal-oxide-silicon-field effect transistor (MOSFET) was discussed.
Abstract: The attainment of low threshold voltage (V T ) for Metal-Oxide-Silicon-Field-Effect-Transistor (MOSFET) devices is being at-temped via four technologies; viz., silicon crystal orientation, composite gate dielectric, silicon gate, and ion implantation. To understand the effect of process variations on V T of a MOS structure, one should review the following equation: V T = Φ ms + Φ B − (Q ox +Q B )/C ox . (1) The threshold voltage (V T ) is essentially the gate voltage re­quired to bring about a strong inversion in MOS structure. The metal-silicon work function (Φ ms ) is a function of gate electrode material (most commonly it is either aluminum or silicon) and to a slight degree, a function of the substrate doping level. For aluminum-silicon (N D ≈ 1015 cm−3) electrode system, Φ ms is around −0. 3 V. If Al electrode is replaced by p-type silicon gate, the Φ ms changes to +0.8 V.1 Thus, by changing the electrode system to silicon-silicon, a reduction of +1.1 V in V T could be observed.