Showing papers on "MOSFET published in 1978"

Subthreshold conduction in MOSFET's

Abstract: The dependence of channel current in subthreshold operation upon drain, gate, and substrate voltages is formulated in terms of a simple model. The basic results are consistent with earlier approaches for long-channel devices. For short-channel devices, the variation of current with drain voltage up to the punch-through voltage is accurately described. The threshold voltage of a short-channel device as a function of applied voltages follows as a natural result of the derivation. Results are presented which confirm the theory over a wide range of drain and gate voltages. With the application of substrate bias it is concluded from the data and the theory that two-dimensional effects can cause dramatic increases in the drain conductance.

A normally-off type buried channel MOSFET for VLSI circuits

Abstract: This paper presents the performance of a buried channel MOSFET (BC-MOSFET) that uses the bulk region as the conducting channel in contrast with the surface channel of the conventional device. Normally-off characteristic has been realized with the p-type silicon gate and the ion-implanted n-channel layer. Fabricated short channel BC-MOSFETs with the gate lengths of 1-3 µ have shown a small shift of threshold voltage with changing the gate length or drain bias. These devices also have high carrier mobility of 750 cm2/v.s and high breakdown voltage compared with those of the conventional device. Minimum delay time of 180 ps was obtained with a 13 stage ring oscillator which was constructed with 1 µ BC-MOSFET.

Device characteristics of short-channel and narrow-width MOSFET's

Abstract: MOS devices have become smaller and smaller as the integrated circuit technology advances. A thorough understanding of the device characteristics of these small-size devices is important. In this paper, three small-geometry effects; namely, short-channel effect (SCE), narrow-width effect (NWE), and minimum-size effect (MSE) (which combines SCE and NWE together) are discussed. The variations of threshold voltage, mobility, and drain current are illustrated for minimum-size devices. The threshold voltage decreases as channel length decreases but increases as device width decreases. Carrier mobility also decreases as the device size becomes small. Simple device models of minimum-size devices are proposed for threshold voltage and carrier mobility. Experimental results of threshold voltage, mobility, and drain current are compared with the calculated results.

GaAs microwave MOSFET's

Abstract: GaAs microwave metal-oxide-semiconductor field-effect transistors (MOSFET's) with plasma-grown native oxides as gate insulator have been fabricated using a low-temperature magnetically controlled plasma-oxidation technique. A small-signal enhancement device with the gate length of 2.0 µm has demonstrated useful unilateral power gains in the 2-8-GHz frequency range. A maximum frequency of oscillation in the enhancement device is 13 GHz. This is the highest in all enhancement-mode GaAs devices reported up to this time. A medium-power depletion device with the gate length of 1.8 µm has the maximum frequency of oscillation of 22 GHz. This value is 10 percent larger than that of the best analogous metal-semiconductor field-effect transistor (MESFET). The intrinsic current-gain cutoff frequency for the depletion MOSFET is 4.5 GHz which is 22 percent higher than that of the MESFET. The superiority of the depletion MOSFET in the small-signal microwave performance over the MESFET results from the smaller gate parasitic capacitance in the MOSFET as compared to the MESFET. The depletion MOSFET has produced 0.4-W output power at 6.5 GHz as a Class A amplifier. Quite a large frequency dispersion of transconductance is observed in the enhancement MOSFET at a frequency range between 10 and 100 kHz and attributed to interface states. The effect of the interface states does not severely restrict the microwave-frequency capabilities of the enhancement MOSFET as well as the depletion MOSFET since the interface states are unable to follow the input-signal variations at high frequencies.

Analysis of the deep depletion MOSFET and the use of the d.c. characteristics for determining bulk-channel charge-coupled device parameters

Abstract: A qualitative and quantitative analysis of the deep depletion MOSFET operated in the regimes of depletion, enhancement and depletion/enhancement, is presented The quantitative analysis presented here does not make any of the simplifications made in some earlier papers, applicable to shallow channel depletion MOSFETs, and uses a four terminal device model so as to provide a complete set of characterisation equations for each mode of operation It is demonstrated that the device parameters of flatband voltage, implanted channel doping and depth, and bulk and surface carrier mobilities, can easily be determined by use of some of the characteristics equations in conjunction with simple measurements made directly from the drain current/drain voltage characteristics Furthermore these parameters are applicable to bulk-channel charge-coupled devices fabricated under the same implantation and drive-in conditions As the device parameters are determined from the drain current/drain voltage characteristics the techniques presented offer an attractive alternative to the more complicated C-V methods used for bulk-channel charge-coupled device characterisation The validity of the model and the techniques used to determine the device parameters is demonstrated by the good agreement between calculated and measured results obtained from fabricated devices

Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides

Abstract: A method for making a semiconductor device is described in which polycrystalline silicon is vacuum deposited and then converted to silicon dioxide thereby providing a number of advantages over direct deposition of silicon dioxide. The method has particular applicability to isoplanar MOSFET integrated circuit manufacturing.

An analysis of the concave MOSFET

Abstract: The electrical characteristics of the concave MOSFET are analyzed by the two-dimensional numerical method and the theoretical result is in reasonable agreement with the experimental result. Even if the channel length of the concave MOSFET is short, the obtained current-voltage characteristics of the concave MOSFET are quite similar to those of the long-channel normal MOSFET and can be approximated by the normal MOSFET formula. In short-channel concave MOSFET's, the threshold voltage lowering due to the short-channel effect is not observed. It is observed that the threshold voltage of the concave MOSFET depends strongly on the substrate bias voltage as compared with the long-channel normal MOSFET. These observed results are followed by the two-dimensional numerical analysis. The increase of the punch-through breakdown voltage as well as that of the surface induced avalanche breakdown voltage of the concave MOSFET is predicted theoretically. The equivalent circuit model of the concave MOSFET is shown and discussed.

MOS RAM with implant forming peripheral depletion MOSFET channels and capacitor bottom electrodes

Abstract: In a one transistor, one capacitor N-channel polysilicon gate MOSFET RAM, having self-aligned contacts to silicon gates, an N-implant is used to both form bottom electrodes of the capacitors and to form depletion mode FET channels in peripheral circuits. Separate polysilicon layers are used for the gates of enhancement mode FETs and for the capacitor upper electrodes and depletion FET gates.

Extremely low current load device for integrated circuit

Abstract: A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.

VMOS Floating gate memory with breakdown voltage lowering region

Abstract: A semiconductor electrically programmable read only memory device (EPROM) utilizes an array of memory cells each in the form of a single V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and word line that extends across the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and word lines by thin oxide layers. A ring of P-type conductive material around the upper end of each V-shaped recess and adjacent its surrounding N-type drain region serves to lower the required programming voltage without increasing the device threshold voltage.

Characterization of the MOSFET Operating in Weak Inversion

Abstract: Publisher Summary This chapter describes the physical properties of the interface between silicon and silicon dioxide in metal-isolator semiconductor transistors and of their influence on the channel current of a MOS transistor, particularly in weak inversion. The channel current consequently, is several orders of magnitude smaller than in the normal operating region and is easily influenced by the nonuniformities in the vicinity of the interface. In order to be able to derive the properties of the interface from the measured weak-inversion current, one has to calculate the theoretical current flowing through the corresponding ideal transistor. To that end, it is necessary to characterize the experimental transistor as accurately as possible. This is done by means of three-terminal capacitance measurements that yield the channel length and the capacitances between different parts of the MOS transistor. The chapter discusses the accurate model for the drain current in a MOSFET, determination of the surface state density from the drain current versus drain voltage measurements in weak inversion, and influence of potential fluctuations on the mobility in weak inversion.

Improved enhancement/depletion GaAs MOSFET using anodic oxide as the gate insulator

Abstract: A GaAs MOSFET with a semi-insulating substrate is described, operating in either the enhancement or the deed depletion modes and showing the highest transconductance reported so far, and a rise time better than 1 ns. The behavior is fully explained by the C/V characteristics of equivalent MOS capacitors.

Dynamic depletion mode: an E/D MOSFET circuit method for improved performance

Abstract: A new method of designing enhancement/depletion (E/D) MOSFET circuits, involving the dynamic or pulsed use of depletion-mode devices, is described. The method can result in improvements in performance and/or power in the design of memory, logic, and driver circuits. The method is compared with the standard approach to the design of E/D circuits. Several circuits designed by the method have been simulated by use of a numerical circuit analysis program and have been placed on an experimental test chip. Theoretical and experimental results are presented.

Method for making a semiconductor device

Abstract: A method for making a semiconductor device is described in which polycrystalline silicon is vacuum deposited and then converted to silicon dioxide thereby providing a number of advantages over direct deposition of silicon dioxide. The method has particular applicability to isoplanar MOSFET integrated circuit manufacturing.

BiMOS micropower ICs

Abstract: Design techniques suitable for micropower integrated circuits are discussed. Some systems require subpicoampere input bias and amplifier, timing, and logic functions with a several hundred milliampere output capability-at a standby current level of a few microamperes. MOSFETs are characterized well into their subthreshold regions and, in concert with standard bipolar devices, are shown to extend the performance capabilities of linear circuit portions. Applications of subthreshold circuits are very broad, however, because the high transconductance-to-current ratios of MOSFET pairs also provide order-of-magnitude improvements in offset temperature-drift and life stability. In combination with bootstrapped input protective networks, subthreshold BiMOS devices can provide operational-amplifier performance normally attained by only die-trimming techniques or hybrid construction. It is shown that the MOSFET is useful not only for its high-impedance input, but also in intermediate and output functions of linear/digital ICs.

MOS addressing circuits for display/memory panels

Abstract: A driving and addressing circuit for applying sustaining, writing and erasing voltages to the cells of a multicelled gas discharge display/memory panel. The voltage generating circuitry is isolated from each panel electrode by a pair of oppositely poled diodes individual to that electrode. The diodes provide low impedance paths for the sustainer current and isolate the electrodes from each other. The writing and erasing voltages are coupled to the electrodes through a plurality of complementary MOSFETs, one per electrode, which eliminate all but one of the diode switch circuits per electrode array of the prior art circuitry. The P-channel and N-channel MOSFETs can be formed on separate integrated circuit chips with one of the pair of the diodes while the other diodes are formed on common anode and common cathode integrated circuit chips. In addition, a portion of the addressing circuitry can be formed on the MOSFET chips. Such a circuit configuration substantially reduces the power requirements and circuit complexity.

Drift compensation circuit for analog memory

Abstract: PURPOSE: To ensure the temperature compensation for the analog quantity at the reading time by applying the gate voltage of the floating gate type MOSFET which is to be an analog memory via the MOSFET featuring the same characteristics at the floating gate type MOSFET. CONSTITUTION: The accumulated analog quantity varies by the reading gate voltage, and accordingly the reading voltage is varied in accordance with the temperature drift. This reading voltage is obtained from the output of MOSFET(T) which is cascade-connected to memory FET. In other words, both the gate voltage applied to MOSFET(T) and the characteristics of the drain current function in the direction where the temperature drift of the memory FET is offset. As a result, the temperature is compensated at the reading time of the analog quantity. COPYRIGHT: (C)1979,JPO&Japio

Method of manufacturing a low voltage n-channel MOSFET device

Abstract: A novel MOSFET circuit and method of manufacture utilizing a double ion implant process for manufacturing a low voltage high performance n-channel device that includes an enhancement transistor inverter combined with a depletion transistor load. The process starts with high resistivity material and uses a first ion implant process to dope the field region and to give the required threshold voltage for an enhancement device. A second ion implant is used to dope the channel region for the depletion device.

Power metal-oxide-semiconductor-field-effect- transistor

Abstract: A planar high power Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) including a substrate with an epitaxial layer on a surface thereof. A gate electrode including a strip of metal extending across a surface of the epitaxial layer and having a plurality of fingers extending therefrom along its length. The gate electrode being electrically insulated from the epitaxial layer by a layer of oxide. A source electrode in the surface of the epitaxial layer including fingers extending therefrom and interdigitating with the fingers of the gate electrode. There are p and n diffusion regions formed in the epitaxial layer except in an area under each of the gate fingers, which area remains undiffused. A drain electrode is connected to the surface of the substrate opposed to the surface upon which the epitaxial layer is deposited. During operation of the MOSFET as the blocking voltage across the transistor increases and the transistor is in the OFF state, the horizontal components of fields from the adjacent and closely spaced p-regions cancel each other so that voltage breakdown due to junction curvature is avoided.

Submicron channel MOSFET's logic under punchthrough

Abstract: The characteristics of n-channel MOSFETs that make use of the punchthrough current are considered in this paper. The current conduction mechanisms of the short channel MOSFET under the bias condition of punchthrough have been studied through the use of two-dimensional computer simulation. Experimental devices with channel lengths as short as 0.5 /spl mu/m were fabricated on a lightly doped substrate. Current-voltage curves of these devices showed pentode-like characteristics for smaller drain biases and triode-like characteristics for larger drain biases. A switching delay as small as 75 ps was obtained for a 13-stage ring oscillator composed of the submicron channel devices.

Thermal-oxide gate GaAs MOSFET's

Abstract: The first thermal-oxide gate GaAs MOSFET of the deep-depletion mode is reported. The gate oxide, which has been grown by the new GaAs oxidation technique in the As 2 O 3 vapor, is so chemically stable that it can be subjected to the fabrication process. Measurement of some dc characteristics of the device fabricated has shown a strikingly suppressed hysteresis.

MOSFET Substrate sensitivity control

Abstract: The sensitivity of the threshold voltage in MOSFET devices to changes in substrate voltage may be reduced at a given temperature by the introduction of sufficiently deep energy level, low diffusivity impurities into the depletion region under the gate of the MOSFET.

Invited) Physics and Device Technology of Silicon on Sapphire

Abstract: Current status of silicon on sapphire technology has been reviewed with emphasis on the following subjects: (a) economical aspects of SOS; material availability and costs, (b) physical limitation to the carrier transport phenomena in epitaxial silicon layer, (c) characterization of SOS; role of crystal defect in silicon film on the physical and electrical properties of silicon layer, (d) device characteristics of MOSFET on SOS wafer; reduction in junction capacitance, lack in the substrate bias effects etc., (e) comparison of SOS LSI with the other bulk LSI's for several basic circuit configurations.

The Multidrain MOS Transistor

Abstract: The multidrain MOS transistor (MD-MOS) improves speed and packing density of the monolithic integrated circuits in the standard N-MOS silicon gate enhancement-depletion technology. In addition, with its modular structure, the MD-MOS gate allows a fast design-to-implementation turraround using symbolic models.

MOS Circuit for generating a square wave form

Abstract: A circuit for generating a square wave form which circuit comprises two MOSFETs and is driven by only one control logic signal. A first MOSFET is connected between a ground potential power supply and the circuit output line while a second MOSFET is connected between the circuit output line and a positive potential power supply. The gate of the second MOSFET is connected to the source of the first MOSFET which has a gate connected to receive the control logic signal. When the logic signal is at a high level, the first MOSFET is turned on and the gate of the second MOSFET is pulled down to ground potential such that the second MOSFET is turned off. Thus, the circuit output line will be near the ground potential. When the logic signal switches to a low level, the first MOSFET is turned off and the voltage across a capacitor which has been charged by a power supply causes the second MOSFET to turn on such that the circuit output line will be near the positive potential. This circuit is typically used to drive capacitive type loads such as those found in gas discharge display devices.

Punch-through MOSFET for high-speed logic

Abstract: This paper will describe punch-through mode operation of a submicron gate MOSFET for high-speed and low-power logic ICs. Switching delays of 90ps and minimum power-delay products of 2fJ have been obtained with ring oscillators.

Complementary MOS memory array including complementary MOS memory cells therefor

Abstract: A memory array employs a plurality of four-transistor storage cells. Each storage cell includes first and second P channel MOSFETs and first and second N channel MOSFETs. The sources of the first and second P channel MOSFETs are connected to a supply conductor. The drain of the first P channel MOSFET is connected to the drain of the first N channel MOSFET. The drain of the second P channel MOSFET is similarly connected to the drain of the second N channel MOSFET. The gates of the first P channel and first N channel MOSFETs are connected together and to the connected drains of the second P channel and second N channel MOSFETs. The gates of the second P channel and second N channel MOSFETs are connected to the drains of the first P channel and first N channel MOSFETs. The source of the first N channel MOSFET is connected to a row line of the memory array and the source of the second N channel MOSFET is connected to a column line of the memory array. In the array, the memory cells in each row share a respective common first conductor, and all of the memory cells in each column share a common second conductor.

Mo gate tetrode

Abstract: The n-channel high-frequency dual-gate MOSFET's or tetrodes made using Mo gate (RMOS) self-aligned processing are described. This includes design and processing considerations, manufacturing yield, and high-frequency performance. Each of the two gates are protected with p-n diode structures which exhibit silicon-controlled rectifier action, UHF data on devices built on epitaxial wafers show high-gain narrow-bandwidth characteristics.

Mis type semiconductor device

Abstract: PURPOSE:To improve a breakdown voltage and to facilitate a manufacturing process by the constitution in which the polycrystalline Si layer which is formed unitarily with the polycrystalline Si layer as a gate electrode is combined with a drain region CONSTITUTION:The polycrystalline Si layer on a channel part, ie the real gate among gate electrodes is formed by a source-side part 9 of a polycrystalline Si layer 4 and is connected to a drain-peripheral part 10 through high resistance of an intrinsic central part 8 so that it is nearly isolated electrically In this case, if the predetermined drain voltage is applied to a drain region 6 through a contact 16, as the drain-peripheral part 11 of the polycrystalline-Si layer 4 is combined through the capacitance in which a gate insulating film 3 is a dielectric, the potential of the drain-peripheral part 11 increases and produces a depletion layer under the drain-peripheral part 11 Consequently, the depletion layer from the drain region 6 easily extends under the drain-peripheral part 11 Then a junction breakdown voltage is increased and the breakdown voltage of the whole MOSFET can be increased

Velocity saturation effects in n-channel deep-depletion SOS/MOSFET's

Abstract: We use the n-channel deep-depletion SOS/MOSFET to measure carrier velocity of electrons in thin SOS films. The data are presented as a function of electric field up to the point where the velocity saturates. We show the consistency of these data across devices of different gate lengths and manufacture operating at different gate voltages. These results lead to the concept of a "universal curve" for the carrier velocity versus electric field relationship which can be applied to the modeling of velocity-saturation effects in n-channel SOS/MOSFET's. We develop a technique for such an application. In addition, by compensating for the effect of surface scattering on mobility, we have been able to show that the velocity versus field relationship at the surface of thin SOS films agrees very closely to that obtained from bulk silicon.