Showing papers on "MOSFET published in 1981"

Threshold-voltage instability in MOSFET's due to channel hot-hole emission

Abstract: Hydrogen introduced and trapped in the gate oxide of MOSFET's by the silicon-nitride capping process can be activated by emitted holes from the MOSFET channel to produce a large threshold-voltage shift. This effect requires avalanche multiplication in the channel for the production of holes when a dc voltage is applied to the gate. For the pulsed-gate case, the magnitude of the threshold-voltage shift depends significantly on the gate-pulse fall time, cycle time, and duty cycle. In both cases the electric field normal to the Si/SiO 2 interface near the drain aids the emission of holes across that interface. A semiquantitative model is proposed which says that holes can recombine at H 2 molecules and release sufficient energy to cause dissociation. The atomic hydrogen created can participate in electrochemical reactions at the gate oxide/channel interface which create nonuniform distributions of trapped charge and interface states along the channel. Model calculations of the time, temperature, and voltage dependences of this threshold instability agree well with measured results.

Effects of grain boundaries on laser crystallized poly-Si MOSFET's

Abstract: Data are reported for n-MOSFET's fabricated in laser crystallized poly-Si on amorphous insulating substrates. The dependence of electrical characteristics on the effective channel length in the range of 100 to 0.3 µm and on channel width from 120 to 20 µm is presented. The electron surface mobility is found to increase as the channel length is reduced, approaching that of devices in single-crystalline silicon. The source-to-drain leakage current, negligible for long channels, rapidly increases for channels shorter than ≃ 3 µm. This excessive current results from grain boundary diffusion of As from source and drain during high temperature fabrication steps.

N-channel enhancement-mode MOSFET characteristics from 10 to 300 K

Abstract: Operation of MOSFET circuits at the liquid nitrogen temperature (77 K) has been suggested as a means of improving circuit and system performance. Previously reported work emphasizes mobility and threshold voltage at 77 K. However, small MOSFET's require several (≳10) parameters for circuit design. Since a full set of MOSFET model parameters have not been previously reported, it has not been established whether conventional models can be applied for MOSFET circuit design at 77 K. We present here the temperature dependence of a full set of MOSFET circuit model parameters for channel lengths from 2.5 to 8.5 µm and for temperatures ranging from 10 to 300 K. Temperatures below 77 K are of interest in evaluating effects of impurity freezeout and temperatures above 77 K are important since actual device temperatures will be above the ambient. Overall, we find that the mobility and the threshold voltage are the dominant temperature dependent parameters and that conventional I-V characteristics persist down to 77 K. Below 77 K, some new features appear in the I-V characteristics. However, the conventional behavior down to 77 K suggests that standard (circuit models can be used for circuits operating at 77 K. Such circuits would be about four times faster than at room temperature and, with liquid nitrogen cooling, would provide an order of magnitude higher power density for VLSI.

A new edge-defined approach for submicrometer MOSFET fabrication

Abstract: A novel technique employing vertical (anisotropic) dry etching for fabricating edge-defined submicrometer MOSFETs is described, and preliminary results are presented. Three basic process techniques are employed: formation of an edge-defined submicrometer element, pattern transfer of the element into an underlying doped polysilicon gate layer, and passivation of the FET using a sidewall oxide. The submicrometer element formation technique is limited to linewidths in the 0.1 µm to 0.4 µm range. Characterization of MOSFETs, having physical channel lengths ∼0.1 µm to 0.15 µm and believed to be the world's smallest MOSFET's reported to date, is discussed.

A model of a narrow-width MOSFET including tapered oxide and doping encroachment

Abstract: A closed-form analytical expression is developed to predict the threshold voltage of a narrow-width MOSFET. The analytical expression developed is the first to include the effects of a recessed tapered oxide, the depletion charge under the thick recessed field oxide due to gate contact overlap and field doping encroachment at the channel edges. The theory is compared with experimental results and the agreement is dose.

UHF MOSFET Mixer

Abstract: A UHF television receiver tuner comprises a varactor tuned circuit coupled to an input electrode of a field effect transistor mixer through a serially connected RF coupling capacitor. A local oscillator signal is coupled to the input electrode of the field effect transistor mixer through an inductive loop whose inductance value is chosen such that proper impedance matching over the UHF band is achieved.

Schottky MOSFET for VLSI

Abstract: Recently MOSFET with Schottky source and drain has been considered an important candidate for VLSI because of its ultra-shallow junctions to minimize short-channel effects, low source and drain series resistances, simplified processes, and the elimination of minority carrier injection into the substrate [1]. We present results of MOSFETs with 300A PtSi as the source and drain contacts. The devices are fabricated on 2 × 1015cm-3, oriented n-Si substrates; and the gate oxide thickness is 250-300A. Long-channel behavior is observed for devices with channel lengths down to 1 µm, in very good agreement with the generalized guide for MOSFET miniaturization[2]. We observe that the output currents are smaller than those for the conventional MOSFETs. This is explained by the potential barrier arising in the gap between the Schottky source contact and the inversion channel. Extensive Arrhenius plots indicate that the gap has a profound effect in enhancing the corner field which in turn can greatly increase the current availability from the source. By reducing the gap to about 100A, the current approaches that as expected from the Pao-Sah theory[3].

Analysis and modeling of dual-gate MOSFET's

Abstract: Dual-gate MOS transistors (both as discrete devices and as circuit elements are extremely attractive for a variety of applications where electronic gain control capability, low feedback parameters, low noise and cross modulation, reduced short-channel effects, or high breakdown voltage are required. In this paper, the operation and physical characteristics of dual-gate MOSFET's are investigated. An accurate model is developed, which enables the simulation of behavior of the device with respect to bias conditions, by means of a simple iterative algorithm. Using this model, the static characteristics are analyzed in detail, special emphasis being directed toward the properties of the drain conductance and transconductances in the various operational modes. Second order effects, not taken into account in the model, are discussed. The boundaries of the operating regions also are calculated by means of simple analytic models. Extensive experimental verification is made through measurements conducted on various dual-gate transistor structures fabricated by a shadowed-gap/lift-off process.

Double threshold MOSFETs in bird's-beak free structures

Abstract: Edge effects found in MOSFET channels fabricated by a new bird's-beak-free process are studied by two-dimensional simulation. Test devices are also fabricated using the side wall masked isolation (SWAMI) process, and electrical characristics are measured. At the sharp corners of active- to field region boundaries, threshold lowering occurs because of electric field concentration. The effective channel width associated with the threshold voltage is very narrow ranging from 0.05 um or less to 0.3 um. Both the threshold and the effective width depend on the shape of the corner, and have weaker dependence on the substrate and surface impurity concentrations and substrate bias, than those of the planar surface devices. The optimization of MOS devices with bird's-beak free structure for conventional applications with very tight design rules is discussed. A three-transistor static memory cell utilizing the double threshold (DT) MOST is proposed and analyzed.

A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer

Abstract: This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through the use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath the surface. An n-type epitaxial layer is grown on the remaining thin single-crystal layer at the surface. Then, buried channel MOSFET's are formed on the n-type layer. The interface between the implanted SiO 2 and the upper silicon is abrupt, and the interface charge density is 6.9 × 1010cm-2. The effective carrier mobility calculated from the drain conductance is 750 cm2/V . s. Leakage current which should be inherent in this device structure can not be observed. Submicron MOSFET's show much smaller threshold voltage shifts than conventional ones, and this agrees with the results of two-dimensional numerical calculation. A ring oscillator composed of MOSFET's with 1-µm channel length shows a minimum delay time of 95 ps and a power delay product of 310 fJ at V DD of 15 V.

n‐channel deep‐depletion metal‐oxide‐semiconductor field‐effect transistors fabricated in zone‐melting‐recrystallized polycrystalline Si films on SiO2

Abstract: n‐channel deep‐depletion mode metal‐oxide‐semiconductor field‐effect transistors (MOSFET’s) have been fabricated in Si films prepared by zone‐melting recrystallization of chemical‐vapor deposited (CVD) polycrystalline Si deposited on SiO2‐coated Si substrates. The transistors exhibit surface electron mobility in the range of 600–700 cm2/Vs, comparable to values for devices fabricated in single‐crystal Si. Measurements of electron mobility as a function of gate bias voltage indicate that the mobility is nearly constant throughout the depth of the recrystallized Si films. Mobility of 650–700 cm2/Vs at the lower Si‐SiO2 interface and subthreshold source‐drain leakage current of a few pA/μm (channel width) have been measured.

Output characteristics of short-channel field-effect transistors

Abstract: A recent model for hot-electron MOS transistors [4], [5] is generalized for short-channel field-effect transistors. It is based on six to seven parameters for the carrier mobility under the influence of transverse and Iongitudinal electric fields, for the threshold voltage and its dependence on drain bias, and for a finite longitudinal field at pinch-off. Such important features of short-channel FET's like reduced available current and voltage gain are well represented, where the latter turns up as important limiting factor in submicron devices. Effects of zero-field mobility, impurities, and device geometry are stated explicitly. The results are confirmed by measured data on 0.9-µm silicon gate MOSFET's.

The Feasibility of Electrical Monitoring of Resin Cure with the Charge-Flow Transistor.

Abstract: A new technique for the electrical monitoring of polymerization reactions such as resin cure is described. The technique is based on the charge-flow transistor, which resembles a conventional metal-oxide-semiconductor field-effect transistor (MOSFET), but with a portion of the metal gate replaced by the resin under study. Electrical signals obtained from several resins undergoing cure are presented, along with an electrical circuit model that can account for the principal features of these signals. The dramatic change in signal shape during cure can be related to corresponding changes in both the real and imaginary parts of the dielectric constant.

Limitations on the performance of field-effect devices for logic applications

Abstract: The switching time and power dissipation of field-effect devices in integrated logic circuits are obtained using a simple equivalent circuit. It is seen that performance is determined by four basic parameters: channel length, operating voltage, parasitic capacitance, and saturation drift velocity. The effects limiting the optimization of these parameters are examined. It is found that channel length cannot be reduced below about 0.2 µm in the metal-oxide-semiconductor field-effect transistor (MOSFET) or below about 500 A in the metal-semiconductor field-effect transistor (MESFET). Operating voltages cannot be reduced below about 750 mV due to subthreshold leakage. In the limit of extremely small sizes, the most promising high-speed devices appear to be MESFET structures in GaAs or InP.

Threshold voltage characteristics of depletion-mode MOSFET's

Abstract: This paper presents the results of a study of the characteristics of the depletion-mode MOSFET. In particular, it is shown that the threshold voltage of this device is a function of its mode of operation (linear or saturated) due to a change in dominant conduction mechanisms caused by the finite depth of donor impurities in the channel. The effect of these impurities on the short channel behavior of the devices also is examined.

The monolithic HV BIPMOS

Abstract: An Integrated switch concept was developed which combines the advantages of the BJT and the MOSFET as power switches in one chip... the BIPMOS. Two types will be described, the "Uncommitted" and the "Shunt". Device layouts, mode of operation, fabrication, and application are described. The devices are fabricated in a self alligned MOS process, where the BJT is fully merged within the MOSFET. With the "Uncommitted" version a BIPMOS Darlington or a "Zenered" MOSFET are built. The "Shunt" BIPMOS is a 450v device with a current capability of 260A/Cm2. It offers efficiency merits over a BJT or a MOSFET when used in typical switch mode power supplies. A SMPS diagram using the "Shunt" BIPMOS is described with an efficiency analysis.

High-power III-V semiconductor device

Abstract: III-V semiconductor devices such as, e.g., MESFET, JFET, MOSFET, and IGFET devices are provided with relatively high-ohmic gates or wide gate finger widths as is desirable for maximum utilization of a semiconductor surface. For example, aluminum gate electrodes having a cross-sectional area of 1.2 square micrometer and a length of 300 micrometers or more are used. The resulting devices have unexpectedly high power handling capability.

Threshold voltage of a narrow-width MOSFET

Abstract: A simple closed-form analytical expression of the threshold voltage for a narrow-width MOSFET is developed. The narrow-width model gives a threshold voltage expression as a function of gate oxide thickness, channel doping concentration, backgate bias and channel width. The theory is compared with experimental results and the agreement is close.

Mos semiconductor device

Abstract: PURPOSE:To increase dielectric strength by providing a buried layer with high impurity density under the source region of an offset gate type MOSFET and a region including a gate. CONSTITUTION:A P type buried layer 11 with high impurity density is provided under the N type source region 5 of an offset gate lateral type power MOSFET having an N type high dielectric strength layer 6 and a region including a gate 4. This greatly reduces the resistance R'b between a substrate 1 and a channel region than the resistance Rb between the substrate 1 and a drain region 7. Therefore, holes generated at a gate end at the time of breakdown are quickly absorbed to the P substrate, so dielectric strength can increase.

dV/dt effects in mosfet and bipolar junction transistor switches

Abstract: Spurious turn-on due to dV/dt triggering is a real possibility in high speed switching circuits using MOSFETs or bipolar junction transistors (BJTs). This paper discusses the mechanisms leading to spurious turn-on, test methods to determine dV/dt limits, the effect of dV/dt turn-on circuit operation, and methods to minimize dV/dt triggering in practical circuits.

The field effect electron mobility of laser-annealed polycrystalline silicon MOSFETs

Abstract: Measured Id-Vd results on MOSFET's and C–V results on MOS capacitors which were fabricated on laser annealed polycrystalline silicon are presented A scanned CW Ar+ laser was used to anneal the samples Laser power varied from 10 to 15 W in increments of 1 W; beam diameter was about 40 μ m and scan rate was about 125 cm/s The field effect mobility, determined from Id-Vd measurements, increases with increasing laser power The effects of electron trapping in the polycrystalline silicon substrate were used to explain the observed mobility of the MOSFET's In transistors annealed at low power (

Integrated MOS driver stage with a large output signal ratio

Abstract: A driver stage formed in integrated MOS technology has a large output signal ratio but with reduced idle currents. First and second control stages are provided of MOSFETs series connected and with their outputs between the MOSFETs connecting to respective gates of an output stage also comprised of series connected MOSFETs. In the output stage, one of the MOSFETs has its channel resistance reduced and is parallel-connected with an additional MOSFET. A boot strap capacitor connects between a gate of the additional MOSFET and an output of the circuit.

Channel electron conduction in laser‐annealed polycrystalline silicon metal‐oxide semiconductor field‐effect transistors

Abstract: A scanned cw Ar+ laser was used to anneal the polycrystalline silicon on nitride structures. Laser power varied from l0 to 15 W in increments of 1 W, the beam diameter was ∼40 μm and the scan rate was ∼12.5 cm/s. The measured field‐effect electron mobility of the metal‐oxide semiconductor field effect transistor fabricated on the annealed silicon increases with increasing laser power. In transistors annealed at power ⩽11 W, an intercrystalline potential barrier resulting from the electron trapping at crystallite and grain boundary regions was found to be the dominant factor in the channel electron conduction. In transistors annealed at power ⩾ 12 W, channel conduction is limited by scattering from surface structure imperfections.

Technology challenges for ultrasmall silicon MOSFET's

Abstract: Work on silicon MOSFET devices scaled down to half‐micron dimensions is gathering momentum in research labs for VLSI applications. Further reductions in device geometries by only a factor of two will bring us to the edge of some fundamental barriers to miniaturization. Design requirements for very thin layers in the device structure lead to resistance effects, statistical fluctuation of doping impurities, and increased concern for interface properties. Scaling down of applied voltage is difficult because built‐in junction potentials and other small voltage terms are no longer negligible. Increased susceptibility to spurious operation or permanent damage from alpha particles, cosmic particles, or other high‐energy radiation is reviewed.

Threshold and subthreshold characteristics theory for a very small buried-channel mosfet using a majority-carrier distribution model

Abstract: Simple expressions of threshold and subthreshold characteristics for a very small buried-channel MOSFET is derived from a model of majority-carrier distribution along the channel. The carrier distribution is determined from the Poisson equation for a high-low junction. The basic formula for the subthreshold characteristic is derived from the majority-carrier drift-current equation. The theory is compared with the measured threshold voltages and the measured inverse semilogarithmic slopes of subthreshold current. The theoretical curves are in a reasonable agreement with experimental results. It is shown for a buried-channel MOSFET having a channel length less than 1 μm that the threshold and subthreshold characteristics change abruptly as the channel length is reduced because the majority-carrier concentration increases through the carrier diffusion from the source and drain terminals. The theoretical estimation shows that buried-channel MOSFETs will have the less short-channel effect than surface-channel MOSFETs for a small drain voltage. The theory also predicts that the buried-channel MOSFET can be scaled down in the same way as the surface-channel MOSFET.

MOSFET Light detecting device having a Schottky junction

Abstract: A device for detecting light having an improved sensitivity and a method for producing the device. N+ source and drain regions are formed on a P-type silicon substrate. The substrate is then covered with an oxidation resistant layer of SiO2. A layer of Pt-Si is then deposited between the source and drain regions and a P-type polysilicon layer is deposited on the Pt-Si layer. The device is then annealed to form a Schottky junction between the polysilicon layer and the Pt-Si layer following which a gate electrode is formed on the polysilicon layer.

Single-device-well MOSFET's

Abstract: A novel MOSFET structure based on merging a surface enhancement-type device and a buried depletion-type device in a Single Device Well (SDW) is described. The SDW MOSFET structure utilizes the inherent two-dimensional geometry of a MOSFET device well to obtain two devices perpendicular to each other, having the same gate, thereby utilizing the hitherto nonutilized volume of the well. The two perpendicular currents of the devices in the merged structure are analyzed. An analytical model is developed and circuit CAD simulations are performed. A test chip is fabricated and the structure performance is evaluated. Some circuit examples are given.

Analytical modelling of depletion-mode MOSFET with short- and narrow-channel effects

Abstract: As we move into the VLSI era, many investigations have been performed on enhancement-mode MOS transistors, and the results have often been used for the depletion-mode device. In order to evaluate the differences from the usual enhancement-mode device, and to understand its own behaviour, we have first made an accurate modelling of a large and wide buried-channel device, assuming a step doping profile. Then, an attempt was made to model the narrow- and short-channel effects, based on regional approaches. The model relies on the assumption that the narrow-channel effect is due to the increase in bulk charge due to the parasitic p+-n+ (field implant-buried layer) diode. For the short-channel effect, our investigations led us to assume that the effective implanted dose is increased by the diffusion of majority carriers from source and drain, which charge is shared between source, drain, bulk and gate. The excess of positive charge controlled by the gate (instead of the lack of negative charge that characterises the short-channel effect of an enhancement-mode MOSFET) can be evaluated with a geometrical approach, by making a double trapezoidal partioning. The surface and buried-channel conductions, as well as the non-pinch-off current are then taken into account to establish the current equations: IDtot = IDsurf + IDB.C + IDn.pinch-off. where IDsurf or IDB.C = f{VDS, VGS, VBS VT (L, W, VBS, VDS)}. The three kinds of current can exist separately or together, thus defining different equations for the total current flowing from source to drain. Comparison with experiments shows a good agreement, and, furthermore, the extracted parameters are very well related to technological parameters. Short and narrow channel transistors, down to micron dimensions, are fairly well described by the model, and one single set of parameters. In conclusion, the depletion-mode transistor appears to be more sensitive to geometry than the enhancement-mode device because of its special structure, and so we need a peculiar model and parameters for this device to get an efficient simulation of circuits fabricated in HMOS technology, where depletion-mode transistors are extensively used as active loads.

SDW MOSFET static memory cell

Abstract: The single device well (SDW) memory cell, including an access transistor, uses only two SDW MOSFETs, versus four-to-six transistors in conventional static memory cells and thus a great saving in silicon area results. Cell static and dynamic performance are discussed and simulated using an appropriate model implemented in the computer-aided circuit analysis program WATAND. The access time of the new cell is comparable to that of conventional MOSFET cells. Using 3 /spl mu/m technology, an SDW memory cell consumes an area of 600 /spl mu/m/SUP 2/ and has an average power consumption of 10 /spl mu/W at 5 V supply. Another version of the cell using a polyresistor is also discussed.

Theoretical study of a channel-doped separate gate Si MOSFET (SG-MOSFET) by two-dimensional computer simulation

Abstract: A new device structure is proposed for Si MOSFET, featuring an insulated gate structure, channel doping, and finite spacing between gate and source and between gate and drain. Two-dimensional numerical analysis shows that punchthrough is suppressed and that minimum gate length, limited bypunchthrough or V T shift, is extended into the submicrometer range.