Showing papers on "MOSFET published in 1984"

Lucky-electron model of channel hot-electron injection in MOSFET'S

Abstract: The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.

Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's

Abstract: The phenomenon of and the physical mechanisms for the generation of minority carriers in the substrate of NMOS and CMOS are studied Secondary impact ionization is not responsible The responsible mechanisms are hot-electron-induced photocarrier generation and, under extreme conditions, forward biasing of the source-substrate junction The photon generation is believed to be due to the bremsstrahlung of the channel hot electrons A theoretical model based on the lucky electron concept and the bremsstrahlung mechanism is proposed The calculated characteristics of photon generation agree well with experimental results About 2 × 10-5photogenerated minority carriers are generated for every (primary) impact-ionization event in NMOSFET Photocarrier-induced leakage current can be fitted with either an inverse square dependence on distance or an exponential dependence with an effective decay length of about 780 µm

Metal‐semiconductor field‐effect transistors fabricated in GaAs layers grown directly on Si substrates by molecular beam epitaxy

Abstract: Device‐quality GaAs layers have been grown directly on Si(100) substrates by molecular beam epitaxy. Metal‐semiconductor field‐effect transistors have been fabricated in these layers with transconductance as high as 85 mS/mm and leakage current as low as 1 μA at Vgs =−3 V for gate dimensions of 2.0 μm×200 μm.

A novel wide dynamic range silicon photodetector and linear imaging array

Abstract: A silicon photodetector structure utilizing the MOSFET subthreshold effect is discussed. This photodetector, which can be integrated on the same chip with MOSFET circuits or CCDs, provides an analog voltage signal over a wide dynamic range. Photodetector and arrays showed, in the visible spectrum an incoming radiation-detection light-intensity dynamic range of greater than 10/SUP 7/. In addition, the photodetector device was used to realize CCD and self-scanned MOSFET linear arrays. The theory of the new photodetector device and its use in forming linear imaging arrays are discussed. Experimental results are presented.

Current-voltage characteristics of thin-film SOI MOSFET's in strong inversion

Abstract: A simple analytic model for the steady-state current-voltage characteristics of strongly inverted silicon-on-insulator (SOI) MOSFET's is developed. The model, simplified by a key approximation that the inversion charge density is described well by a linear function of the Surface potential, clearly shows the dependence of the drain current on the device parameters and on the terminal voltages, including the back-gate (substrate) bias. The analysis is supported by measurements of current-voltage characteristics of thin-film (laser-recrystallized) SOI MOSFET's. The dependence of carrier mobility on the terminal voltages, especially the back-gate bias, is analyzed and shown to underlie discrepancies between the theoretical (constant mobility) and experimental results at high gate voltages. The mobility dependence on the back-gate bias enhances the strong influence of the back gate on the drain current, especially when the device is saturated.

Hydrogen passivation of PolySilicon MOSFET's from a plasma Nitride source

Abstract: Improvements in polysilicon grain-boundary passivation techniques have made polysilicon MOSFET's increasingly attractive, as vertically stackable circuit components in applications, where high mobility is not a primary requirement. A simple method for the "last step" passivation of grain boundaries in polysilicon MOSFET's is presented. The method involves diffusion of atomic hydrogen at 450°C from a plasma-deposited compressive silicon nitride layer for reaction at silicon grain-boundary dangling bond sites. By use of this technique, ON/OFF current ratios of greater than 106can be achieved with drive currents that are sufficient for many circuit applications.

A novel wide dynamic range silicon photodetector and linear imaging array

Abstract: A novel silicon solid-state photodetector structure utilizing the MOSFET subthreshold effect was conceived, developed, fabricated, and experimental results were obtained. This photodetector device, which can be integrated on the same chip with MOSFET circuits or CCD's, provides an analog voltage signal over a wide dynamic range. Fabricated photodetector devices and arrays showed experimentally, in the visible spectrum, an incoming radiation detection light intensity dynamic range of greater than 107. In addition, the novel photodetector device was used to realize CCD and self-scanned MOSFET linear arrays. In this paper, we describe in detail the theory of the new photodetector device and its applications to form linear imaging arrays. Finally, we present experimental results obtained on developed and fabricated devices and arrays.

Mosfet and MOS Capacitor Responses to Ionizing Radiation

Abstract: The ionizing radiation responses of metal oxide semiconductor (MOS) field-effect transistors (FETs) and MOS capacitors are compared. It is shown that the radiation-induced threshold voltage shift correlates closely with the shift in the MOS capacitor inversion voltage. The radiation-induced interface-state density of the MOSFETs and MOS capacitors was determined by several techniques. It is shown that the presence of "slow" states can interfere with the interface-state measurements.

Noise associated with distributed resistance of MOSFET gate structures in integrated circuits

Abstract: The effect of thermal voltage fluctuations in a resistive gate matrix perpendicular to the direction of channel current, in a MOSFET, are treated in detail. A general formula is derived to arrive at channel current fluctuations for an arbitrary gate matrix layout. This formulation is an extension of the analysis done by Thornber and is valid for frequencies at which the distributed RC time constants associated with the gate matrix are not important. The results of this analysis can be used to design low-noise resistive gate structures.

MOSFET "H" Switch circuit for a DC motor

Abstract: A MOSFET "H" switch circuit for providing bidirectional control to a DC motor. The power MOSFET's employed have significant advantages over bipolar and darlington power transistors and allow for microcomputer interfacing for providing bidirectional rotational control as well as motor speed control by pulse width modulation.

A capacitance method to determine channel lengths for conventional and LDD MOSFET's

Abstract: A simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel length. Measurements from two gate biases on devices of different channel lengths are sufficient to obtain a full characterization. In contrast to the channel-resistance method, the accuracy of the capacitance method is independent of the source-drain and contact series resistance. It can, therefore, be used for conventional as well as lightly-doped drain (LDD) devices. Channel length and gate-oxide thickness determined by this method are given for conventional and LDD MOSFET's. For conventional MOSFET's, the new method agrees with the traditional effective length measurements to better than 0.1 µm.

An analytical model for the channel electric field in MOSFET's with graded-drain structures

Abstract: A simple analytical model for the lateral channel electric field in the drain region of MOSFET's with graded-drain or lightly doped drain structures is presented. The model's results agree well with two-dimensional simulations of the electric field in the drain region. Due to its simplicity, this model gives a better understanding of the mechanisms involved in reducing the electric field in the lightly doped region. Results show the impact of the length and doping concentration, assumed to be Gaussian, of the lightly doped region on the electric field. Effects of the oxide thickness and junction depth are also accounted for. In each case, there is an optimum doping concentration that minimizes the peak electric field.

A simple method to determine channel widths for conventional and LDD MOSFET's

Abstract: A new method to determine the channel widths and in situ gate-oxide thicknesses of conventional and LDD MOSFET's is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel width. Measurements from two gate biases on devices of different channel widths are sufficient to obtain a full characterization. Channel widths and gate-oxide thicknesses determined by this method are given for both types of devices. This method applies to large-size as well as small-size, test devices.

Transient drain current and propagation delay in SOI CMOS

Abstract: The transient overshoot in drain current that occurs in thin-film SOI (Si-on-SiO 2 ) MOSFET's because of the floating body in analyzed, and the benefit it can provide to propagation delay (speed) in SOI CMOS digital circuits is assessed. The analysis accounts for the charge coupling between the front and back gates, and hence describes the dependence of the transient drain (saturation) current and propagation delay on the back-gate bias as well as on the switching frequency. Measurements of the transient current in recrystallized SOI MOSFET's and of propagation delay in SOI CMOS inverters and ring oscillators are described and shown to support the theoretical analysis. The current overshoot is especially beneficial in low-voltage circuits, although at high frequencies other floating-body effects can degrade the speed.

Elevated source/drain MOSFET

Abstract: The fabrication of both n- and p-channel MOSFET's with the souce/drain regions elevated above the electrical channel is described. The realization of effective shallow junctions is demonstrated and the device properties are compared to those of conventional MOSFET's.

Two-dimensional analytical modeling of threshold voltages of short-channel MOSFET's

Abstract: We present an analytical model of the threshold voltage of a short-channel MOSFET based on an explicit solution of two-dimensional Poisson's equation in the depletion region under the gate. This model predicts an exponential dependence on channel length (L), a linear dependence on drain voltage (V D ), and an inverse dependence on oxide capacitance (e ox /t ox ). An attractive feature of this model is that it provides an analytical closed-form expression for the threshold voltage as a function of material and device parameters (t ox , V D , L, substrate bias, and substrate doping concentration) without making premature approximations. Also, this expression reduces to the corresponding expression for long-channel devices.

Semiconductor device monolithically comprising a V-MOSFET and bipolar transistor isolated from each other

Abstract: A semiconductor device comprising a high voltage withstanding vertical MOSFET and a low voltage withstanding element both formed on a single chip. A buried layer of a high impurity concentration is formed in a region where the vertical MOSFET is formed, and another buried layer of a high impurity concentration is formed in a region where the low voltage withstanding element is formed. These buried layers have different thickness, whereby the series resistance of a circuit adjacent to the vertical MOSFET is reduced without lowering the withstand voltage of the vertical MOSFET.

Fast turn-off circuit for photovoltaic driven MOSFET

Abstract: A power MOSFET is controlled by illuminating a single photovoltaic generator which produces an output current which charges the gate capacitanace of the power MOSFET to turn on the device. A sensing impedance which may be a diode, MOSFET or other component is connected between the photovoltaic generator and the gate of the power MOSFET. The sensing impedance in the disclosed embodiment is a diode. The sensing impedance forces the power MOSFET gate voltage instantaneously to follow the photovoltaic generator output voltage. The diode is connected in series with the charging circuit and a switching transistor is connected in parallel with the gate capacitance of the MOSFET. The switching transistior base is coupled to the output of the photovoltaic source so that, when the photovoltaic source turns off, and the voltage of the photovoltaic source decays below a predetermined value, the switching transistor turns on to short-circuit the MOSFET gate capacitance so that it can immediately discharge to provide fast turn-off of the power MOSFET. A dV/dt clamping circuit is provided to prevent false charging of the power MOSFET gate through its drain-to-gate capacitance.

Monolithically integrated In0.53Ga0.47As-PIN/InP-MISFET photoreceiver

Abstract: In0.53Ga0.47As PIN photodiode and InP MISFET were monolithically integrated on an Fe-doped semi-insulating InP substrate. Photoreceiver sensitivities were measured at 100 Mbit/s NRZ pseudorandom signals.

Non-latch-up 1200V 75A bipolar-mode MOSFET with large ASO

Abstract: In 1984 ICSSDM, Kobe, we already reported the development of 1200V, 75A bipolar-mode MOSEs(BIFET[l], or called IGT, COMFET [2,3]), which could turn-off 75Amps drain current with lOOOV applied drain voltage at the elevated temperature, 125 C(see Fig. 1). This paper presents improved BIFETs with non-latch-up structure as well as a large ASO. Figure 2 shows a cross section of a new BIFET. A part of the source layer is periodically eliminated, providing a low resistance bypass for holes to the source electrode without biasing the source-base junction. The maximum drain current was substantially limited by the c annel pinch-off effect before ti reached the increased latchup current level, which was attained by the vertical BIFET structure and the optimized source pattern. Thus, the latch-up mode was not observed under any driving conditions unless gate voltage exceeds 20V. It was found that the latch-up current density JL depends gate width LG through the following equation [I]: JL=Vbi/(LG Rb) ----LG: gate width; Vbi:built-in voltage for sourcebase junct.; Rb:channel to source electrode p-base resistance for unit channel width. New BIFET structure provides a lower Rb, which enables to use a larger LG than the original BIFET with attaining a high latch-up current density. Thus, new BIFETs exhibit low forward voltage regardless of reduced channel width. BIFETs should have a sufficiently large AS0 so that BIFETs can be used as a key switching device in place of bipolar transistors in a power application system. If the external load is caused to be short-circuited due to system failure, drain current is limited only by the device resistance itself with the drain voltage being the same as the external power supply voltage. The device should dissipate a large heat 'until a protection circuit works, reducing gate voltage to zero. Figure 3 shows the measured 25 pec forward conductionAS0 limit. The improved BIFETs can sustainmore than 65Amps drain current with 600V forward voltage drop and 20V gate voltage during 25 gsec, which is sufficient for sensing and device protection. Measured switching AS0 is also included in Fig. 3. Voltage and current density product exceeds 3X105VA/cm2, which suggests avalanche multiplication for a failure cause. Neither snubber nor clamp circuit is necessary for the inductive load switching. Figure 4 shows 48Amps switching waveforms, wherein voltage surge is clamped by the device itself. The electrical characteristics for the improved BIFETs are given in Table. BIFETs are now ready for applications.

Effect of hot-electron stress on low frequency MOSFET noise

Abstract: Hot-electron reliability problems are of great importance in small geometry n-channel field-effect transistors. Accumulation of negative charge within the gate insulator and creation of interface states represent the two dominant degradation mechanisms. Since MOSFET noise is ascribed to Si-SiO 2 interface states, one might reasonably expect this noise to increase after hot-electron stress. We verify this expectation and show how the noise increase depends on gate voltage during stress. MOSFET noise is important for analog circuit performance and, hence, consideration of the long-term stability of noise, as well as threshold voltage and transconductance, should be included in analog circuit/process design.

A new vertical double diffused MOSFET—The self-aligned terraced-gate MOSFET

Abstract: A new power MOSFET structure with a Self-aligned Terraced Gate (STGMOSFET) is demonstrated. The unique gate structure of the STGMOSFET reduces the parasitic gate capacitances, resulting in improved high-frequency performance. The STGMOSFET structure was used to design a 3.5 mm × 3.5 mm transistor. This chip had an on-resistance of 2.3 Ω and a 500-V source-drain breakdown voltage. It exhibited excellent high-frequency performance with a cut-off frequency of 100 MHz, and rise and fall times of 5 and 20 nS, respectively.

Surface induced latchup in VLSI CMOS circuits

Abstract: Experimental as well as theoretical results on the latch-up effect in CMOS structures with and without an epitaxial layer are presented. In structures with an epitaxial layer the critical current for latchup firing is two orders of magnitude higher and latchup is essentially surface controlled. The strong surface effect observed is a consequence of the gate influence of surface conduction of the field oxide MOSFET's and on current gains of the bipolar transistors. Latch-up sensitivity can be decreased by increasing p+/p-well and n+/n-well spacing, by decreasing expitaxial layer thickness and by increasing substrate doping. In reducing the lateral dimensions, short-channel effects of the field oxide transistors imply the most severe limitations for latch-up immunity.

Current overload protected solid state relay

Abstract: A control circuit for protecting a metal oxide semiconductor field-effect power transistor from current overloads is disclosed in one embodiment of the control circuit A silicon controlled rectifier is used to remove the bias voltage from the MOSFET in the event of a current overload In another embodiment of the invention a bipolar transistor in combination with a second MOSFET is used to turn off the power MOSFET in the event of a current overload The voltage appearing across the power MOSFET is used as an indication of a current overload condition

Electrical Characteristics of Large-Scale Integration Silicon MOSFET's at Very High Temperatures,Part III: Modeling and Circuit Behavior

Abstract: The effects of high temperature (27°C to 300°C) on electrical characteristics of long n and p channel metal-oxide semiconductor fieldeffect transistors (MOSFET's) are used to extend the validity of the conventional (room temperature) large and small signal models of these devices. A complementary metal-oxide semiconductor (CMOS) inverter's transfer characteristics and switching speed performance, and the frequency response of a simple resistive load inverter are presented, with temperature as a parameter. Some implications of the models developed, on analog MOS circuit design (for high-temperature, operation), are discussed.

Insulated gate transistor modeling and optimization

Abstract: The Insulated Gate Transistor (IGT) is a new power switching device which appears promising for high voltage applications. As of this date, however, this device has not been quantitatively modeled or optimized. The aim of the present study is to develop an accurate and effficient model of the IGT. The IGT is modeled as a Bipolar Junction Transistor (BJT) driven by a MOSFET. The bipolar nature of the device is examined by studying the effects of carrier lifetime on electrical performances. This model also predicts the effects of the gate-oxide thickness, channel length, and cell spacing on the IGT forward I-V characteristics for a 100-1200V range in blocking voltage. The relative significance of the MOS/BJT components of the device has been explored. This is particularly important when optimizing designs over a wide range of voltage ratings Careful attention to this has led to greater than a three times improvement in high temperature dynamic latching current This is the key to obtaining a wide safe-operating-area for the IGT. For the first time, an accurate and straightforward mode of the IGT has been developed. The model predictions are within 10% of the experimental data.

An analytic and accurate model for the threshold voltage of short channel mosfets in vlsi

Abstract: Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (