Showing papers on "MOSFET published in 1986"
TL;DR: In this article, a new technique is presented for separating the threshold voltage shift of a metaloxide-semiconductor transistor into shifts due to interface traps and trappedoxide charge, which is applied to threshold voltage shifts on an n-channel transistor that result from ionizing radiation.
Abstract: A new technique is presented for separating the threshold‐voltage shift of a metal‐oxide‐semiconductor transistor into shifts due to interface traps and trapped‐oxide charge. This technique is applied to threshold‐voltage shifts on an n‐channel transistor that result from ionizing radiation.
676 citations
TL;DR: In this article, the authors showed that the sub-threshold slope of transistors made in thin silicon films can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel.
Abstract: Silicon-on-insulator (SOI) n-channel transistors have been made in thin (90 nm) silicon films Both modeling and experimental results show that excellent subthreshold slopes can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel For comparison, the subthreshold slope of transistors made in thicker films is also reported
263 citations
23 Jun 1986
TL;DR: In this article, a novel resonant switch operating under the principle of zerovoltage switching is presented, which eliminates the switching loss and dv/dt noise due to discharging of MOSFET's junction capacitances and the reverse recovery of diodes, and enables the converters to operate at yet higher frequencies.
Abstract: A novel resonant switch operating under the principle of zero-voltage switching is presented. In contrast to the zero-current switching, this technique eliminates the switching loss and dv/dt noise due to the discharging of MOSFET's junction capacitances and the reverse recovery of diodes, and enables the converters to operate at yet higher frequencies.
239 citations
TL;DR: In this article, the intrinsic parasitic series resistance that occurs near the channel end of a MOSFET is analyzed, including the effects due to the unavoidable doping gradient near the metallurgical junction.
Abstract: The intrinsic parasitic series resistance that occurs near the channel end of a MOSFET is analyzed. This new model includes the effects due to the unavoidable doping gradient near the metallurgical junction. It is assumed that current first conducts through the accumulation layer before spreading into the bulk region, and thus the spreading (injection) resistance and the accumulation layer resistance have to be considered in series and both are gate-voltage dependent. More importantly, they are shown to be a strong function of the steepness of the doping profile. The model quantitatively predicts these resistance components for a given process, and it emphasizes the necessity for a steep junction profile in order to minimize the series resistance of MOSFET's.
140 citations
TL;DR: Inversion-layer capacitance has been experimentally characterized and identified to be the main cause of the second-order thickness-dependence of MOSFET characteristics as discussed by the authors, and empirical equations for inversion layer capacitance and mobilities versus electric field are proposed.
Abstract: Inversion-layer capacitance has been experimentally characterized and identified to be the main cause of the second-order thickness-dependence of MOSFET characteristics. Field-dependent channel mobilities of both electrons and holes were independent of gate-oxide thicknesses from 50 to 450 A, e.g., there is no evidence of the alleged mobility degradation in very thin gate-oxide MOSFET's. Subthreshold slope, insignificantly affected by the inversion-layer capacitance, follows the simple theory down to ∼ 35 A of oxide thickness. The empirical equations for inversion-layer Capacitance and mobilities versus electric field are proposed.
138 citations
TL;DR: In this paper, hole-trapping effects at doses to 15 Mrad(SiO2) were examined in MOS field effect transistors (MOSFET's) and MOS capacitors with 11-to 27-nm gate oxides.
Abstract: We present the results of an investigation into the buildup of trapped positive oxide charge responsible for a negative component of radiation-induced threshold voltage shift in both hard and soft metaloxide semiconductor (MOS) gate oxides and the processes which limit this buildup. Hole-trapping effects at doses to 15 Mrad(SiO2) were examined in MOS field-effect transistors (MOSFET's) and MOS capacitors with 11- to 27-nm gate oxides. The observed saturation of threshold voltage shift was modeled with the aid of a computer simulation of charge buildup in an MOS structure and was found to be caused by a complex interaction between trap filling and recombination of radiation-generated free electrons with trapped holes, modulated by trapped-hole-induced distortion of the oxide electric field. A supplemental measurement of 10-keV x-ray-induced currents in MOS capacitors produced no evidence for radiation-generated hot electron injection from the Si substrate into SiO2 layers of various thicknesses and also yielded data on x-ray-induced charge generation in the SiO2.
131 citations
Patent•
13 Jun 1986TL;DR: In this paper, the integration of Si MOSFETs and gallium arsenide MESFET on a silicon substrate is described, except for contact openings and final metallization.
Abstract: Monolithic integration of Si MOSFETs and gallium arsenide MESFETs on a silicon substrate is described herein. Except for contact openings and final metallization, the Si MOSFETs are first fabricated on selected areas of a silicon wafer. CVD or sputtering is employed to cover the wafer with successive layers of SiO 2 and Si 3 N 4 to protect the MOSFET structure during gallium arsenide epitaxy and subsequent MESFET processing. Gallium arsenide layers are then grown by MBE or MOCVD or VPE over the entire wafer. The gallium arsenide grown on the bare silicon is single crystal material while that on the nitride is polycrystalline. The polycrystalline gallium arsenide is etched away and MESFETs are fabricated in the single crystal regions by conventional processes. Next, the contact openings for the Si MOSFETs are etched through the Si 3 N 4 /SiO 2 layers and final metallization is performed to complete the MOSFET fabrication. In an alternative embodiment, Si MOSFETs and aluminum gallium arsenide double heterostructure LEDs are formed in a similar manner.
122 citations
TL;DR: In this paper, it has been found that certain n-channel MOSFET's fabricated on silicon-on-insulator (SOI) substrates formed by oxygen implantation can have very steep slopes in the subthreshold region.
Abstract: It has been found that certain n-channel MOSFET's fabricated on silicon-on-insulator (SOI) substrates formed by oxygen implantation can have \log (I_{d}): V_{gs} , characteristics with very steep slopes in the subthreshold region. In contradiction to normal models for short-channel transistors on bulk silicon, the slope becomes steeper for shorter gate lengths or higher drain voltages. This effect is shown to be related to the kink in the output characteristics of transistors with floating islands.
85 citations
TL;DR: In this article, an analytical expression can simulate the inverse-narrow-width effect, which is a reduction in the threshold voltage of a MOSFET with decreasing channel width, and the model is compared with experimental threshold voltage data from small-geometry PMOS devices with fully recessed isolation oxides.
Abstract: For the first time an analytical expression can simulate the inverse-narrow-width effect. The inverse-narrow-width effect is a reduction in the threshold voltage of a MOSFET with decreasing channel width. We compare the model with experimental threshold voltage data from small-geometry PMOS devices with fully recessed isolation oxides and an inverse-narrow-width effect is predicted.
79 citations
TL;DR: Fully monolithic integration of interconnected GaAs/Al-GaAs double-heterostructure LED's and Si MOSFET's is demonstrated for the first time in this paper.
Abstract: Fully monolithic integration of interconnected GaAs/Al-GaAs double-heterostructure LED's and Si MOSFET's is demonstrated for the first time. The Si MOSFET's, with a gate length of 5 µm and gate width of 1.6 mm, have almost the same characteristics as those of control devices fabricated on a separate Si wafer. The LED output collected by a microscope lens with a numerical aperture of 0.65 is about 6.5 µW at 100- mA dc current. LED modulation rates up to 27 Mbit/s have been achieved by applying a stream of voltage pulses to the MOSFET gate. The modulation rate is limited by the speed of the MOSFET.
77 citations
TL;DR: In this paper, a new method for determining the channel charge and mobility of a MOS transistor as a function of gate bias from the ac admittance measurements is described, where the peaks of the G/omega versus ω curves are used to deduce gate-channel capacitance and mobility.
Abstract: A new method is described for determining the channel charge and mobility of a MOS transistor as a function of gate bias from the ac admittance measurements. The admittance of the conduction channel of the MOSFET is derived from a transmission line model. The peaks of the G/\omega versus ω curves are used to deduce gate-channel capacitance and mobility. The mobile carrier density and mobility in very thin-oxide MOSFET's can be measured more accurately using this ac method, since a zero lateral field and a uniform mobile charge distribution along the channel is maintained with zero drain-source voltage and interface trap effects are reduced by using high test frequencies. Measured data on the electron mobility versus gate voltage are presented for 90-A gate dielectric MOS transistors.
TL;DR: An 8 × 8 bit NMOS multiplier test chip for image processing systems has been realized on the basis of a newly designed carry save adder cell, with a multiplication rate of 3.3 108 1/sec being achieved.
Abstract: An 8X8-bit multiplier test circuit developed in a 1-/spl mu/m NMOS technology is described. To achieve a high throughput rate, extensive pipelining is used in a semi-systolic fashion. It is shown that this saves area and allows for shorter cycle times compared to a pure systolic array. Problems with widely distributed lines (broadcasting) are avoided by a novel carry-save-adder cell. The data inputs and outputs are ECL compatible. The circuit contains 5480 MOSFET's in an active area of 0.6 mm/sup 2/. Effective channel lengths of 0.9 and 1.1 /spl mu/m are utilized for the enhancement and depletion transistors with a gate oxide thickness of 12.5 nm. The power dissipation is 1.5 W at a supply voltage of 3 V. The test chip operates up to a clock frequency of 330 MHz at room temperature and up to 600 MHz with liquid nitrogen cooling. This demonstrates the applicability of large-scale integrated MOS circuits in a frequency range of several hundred megahertz.
TL;DR: In this paper, the first 3C-SiC MOSFET was successfully fabricated on a 3C SiC film heteroepitaxially grown on an Si substrate.
Abstract: Cubic-SiC (3C-SiC) MOSFET's were successfully fabricated for the first time on a 3C-SiC film heteroepitaxially grown on an Si substrate. The device showed acceptable static characteristics. A novel device structure was devised, which enabled the use of conventional equipment for silicon devices, and eliminated dedicated processes for a stable and rigid SiC film.
TL;DR: In this article, the temperature coefficient of the threshold voltage of the most common types of MOSFET devices has been measured and analyzed in terms of the underlying device physics, due to differences in gate contact potential and anomalies of the substrate backbias effect.
Abstract: The temperature coefficient of the threshold voltage of the most common types of MOSFET devices has been measured and analyzed in terms of the underlying device physics. Owing to differences in gate contact potential and anomalies of the substrate backbias effect, the above coefficient has a typical value for each type. In particular for a compensated device, such as a CMOS p-channel MOSFET, the value of the temperature coefficient is relatively large (up to 3 mV/degree).
TL;DR: In this article, the fabrication of MOSFET's with submicrometer gate lengths using Gas Immersion Laser Doping (GILD) to dope the source-drain and gate regions of n-channel devices is described.
Abstract: The fabrication of MOSFET's with submicrometer gate lengths using Gas Immersion Laser Doping (GILD) to dope the source-drain and gate regions of n-channel devices is described. The GILD step relies on a melt/regrowth process, initiated by a pulsed excimer laser (XeCl, λ = 308 nm), to drive in a dopant species adsorbed on the clean silicon surface. High dopant concentrations (1 × 1019to 2 × 1021cm-3) and shallow junctions (600-1000 A) make this process ideally suited for source-drain formation in submicrometer structures. In this work the transistors are fabricated using an otherwise conventional NMOS process. The resultant devices have similar source-drain R sheet values and lower poly R sheet when compared to devices fabricated using a conventional implanted source-drain and diffused polysilicon gate. Short-channel devices ( L_{poly} = 0.9 µm) exhibit excellent I-V characteristics and little change in V t .
NEC1
TL;DR: In this article, practical limitations in channel lengths for n-channel MOSFETs under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drone, double diffused drain (DDD), and lightly doped drain (LDD) structures.
Abstract: Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.
TL;DR: In this article, the authors identify various sources of leakage current in thin-film silicon on insulator (SOI) MOSFET's made in hydrogen-passivated small-grain polycrystalline silicon.
Abstract: In this paper we identify various sources of leakage current in thin-film silicon on insulator (SOI) MOSFET's made in hydrogen-passivated small-grain polycrystalline silicon. The action of a parasitic bipolar transistor that can amplify the leakage current due to the thermally generated carriers has been confirmed and characterized. A current gain (β) of more than 6 for the parasitic bipolar transistor has been experimentally measured in accumulation-mode devices, in spite of the presence of a large number of defects. This high gain is attributed to the presence of the vertical electric field, which separates the carriers, thus reducing the probability of recombination. The presence of field-enhanced generation is shown to be the cause of the observed increase in the leakage current with positive front- or back-gate bias for p-channel accumulation-mode devices. Reasonable agreement has been obtained between experimental data and theory based on field-enhanced generation due to Poole-Frenkel barrier lowering.
TL;DR: In this paper, the authors investigated polycrystalline-silicon MOSFET operation by means of a two-dimensional device-analysis program developed at the University of Bologna.
Abstract: In this paper we investigate polycrystalline-silicon MOSFET operation by means of a two-dimensional device-analysis program developed at the University of Bologna. The grain-boundary model used in this study allows for both donor and acceptor states at the interface, and assumes a drift-diffusion transport mechanism, consistently with the general structure of the code. Results achieved thus far allow us to interpret the increased threshold voltage experimentally observed in polycrystalline-silicon MOSFET's and the device transconductance in strong inversion; on the other hand, the current increase occurring at negative gate voltages is not justified by the numerical model so far implemented. It is believed that field-enhanced emission rates and impact ionization are possible mechanims to interpret the above conduction increase.
TL;DR: In this paper, the integration of Si MOSFET's and GaAs MESFETs on a monolithic GaAs/Si (MGS) substrate has been demonstrated.
Abstract: Integration of Si MOSFET's and GaAs MESFET's on a monolithic GaAs/Si (MGS) substrate has been demonstrated. The GaAs MESFET's have transconductance of 150 mS/mm for a gate length of 1 µm, and the Si MOSFET's have transconductance of 19 mS/mm for a gate length of 5 µm and an oxide thickness of 800 A. These characteristics are comparable to those for devices fabricated on separate GaAs and Si substrates.
TL;DR: In this article, a GaAs light-emitting diode (LED) driven by a Si metaloxide-semiconductor (MOS) transistor was fabricated and the light output as a function of applied gate voltage was measured.
Abstract: A monolithic optoelectronic circuit, consisting of a GaAs light‐emitting diode (LED) driven by a Si metal‐oxide‐semiconductor (MOS) transistor, has been fabricated. Light output as a function of applied gate voltage was measured. The LED’s were fabricated in GaAs layers on Ge‐coated Si substrates containing MOS transistors. Normal transistor performance was observed after the GaAs LED fabrication, indicating that GaAs and Si processing technologies appear to be compatible.
TL;DR: A physical model that characterizes the subthreshold drain current (gatevoltage swing) and threshold voltage of thin-film LPCVD polysilicon MOSFET's is developed and supported experimentally.
Abstract: A physical model that characterizes the subthreshold drain current (gate-voltage swing) and the threshold voltage of thin-film LPCVD polysilicon MOSFET's is developed and supported experimentally. The model describes the influence of the grain boundaries and of the charge coupling between the front and back gates on the subthreshold behavior. Main predictions are that the gate-voltage swing depends strongly on grain-boundary properties but weakly on the charge-coupling effects, that the threshold voltage depends strongly on grain-boundary properties and charge-coupling effects, and that the charge-coupling effects diminish as the grain-boundary trap density, the thickness of the film, or the doping density in the film increases. Comparisons of model predictions and measured data for passivated (hydrogenated) and unpassivated devices indicate quantitatively how hydrogenation reduces the trap density and increases the carrier mobility in the channel.
TL;DR: In this paper, a half-micrometer buried p-channel MOSFET with efficient punch-through stops is described, which achieves high punchthrough resistance without increasing the nwell concentration and extreme scaling of channel and source-drain junction depths.
Abstract: This paper describes design and characteristics of a new half-micrometer buried p-channel MOSFET with efficient punch-through stops. The approach for scaling down the buried p-channel MOSFET's is discussed by using two-dimensional process/device simulations and experimental results. The efficient punchthrough stops have realized high punchthrough resistance in half-micrometer dimensions without increasing the n-well concentration and extreme scaling of channel and source-drain junction depths. Moreover, this p-channel MOSFET shows the breakdown voltage to be as high as 10 V. The fabrication sequence is compatible with the conventional n-channel LDD MOSFET's.
Patent•
06 Feb 1986TL;DR: In this article, a power MOSFET reversing H-drive system with a first pair of N-channel and P-channel MOS-FETs connected in series with a load (LD1, LD2) to a power supply source (T 1) and a second like pair of nchannel and p-channel mOS-fETs (Q3, Q4) connected with an overvoltage protector (Z1, Z2) allowing extension of the supply voltage (T1) range under which the system is operable.
Abstract: A power MOSFET reversing H-drive system having a first pair of N-channel and P-channel MOSFETs (Q1, Q2) connected in series with a load (LD1, LD2) to a power supply source (T 1) and a second like pair of N-channel and P-channel MOSFETs (Q3, Q4) connected in series with the load (LD1, LD2) to the source (T1), each pair having a resistance voltage divider (R1-R2, R5-R6) for providing the P-channel MOSFET (Q1, Q3) with a different voltage level gate signal from the logic level input signal by which the N-channel MOSFET (Q2, Q4) is gated, an overvoltage protector (Z1, Z2) allowing extension of the supply voltage (T1) range under which the system is operable, and the on-state resistances and the flyback current capability of the intrinsic diodes (ID1, ID4) being matched to the size of the load to be driven
TL;DR: In this article, a threshold voltage model for short and long-channel MOSFETs with a nonuniform substrate doping profile is presented, based upon an approximate two-dimensional analytical solution of Poisson's equation.
Abstract: A threshold voltage model is presented which is valid for short- and long-channel MOSFET's with a nonuniform substrate doping profile. The model is based upon an approximate two-dimensional analytical solution of Poisson's equation for a MOSFET of arbitrary substrate doping profile which takes into account the effect of curved junctions of finite depth. The analytical model is compared to MINIMOS simulations showing that it can accurately predict short-channel threshold voltage falloff and threshold voltages in this vicinity without the use of fitting parameters.
TL;DR: In this article, the authors studied the electron mobility behavior in submicron MOSFETs in the temperature range of 77-300 K and found that the effective mobility as well as the field-effect mobility are less temperature dependent.
Abstract: The electron mobility behaviour in submicron MOSFETs is studied in the temperature range of 77–300 K. As the effective channel length is reduced, the effective mobility as well as the field-effect mobility are found to decrease and to become less temperature dependent. These experimental results are explained by the influence of series resistance and effective channel length, which are both temperature dependent. The possibility of accurate determination of series resistance and “pure” mobility is demonstrated. A new method is proposed to determine submicron MOSFET channel length at low temperatures.
Patent•
04 Jun 1986
TL;DR: In this paper, a P-type silicon substrate is selectively oxidized to form a thick oxide film and then the oxide film is wet-etched to lower a substrate surface on an N-well.
Abstract: PURPOSE:To improve integration degree by forming an N-well to build an N-channel transistor, thereafter by wet-etching the part by forming a thick oxide film and by providing a step to a surface of a P-type silicon substrate. CONSTITUTION:A P-type silicon substrate 1 is selectively oxidized to form a thick oxide film 22. The oxide film 22 is wet-etched to lower a substrate surface 23 on an N-well 2 relatively to the surface of the P-type silicon substrate 1. Then a first MOSFET 15 is formed to a region which is formed by wet- etching the P-type silicon substrate 1. A second MOSFET 16 is formed on the P-type silicon substrate 1 adjoining the N-well 2. According to this constitution, it is possible to restrain lap-up phenomenon, to cut down a distance between MOSFETs 15, 16 and to improve integration degree.
TL;DR: In this paper, the authors describe high-voltage CMOS separation by implanted oxygen (SIMOX) technology and its application to a BSH-LSI that provides the basic functions of battery feed, supervision, and hybrid for subscriber line interface cuircuits.
Abstract: This paper describes high-voltage CMOS separation by implanted oxygen (SIMOX) technology and its application to a BSH-LSI that provides the basic functions of battery feed, supervision, and hybrid for subscriber line interface cuircuits. This technology is characterized by the existence of an electric-field-shielding (EFS) layer formed between the buried SiO 2 and the surface Si layer by oxygen implantation. The density of localized states at the Fermi level of the EFS layer has been estimated to be about 1 × 1019cm-3. eV-1using the Cohen-Fritzsche-Ovshinsky model. The EFS layer reduces substrate voltage dependence of the threshold voltage and increases the drain-to-source breakdown voltage for MOSFET's. Specifically, the drain-to-source breakdown voltage has been raised to 180 V. The BSH-LSI, which is composed of high-voltage CMOS of more than 60 V and low-voltage CMOS of 15 V, has been successfully fabricated containing resistors and capacitors. Compared with a conventional bipolar BSH-LSI, the chip size and the dissipation power of the LSI have been reduced to approximately one-third and one-half, respectively.
01 Jan 1986
TL;DR: In this article, the degradation mechanism caused by hot carrier injection is clarified by the distribution of emitted carrier density at the interface of a two-dimensional device simulator. And the validity of the emitted carrier distribution is checked by the measured gate current-voltage characteristics.
Abstract: To clarify the degradation mechanism caused by hot carrier injection, the distribution of the emitted carrier density at the interface are simulated by the two-dimensional device simulator. The validity of the emitted carrier distribution is checked by the measured gate current-voltage characteristics It is shown that both the distribution of emitted electrons and holes are essential to explain the measured transistor degradation in both conventional and LDD MOSFET. Furthermore, the difference of the emitted carrier distribution between LDD and conventional MOSFET, gives a good explanation of the difference of measured conductance degradation in early stress stage.
01 Jan 1986
TL;DR: In this paper, it was shown that the use of silicide-clad diffusions causes output buffer failure threshold levels to degrade by more than 50% from what is observed without silicided diffusions, and that using the graded drain process, intended for hot electron suppression, causes a further degradation in the ESD protection level.
Abstract: Scaling MOSFET's to one micron gate lengths and below has required the use of LDD and silicide clad source and drain diffusions. While these structural enhancements improve transistor performance and hot electron reliability they adversely effect ESD tolerance. In our experiments, we found that the use of silicide clad diffusions causes output buffer failure threshold levels to degrade by more than 50% from what is observed without silicided diffusions. In addition the use of the graded drain process, intended for hot electron suppression, causes a further degradation in the ESD protection level. For the first time we show that graded drain devices dissipate more power at a given current level when operating in the low impedance snap-back mode. In addition, experimental and theoretical results predicting ESD degradation due to the low resistance silicides are correlated with output buffer ESD performance. Finally, the role of the parasitic bipolar device, present in all CMOS output buffers, has been identified as providing an additional current path to ground during an electrostatic discharge.
TL;DR: In this paper, the lateral surface superlattice and the quasi-one-dimensional (QoD) device are described and projections made with regard to lithographic techniques for future electronic systems based on sub-100 nm linewidth devices.
Abstract: Two new types of Si metal‐oxide‐semiconductor field‐effect transistor (MOSFET) devices have been fabricated and tested which involve a dual gate structure, the lower one being a W grating of 0.2 μm period, 0.1 μm linewidth. These devices, the lateral surface superlattice and the quasi‐one‐dimensional device, explore the regime where quantum mechanical effects become important. Fabrication techniques are described and projections made with regard to lithographic techniques for future electronic systems based on sub‐100 nm linewidth devices. X‐ray lithography at λ∼1 nm can provide linewidth control ≲10 nm and high pixel‐transfer rate. The mask‐to‐substrate gap is constrained by diffraction. However, with a resist of sufficiently high contrast (and low sensitivity to avoid edge raggedness) linewidths of 50 nm should be feasible in high volume production at mask–substrate gaps of a few μm.