Showing papers on "MOSFET published in 1988"

New method for the extraction of MOSFET parameters

Abstract: A new method for the extraction of the MOSFET parameters is presented. The method, which relies on combining drain current and transconductance transfer characteristics, enables reliable values of the threshold voltage V/sub t/, the low field mobility mu /sub 0/ and the mobility attenuation coefficient theta to be obtained.

An analytical model for the steady-state and transient characteristics of the power insulated-gate bipolar transistor

Abstract: An analytical model for the power Insulated-Gate Bipolar Transistor (IGBT) is developed. The model consistently describes the IGBT steady-state current-voltage characteristics and switching transient current and voltage waveforms for all loading conditions. The model is based on the equivalent circuit of a MOSFET which supplies the base current to a low-gain, high-level injection, bipolar transistor with its base virtual contact at the collector end of the base. The basic element of the model is a detailed analysis of the bipolar transistor which uses ambipolar transport theory and does not assume the quasi-static condition for the transient analysis. This analysis differs from the previous bipolar transistor theory in that (1) the relatively large base current which flows from the collector end of the base is properly accounted for, and (2) the component of current due to the changing carrier distribution under the condition of a moving collector-base depletion edge during anode voltage transitions is accounted for. Experimental verification of the model using devices with different base lifetimes is presented for the on-state current-voltage characteristics, the steady-state saturation current, and the current and voltage waveforms for the constant voltage transient, the inductive load transient, and the series resistor-inductor load transient.

A new discretization strategy of the semiconductor equations comprising momentum and energy balance

Abstract: A discretization scheme is applied to the hydrodynamic model for semiconductor devices that generalizes the Scharfetter-Gummel method to both the momentum-conservation and the energy-conservation equations. The major advantages of the scheme are: (1) the discretization is carried out without neglecting any terms, thus providing a satisfactory description of such effects as velocity overshoot and carrier heating; and (2) the resulting equations lend themselves to a self-consistent solution procedure similar to those currently used to solve the simpler drift-diffusion equations. Two-dimensional steady-state simulations of an n-channel MOSFET and of an n-p-n BJT (bipolar junction transistor) have been carried out by means of an improved version of the program HFIELDS. Carrier-temperature plots have been obtained with a reasonable computational effort, demonstrating the efficiency of this technique. The results have been compared with those obtained with the standard drift-diffusion model and significant differences in the electron concentration have been found, especially at the drain end of the MOSFET channel. >

Characterization of device parameters in high-temperature metal-oxide-semiconductor field-effect transistors in β-SiC thin films

Abstract: Both inversion‐ and depletion‐mode n‐channel metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) have been fabricated on β‐SiC thin films grown by chemical‐vapor deposition. The inversion‐mode devices were made on in situ doped (Al) p‐type β‐SiC(100) thin films grown on Si(100) substrates. The depletion‐mode MOSFETs were made on n‐type β‐SiC(111) thin films grown on the Si(0001) face of a 6H α‐SiC substrates. Stable saturation and low subthreshold currents were achieved at drain‐source voltages exceeding 5 and 25 V for the inversion‐mode and depletion‐mode devices, respectively. The transconductance increased with temperature up to 673 K for the short‐gate‐length devices, of either mode, and then decreased with further increases in temperature. It is proposed that the transconductances and threshold voltages for the inversion‐mode devices are greatly affected by minority‐carrier injection from the source. Stable transistor action was observed for both types of devices at temperatures up to 823 K,...

Evolution of the MOS transistor-from conception to VLSI

Abstract: Historical developments of the metal-oxide-semiconductor field-effect transistor (MOSFET) during the last 60 years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triode structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon. MOSFET in 1960. A survey is then made of the milestones of the past 30 years leading to the latest submicron silicon logic CMOS (complementary MOS) and BICMOS (bipolar-junction transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. The status of the submicron lithographic technologies is summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. The use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed. >

Trench power MOSFET device

Abstract: A trench power MOSFET device is disclosed wherein the method of manufacturing produces a high density MOSFET cell with good breakdown characteristics.

A study of the leakage mechanisms of silicided n+/p junctions

Abstract: Leakage mechanisms for shallow, silicided, n+/p junctions have been investigated. This study consists of two parts: (a) the isolation of the processing steps that cause junction leakage, and (b) the study of the mechanism for a particular process that causes leakage. Reactive ion etching, improper junction, silicide formation procedures, ion mixing, and mechanical stress are found responsible for junction leakage, although through different mechanisms. Two mechanisms have been identified for junction leakage: (a) generation centers in the depletion region caused by deep levels from damage, or from impurities, and (b) Fowler–Nordheim tunneling caused by irregularities at the silicide/silicon interface at high reverse bias. Junction leakage can be avoided by carefully designing the details of silicide and junction formation and by carefully fine‐tuning the processing steps to prevent damage of the Si substrate after forming the junction. The best junctions are made by implanting As into CoSi2 and by driving the As into Si from the silicide at 800 °C. The lower temperature drive is possible since all ion damage is contained within the silicide, leaving no damage in the Si substrate to anneal out. Very shallow, silicided, n+/p junctions can be fabricated reproducibly. These junctions demonstrate the same electrical characteristics as deeper, nonsilicided junctions, indicating that there is no fundamental barrier prohibiting fabrication of low‐leakage, silicided junctions.

A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD

Abstract: A charge-based large-signal transient model for the enhancement-mode thin-film SOI MOSFET in strong inversion, suitable for circuit simulators such as SPICE, is presented. The model physically accounts for the predominant short-channel effects in MOSFET's (namely threshold-voltage reduction, drain-induced conductivity enhancement, velocity saturation with mobility degradation, and channel-length modulation) as influenced by the unique features of thin SOI devices (i.e. the presence of an additional back gate and the possibility of a floating film body). It includes a description of generation current due to (weak) impact ionization, which can have a far greater influence on SOI (as compared to bulk) MOSFET's due to the associated charging of the floating body. Measurements on devices of varied geometry show good agreement with model predictions. The model is implemented in SPICE2, to be used for circuit and device CAD, and TECAP, for automated parameter extraction. >

Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFETs

Abstract: A convenient optimization method using a circuit simulator SPICE2 with realistic models for short-channel MOSFETs and capacitances is described. By using this method, MOSFET size optimization is carried out and it is found that the optimum size ratio of NMOS versus PMOS shifts from the simple theory of S. Flannagan (ibid., vol 20, p.880-2, 1985). NMOS size should be larger than PMOS size. This is due to the velocity saturation carriers in short-channel MOSFETs. The effects of the parasitic PMOS and NMOS sizes, supply voltage, and temperature are also considered. It is also shown that the symmetry of the cross-coupled NANDs and insertion of cascaded inverters do not help the optimization. >

Conductance technique in MOSFETs: Study of interface trap properties in the depletion and weak inversion regimes

Abstract: A new and accurate approach to a.c. conductance measurements on MOSFETs is presented. It is shown that the conductance technique can be used to study interface trap properties in most of the silicon band-gap by direct measurement on a single MOSFET. The equivalent circuit is analyzed and the influence of the channel length on the inversion layer response is discussed in detail. It is shown that the channel time constant is mainly determined by the channel length. For small channel lengths L

A review of thermal characterization of power transistors

Abstract: The thermal characteristics of power transistors and their measurement are discussed. The devices discussed include bipolar transistors and metal-oxide-semiconductor field-effect transistors (MOSFETs). Measurement problems common to these devices are addressed, such as general methods for measuring device temperature, control of thermal environment, selection of a temperature-sensitive electrical parameter, measurement of temperature-sensitive electrical parameters, reasons for measuring temperature, and temperature measurement of integrated power devices. Procedures for detecting nonthermal switching transients, extrapolation of the measured temperature to the instant of switching, and for measuring the temperature of Darlington transistors are included. The needs for thermal characterization of evolving devices such as high voltage and power integrated circuits and merged bipolar/MOSFET devices are mentioned. >

Inverse-narrow-width effects and small-geometry MOSFET threshold voltage model

Abstract: An analytical threshold voltage model is developed based on the results from a three-dimensional MOSFET simulator, called MICROMOS. The model is derived by solving Poisson's equation analytically and is used to predict the threshold voltage of MOSFETs with fully recessed oxide isolation (the trench structure). Coupling was observed between the short-channel effect and the inverse-narrow-width effect. The coupling results from the mutual modulation of the depletion depth and is used to extend the analytical inverse narrow-width model to small-geometry devices. The model is compared with experimental data obtained from the literature as well as with the three-dimensional simulator. Satisfactory agreement for channel length down to 1.5 mu m and channel widths down to 1 mu m has been obtained. >

Gate controllable lightly doped drain mosfet devices

Abstract: An LDD MOSFET structure in which gate sidewall spacers are formed of polycrystalline silicon and electrically shorted to the gate to extend gate control over the LDD region surface oxide and thereby reduce and control interface charge trapping without increasing substrate currents.

Lightly doped drain MOSFET with reduced on-resistance

Abstract: Construction method and apparatus for lightly doped drain MOSFET that has low or minimum drift on-state resistance and maintains high voltage blocking in the off-state. Temperature sensitivity of the electrical properties of the MOSFET are also reduced relative to MOSFETs produced by processes such as SIPOS. Voltage level shifting of p-channel and n-channel MOSFETs, produced according to the invention, relative to another voltage level is easily accomplished.

Hot‐carrier light emission from silicon metal‐oxide‐semiconductor devices

Abstract: Light emitted from energetic electrons and holes near the drain region of Si field‐effect transistor devices is measured spectrally resolved in the important energy range about the band gap. Using a sensitive Ge detector we examine the spectral range from 0.75 to 1.55 eV in order to identify and study the recombination of impact ionization generated electron‐hole pairs. Two distinct recombination lines are observed superposed on a continuum background.

Modelling and simulation of power mosfet's and power diodes

Abstract: A model of the power Mosfet is modified, improved and implemented into SPICE. A method for parameter extraction from electrical measurements is developed. The simulation results show a good agreement with t he measurements. The model considered is simple and accurate. The switching behavior of Mosfet's was simulated and analyzed. The parasitic oscillation in parallel circuits has been investigated. A favorable solution to avoid this undesirable effect is proposed and proved. A fundamental study was carried out to develop a new electric-analyti cal model for the PIN power diode. The internal processes d uring s witching were investigated by using physical device simulation. For the dide model a one-dimensicnal solution was derived. This solution includes the static and the dynamic behavior with the reverse recovery effect and high current effects. The simulations correlate well with the measurements.

Method for making silicide interconnection structures for integrated circuit devices

Abstract: A method for forming a contact to a selective region of an integrated circuit characterized by the steps of: forming a layer of refractory metal over and around the selected region; forming a layer of amorphous silicon over the layer of refractory metal; patterning the amorphous silicon into an elongated strip which extends away from the selected region; annealing the integrated circuit to convert the strip of amorphous silicon into a silicide path; and removing the unreacted refractory metal. The method of the present invention can be used to extend a contact to the source, drain, or gate of a MOSFET from the top of an adjacent section of field oxide, and can also be used as a method for local interconnection of IC devices, such as CMOS devices.

On-line monitoring of the mosfet device junction temperature by computation of the threshold voltage

Abstract: A method for an on-line junction temperature measurement is introduced. The circuit allows the calibration of a real-time thermal model of a power MOSFET. A regular calibration of the real-time model provides an accurate thermal flux model over the lifetime of the power MOSFET. The measurement of threshold voltage is used to determine the device temperature. The paper presents the on-line measurement method, the circuit and test results.

High power transistor with voltage, current, power, resistance, and temperature sensing capability

Abstract: One or more probe cells are use to sense voltage and current accurately and without affecting performance of the switching device (T 1 ) or the load. In addition, power, resistance, and temperature can be determined from the voltage and current. Voltage sensing is accomplished by placing a large value resistor (R 3 ) (much greater than the on-resistance of the probe cell(s) between the probe cell(s) and its low voltage connection (the common source terminal in the case of MOSFET's). Since the resistor (R 3 ) is much greater than the cell resistance, the voltage across the resistor is nearly equal to the voltage across the power chip (10). Current probe cells are isolated from switching cells (27) in MOSFET power chips. The cell locations adjacent the probe cells are occupied by cells (50) that are inactive by virtue of their not having had a source region implanted therein during the chip fabrication. This isolation prevents any crosstalk between probe and switching cells.

Simulation of hot-electron trapping and aging of nMOSFETs

Abstract: An analysis of the degradation of 1- mu m-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO/sub 2/ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the device's lifetime by simulated aging is proposed. >

Conductivity-modulation metal oxide semiconductor field effect transistor

Abstract: A conductivity-modulation MOSFET employs a substrate (30) of an N type conductivity as its N base. A first source layer (34) of a heavily-doped N type conductivity is formed in a P base layer (32) formed in the N base (30). A source electrode (38) electrically conducts the P base (32) and the source (34). A first gate electrode (36) insulatively covers a channel region (CH1) defined by the N⁺ source layer (34) in the P base (32). A P drain layer (44) is formed on an opposite substrate surface. An N⁺ second source layer (46) is formed in a P type drain layer (44) by diffusion to define a second channel region (CH2). A second gate electrode (40) insulatively covers the second channel region (CH2), thus providing a voltage-controlled turn-off controlling transistor. A drain electrode (48) of the MOSFET conducts the P type drain (44) and second source (46). When the turn-off controlling transistor is rendered conductive to turn off the MOSFET a "shorted anode structure" is temporarily formed wherein the N type base (30) is short-circuited to the drain electrode (48), whereby case, the flow of carriers accumulated in the N type base (30) into the drain electrode is facilitated to accelerate dispersion of carriers upon turn-off of the transistor.

A new experimental method to determine the saturation voltage of a small-geometry MOSFET

Abstract: A new extraction method which determines the saturation voltage of a small-geometry MOSFET directly from the measured data is proposed and investigated. In this method, a special function G is formed and the drain-source saturation voltage is identified as the voltage of the peak point in a plot of G vs the drain-source voltage. Since the method is based on a general device theory, it is virtually independent of any device model and quite versatile and applicable for all MOSFETs. In addition, no given device parameters or iterations are required in the method. To verify the new method, SPICE MOS models are used as a calculation example. Moreover, the method is also applied to various fabricated MOSFETs to determine the saturation voltage. It is found that the saturation voltage can be definitely determined without ambiguity and the determined saturation voltage is quite close to that from the optimal extractions. Thus the method can be incorporated into the parameter extraction and the device modeling for small-geometry MOSFETs.

Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1/4- mu m-width MOSFETs

Abstract: The dependence of MOSFET gate controllability on the field-isolation scheme is investigated using three-dimensional simulation. It is found that a fully-recessed-oxide (trench) isolated MOSFET has a steep subthreshold characteristic and high transconductance in comparison with a nonrecessed device. These features result from the small depletion capacitance due to the crowding of the gate's fringing field at the channel edge. It is also found that the gate and diffused line capacitances in the case of fully-recessed-oxide isolation are small, so that high switching speed operation can be expected. These features are enhanced with a reduction in the channel width, especially for lower-submicrometer-width MOSFETs. A drawback of a fully-recessed-oxide MOSFETs is its low threshold voltage. However, the leakage current is not as large as that inferred from the inverse narrow-channel effect because of its steep subthreshold characteristic. Several countermeasures for this low threshold voltage are discussed. >

Electron energy distribution for calculation of gate leakage current in MOSFETs

Abstract: A new equation, which does not require any fitting parameters, has been developed to predict gate leakage current density in MOSFETs. The equation is based upon a non-Maxwellian hot-electron distribution function derived from the Boltzmann transport equation, and utilizes a physically calculated local electron temperature. The model predicts gate currents for a sample submicron MOSFET that are in good agreement with experiment.

Circuit including a combined insulated gate bipolar transistor/MOSFET

Abstract: An IGBT and FET are integrated in a common semiconductor body and share common source/emitter, base and drift regions and an insulated gate electrode. The ON-resistance and turn-off time of this device can be controlled by connecting the drain and collector electrodes to one main terminal for the device with a resistor between either the drain region/drift region interface or the collector junction and the main terminal of the device.

Modelling of ohmic MOSFET operation at very low temperature

Abstract: A model for the ohmic operation of a MOS transistor at very low temperature (4–40 K) is presented. The model is based on a quantum treatment of the inversion layer and on a specific low temperature mobility law. It enables a good description of the MOSFET transfer characteristics (field effect mobility, drain current) as a function of gate voltage and predicts the temperature dependence of the maximum field effect mobility and of the threshold voltage.

Numerical experiment for 2500 V double gate bipolar-mode MOSFETs (DGIGBT) and analysis for large safe operating area (SOA)

Abstract: A double-gate bipolar-mode MOSFET (DGIGBT) is proposed as a high-speed switching device exceeding 2500 V. The DGIGBT inherently has a reverse conducting diode. It is numerically predicted that the device will attain a better tradeoff between turn-off time and forward voltage than an 1800-V single-gate device. It is experimentally confirmed that DGIGBTs have an SOA exceeding the theoretical power dissipation limit for an n-p-n transistor, and it is shown why the SOA can exceed this limit. >

Resistorless electrostatic discharge protection device for high speed integrated circuits

Abstract: An electrostatic discharge protection circuit without the use of a series resistor is described. MOSFET transistors with a turn-on voltage above the postive supply voltage but below the breakdown voltage are used. In one embodiment, parasitic bipolar transistors formed in conjunction with the MOSFETs are employed for further protection.

Observation of mobility enhancement in ultrathin SOI MOSFETs

Abstract: The mobility in n-channel SOI MOSFETs exhibits a significant increase as the SOI film becomes thinner than 1000 A. At a 500 A SOI thickness, the mobility values are distributed in the 700–1100 cm2/Vs range, which are obviously higher than the value in a bulk MOSFET having an identical doping concentration. The observed mobility enhancement has been explained by a decrease in the vertical electric field, associated with the complete depletion of the SOI film.

A mobility model for submicrometer MOSFET simulations including hot-carrier-induced device degradation

Abstract: The model presented includes the quantum effects of electrons in the inversion layer proposed by S.A. Schwarz and S.E. Russek (1983) and the surface scattering effects due to the interfacial charges. By comparison with experimental data from scaled MOSFETs, the limitation of K. Yamaguchi's (1983) mobility model in submicrometer device simulations is implied, while the quantum channel broadening effects have been proven significant in turn. In addition, it is shown that the modeling of the screening effect of Coulomb scattering plays an important role in simulating the hot-carrier-induced MOSFET degradation. The model can predict the current-voltage characteristics within 5% accuracy for scaled MOSFETs down to 0.5- mu m, as well as the degradation of electrical characteristics due to hot-carrier effects for submicrometer MOSFETs. >