Showing papers on "MOSFET published in 1991"

Silicon-on-Insulator Technology: Materials to VLSI

Abstract: 1 Introduction.- 2 SOI Materials.- 2.1 Introduction.- 2.2 Heteroepitaxial techniques.- 2.2.1 Silicon-on-Sapphire (SOS).- 2.2.2 Other heteroepitaxial SOI materials.- 2.2.2.1 Silicon-on-Zirconia (SOZ).- 2.2.2.2 Silicon-on-Spinel.- 2.2.2.3 Silicon on Calcium Fluoride.- 2.3 Dielectric Isolation (DI).- 2.4 Polysilicon melting and recrystallization.- 2.4.1 Laser recrystallization.- 2.4.2 E-beam recrystallization.- 2.4.3 Zone-melting recrystallization.- 2.5 Homoepitaxial techniques.- 2.5.1 Epitaxial lateral overgrowth.- 2.5.2 Lateral solid-phase epitaxy.- 2.6 FIPOS.- 2.7 Ion beam synthesis of a buried insulator.- 2.7.1 Separation by implanted oxygen (SIMOX).- 2.7.1.1 "Standard"SIMOX.- 2.7.1.2 Low-dose SIMOX.- 2.7.1.3 ITOX.- 2.7.1.4 SMOXMLD.- 2.7.1.5 Related techniques.- 2.7.1.6 Material quality.- 2.7.2 Separation by implanted nitrogen (SIMNI).- 2.7.3 Separation by implanted oxygen and nitrogen (SIMON).- 2.7.4 Separation by implanted Carbon.- 2.8 Wafer Bonding and Etch Back (BESOI).- 2.8.1 Hydrophilic wafer bonding.- 2.8.2 Etch back.- 2.9 Layer transfer techniques.- 2.9.1 Smart-Cut(R).- 2.9.1.1 Hydrogen / rare gas implantation.- 2.9.1.2 Bonding to a stiffener.- 2.9.1.3 Annealing.- 2.9.1.4 Splitting.- 2.9.1.5 Further developments.- 2.9.2 Eltran(R).- 2.9.2.1 Porous silicon formation.- 2.9.2.2 The original Eltran(R) process.- 2.9.2.3 Second-generation Eltran(R) process.- 2.9.3 Transferred layer material quality.- 2.10 Strained silicon on insulator (SSOI).- 2.11 Silicon on diamond.- 2.12 Silicon-on-nothing (SON).- 3 SOI Materials Characterization.- 3.1 Introduction.- 3.2 Film thickness measurement.- 3.2.1 Spectroscopic reflectometry.- 3.2.2 Spectroscopic ellipsometry.- 3.2.3 Electrical thickness measurement.- 3.3 Crystal quality.- 3.3.1 Crystal orientation.- 3.3.2 Degree of crystallinity.- 3.3.3 Defects in the silicon film.- 3.3.3.1 Most common defects.- 3.3.3.2 Chemical decoration of defects.- 3.3.3.3 Detection of defects by light scattering.- 3.3.3.4 Other defect assessment techniques.- 3.3.3.5 Stress in the silicon film.- 3.3.4 Defects in the buried oxide.- 3.3.5 Bond quality and bonding energy.- 3.4 Carrier lifetime.- 3.4.1 Surface Photovoltage.- 3.4.2 Photoluminescence.- 3.4.3 Measurements on MOS transistors.- 3.4.3.1 Accumulation-mode transistor.- 3.4.3.2 Inversion-mode transistor.- 3.4.3.3 Bipolar effect.- 3.5 Silicon/Insulator interfaces.- 3.5.1 Capacitance measurements.- 3.5.2 Charge pumping.- 3.5.3 ?-MOSFET.- 4 SOI CMOS Technology.- 4.1 SOI CMOS processing.- 4.1.1 Fabrication yield and fabrication cost.- 4.2 Field isolation.- 4.2.1 LOCOS.- 4.2.2 Mesa isolation.- 4.2.3 Shallow trench isolation.- 4.2.4 Narrow-channel effects.- 4.3 Channel doping profile.- 4.4 Source and drain engineering.- 4.4.1 Silicide source and drain.- 4.4.2 Elevated source and drain.- 4.4.3 Tungsten clad.- 4.4.4 Schottky source and drain.- 4.5 Gate stack.- 4.5.1 Gate material.- 4.5.2 Gate dielectric.- 4.5.3 Gate etch.- 4.6 SOI MOSFET layout.- 4.6.1 Body contact.- 4.7 SOI-bulk CMOS design comparison.- 4.8 ESD protection.- 5 The SOI MOSFET.- 5.1 Capacitances.- 5.1.1 Source and drain capacitance.- 5.1.2 Gate capacitance.- 5.2 Fully and partially depleted devices.- 5.3 Threshold voltage.- 5.3.1 Body effect.- 5.3.2 Short-channel effects.- 5.4 Current-voltage characteristics.- 5.4.1 Lim & Fossum model.- 5.4.2 C?-continuous model.- 5.5 Transconductance.- 5.5.1 gm/ID ratio.- 5.5.2 Mobility.- 5.6 Basic parameter extraction.- 5.6.1 Threshold voltage and mobility.- 5.6.2 Source and drain resistance.- 5.7 Subthreshold slope.- 5.8 Ultra-thin SOI MOSFETs.- 5.8.1 Threshold voltage.- 5.8.2 Mobility.- 5.9 Impact ionization and high-field effects.- 5.9.1 Kink effect.- 5.9.2 Hot-carrier degradation.- 5.10 Floating-body and parasitic BJT effects.- 5.10.1 Anomalous subthreshold slope.- 5.10.2 Reduced drain breakdown voltage.- 5.10.3 Other floating-body effects.- 5.11 Self heating.- 5.12 Accumulation-mode MOSFET.- 5.12.1 I-V characteristics.- 5.12.2 Subthreshold slope.- 5.13 Unified body-effect representation.- 5.14 RF MOSFETs.- 5.15 CAD models for SOI MOSFETs.- 6 Other SOI Devices.- 6.1 Multiple-gate SOI MOSFETs.- 6.1.1 Multiple-gate SOI MOSFET structures.- 6.1.1.1 Double-gate SOI MOSFETs.- 6.1.1.2 Triple-gate SOI MOSFETs.- 6.1.1.3 Surrounding-gate SOI MOSFETs.- 6.1.1.4 Triple-plus gate SOI MOSFETs..- 6.1.2 Device characteristics.- 6.1.2.1 Current drive.- 6.1.2.2 Short-channel effects.- 6.1.2.3 Threshold voltage.- 6.1.2.4 Volume inversion.- 6.1.2.5 Mobility.- 6.2 MTCMOS/DTMOS.- 6.3 High-voltage devices.- 6.3.1 VDMOS and LDMOS.- 6.3.2 Other high-voltage devices.- 6.4 Junction Field-Effect Transistor.- 6.5 Lubistor.- 6.6 Bipolar junction transistors.- 6.7 Photodiodes.- 6.8 G4 FET.- 6.9 Quantum-effect devices.- 7 The SOI MOSFET in a Harsh Environment.- 7.1 Ionizing radiations.- 7.1.1 Single-event phenomena.- 7.1.2 Total dose effects.- 7.1.3 Dose-rate effects.- 7.2 High-temperature operation.- 7.2.1 Leakage current.- 7.2.2 Threshold voltage.- 7.2.3 Output conductance.- 7.2.4 Subthreshold slope.- 8 SOI Circuits.- 8.1 Introduction.- 8.2 Mainstream CMOS applications.- 8.2.1 Digital circuits.- 8.2.2 Low-voltage, low-power digital circuits.- 8.2.3 Memory circuits.- 8.2.3.1 Non volatile memory devices.- 8.2.3.2 Capacitorless DRAM.- 8.2.4 Analog circuits.- 8.2.5 Mixed-mode circuits.- 8.3 Niche applications.- 8.3.1 High-temperature circuits.- 8.3.2 Radiation-hardened circuits.- 8.3.3 Smart-power circuits.- 8.4 Three-dimensional integration.

A simple MOSFET model for circuit analysis

Abstract: A simple, general, yet realistic MOSFET model, the nth power law MOSFET model, is introduced. The model can express I-V characteristics of short-channel MOSFETs at least down to 0.25- mu m channel length and of resistance inserted MOSFETs. The model evaluation time is about 1/3 of the evaluation time of the SPICE3 MOS LEVEL3 model. The model parameter extraction is done by solving single variable equations and thus can be done within a second, unlike the fitting procedure with expensive numerical iterations used for the conventional models. The model also permits analytical treatment of circuits in the short-channel region and plays the role of a bridge between complicated MOSFET current characteristics and circuit behavior in the deep-submicrometer region. >

Delay analysis of series-connected MOSFET circuits

Abstract: In order to derive analytical delay expressions for CMOS gates in the submicrometer region, a realistic MOS model which incorporates an nth power law MOS model is developed. Closed-form delay formulas are obtained for CMOS inverters and series-connected MOSFET structures (SCMSs) that include short-channel effects. It is shown that the ratio of the delay of NAND/NOR to the delay of the inverter becomes smaller in the submicrometer region, because the V/sub DS/ and V/sub GS/ of each MOSFET in the SCMS are smaller than those of an inverter MOSFET. The smaller voltages in turn mitigate and relax the severe carrier velocity saturation in miniaturized MOSFETs. The results of the analysis for submicrometer VLSI designs show that if the maximum number of series-connected MOSFETs is considered to be five in 2- mu m designs, then the number can be increased to six or seven in the submicrometer circuit design. In typical cases in VLSI designs, the delay ratio for N-SCMS is much less than N/sup 2/. The delay dependence on input terminal position for SCMS structures is also described. >

Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's

Abstract: Floating-body effects triggered by impact ionization in fully depleted submicrometer silicon-on-insulator (SOI) MOSFETs are analyzed based on two-dimensional device simulations. The parasitic bipolar junction transistor (BJT) effects are emphasized, but the kink effect and its disappearance in the fully depleted device are first explained physically to provide a basis for the BJT analysis. The results of simulations of the BJT-induced breakdown and latch phenomena are given, and parametric dependences are examined to give physical insight for optimal design. The analysis further relates the DC breakdown and latch mechanisms in the fully depleted submicrometer SOI MOSFET to actual BJT-related problems in an operating SOI CMOS circuit. A comprehensive understanding of the floating-body effects is attained, and a device design to control them utilizing a lightly doped source (LDS) is suggested and shown to be feasible. >

Enhancement-mode quantum-well Ge/sub x/Si/sub 1-x /PMOS

Abstract: The authors demonstrate the feasibility of a p-channel quantum-well MOSFET on a Ge/sub x/Si/sub 1-x//Si heterostructure. The advantages of the enhancement-mode p-channel MOSFET device compared to GeSi MODFETs are its high impedance, channel mobility, and channel transconductance. The device shows good saturation and cutoff behaviour. A saturation transconductance of 64 mS/mm was measured for a 0.7- mu m channel device at a drain-to-source voltage of -2.5 V. The channel mobility was found to be higher than that of a similarly processed Si p-channel MOSFET. >

High-gain lateral bipolar action in a MOSFET structure

Abstract: A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25- mu m base width have been successfully fabricated in a p-well 0.25- mu m bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported. >

Impact of the vertical SOI 'DELTA' structure on planar device technology

Abstract: A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an ultrathin SOI MOSFET that has high crystalline quality, as good as that of conventional bulk single-crystal devices. Experiments and three-dimensional simulations have shown that this new gate structure has effective channel control and that the vertical ultrathin SOI structure provides superior device characteristics: reduction in short-channel effects, minimized subthreshold swing, and high transconductance. >

Switched-current circuit design issues

Abstract: Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%. >

An intelligent MOS transistor featuring gate-level weighted sum and threshold operations

Abstract: A novel functional MOS transistor which behaves much more intelligently than a mere switching device has been developed The device has a floating gate whose potential is controlled by a plural number of input gates via capacitive coupling The transistor is called a 'neuron MOSFET' due to its similarity to biological neurons in that the transistor turns on when the weighted sum of all input signals exceeds a certain threshold value Test devices were fabricated using a double-polysilicon NMOS process The analysis of the basic device operation and its experimental verification are presented A number of interesting applications of the neuron MOSFET are described which include a variable threshold transistor, a neuron circuit, a single-gate D/A (digital-to-analog) converter, and a soft hardware logic circuit >

Extension of RESURF principle to dielectrically isolated power devices

Abstract: The RESURF (reduced surface field) principle has been extended to dielectrically isolated power devices including the effect of the formation of an inversion layer under the isolating oxide. Two device structures that allow high voltage operation have been investigated. Extensive two-dimensional simulations have been performed to relate the breakdown voltage to the doping and length of the drift region, and the thicknesses of the silicon layer and isolating oxide. It has been shown that lateral devices with breakdown voltages up to 600 V can be obtained. >

A floating-gate MOSFET with tunneling injector fabricated using a standard double-polysilicon CMOS process

Abstract: A floating-gate MOSFET which is programmable in both directions by Fowler-Nordheim tunneling and is fabricated using an inexpensive standard 2- mu m double-polysilicon CMOS technology is discussed. Tunneling occurs at a crossover of polysilicon 1 with polysilicon 2. Device layout and basic device characteristics are presented, and recommendations for efficient programming are given. This is the first floating-gate FET with a tunneling injector fabricated in standard technology that has close to symmetric programming characteristics for both charging and discharging of the gate. >

Insulated gate field-effect transistor with pulse-shaped doping

Abstract: A silicon MOSFET is provided, which can be made with an effective channel length of under one micrometer without incurring severe short-channel effects. The MOSFET includes first and second channel regions located between the source and drain regions, the first channel region overlaying the second channel region. The second channel region has a higher carrier density than the first channel region, and functions as a buried ground plane.

Raised source/drain MOSFET with dual sidewall spacers

Abstract: A raised source/drain (S/D) MOSFET with sidewall spacers formed both before and after selective epitaxial silicon deposition in S/D regions is discussed. The second spacer overlies any faceted regions of the epitaxial silicon near the gate edge and has advantages for MOSFETs with implant-doped or in-situ doped epitaxial silicon regions. In particular, the spacer can prevent S/D dopants from being implanted through any thinner faceted regions near the gate edge, which would otherwise result in a deeper than desired junction depth in the silicon substrate. Additionally, the spacer can prevent source-to-substrate salicide shorts through the thinner faceted regions. >

Dynamic effects in SOI MOSFET's

Abstract: The use of SOI (silicon-on-insulator) and conventional bulk MOSFETs by circuit designers is similar in a wide range of functions for logic purposes. Differences may appear when asynchronous design is used, due to floating body effects. The consequences of direct coupling between drain and source of a MOSFET in the OFF-state are discussed, and the characterization of this effect for various SOI technologies is presented. Two mechanisms are proposed to explain the results: a capacitive coupling between drain and floating body, which corresponds to a drain to source coupling when the floating body follows the source potential; and a dynamic bipolar effect in which the base current is constituted by the gate oxide charge in accumulated mode. This effect leads to a parasitic drain to source discharge, which can result in an upset in a SRAM memory cell or in a dynamic latch. It is found that a careful design must be done if functions like dynamic or static latch are needed. >

SiGe-channel n-MOSFET by germanium implantation

Abstract: The first n-SiGe-channel MOSFETs fabricated using high-dose germanium implantation and solid-phase epitaxy are reported The polysilicon-gate MOSFETs were fabricated in the same chip in which conventional polysilicon-gate n-MOSFETs were made and their electrical characteristics are compared The SiGe-channel MOSFETs show some significantly better electrical characteristics as compared to the silicon-channel MOSFETs For example, the SiGe MOSFETs show higher drain conductance in the triode region and higher transconductance overall The threshold voltage of the SiGe MOSFET appears to be smaller and the carrier mobility in the channel appears to be higher >

Direct observation of interfacial point defects generated by channel hot hole injection in n‐channel metal oxide silicon field effect transistors

Abstract: Using a modified electron spin resonance technique known as spin‐dependent recombination, we have found that channel hot hole injection in n channel metal oxide silicon (MOS) transistors creates the trivalent silicon dangling bond defect known as the Pbo center. This letter reports the first direct identification of the atomic structure of interfacial point defects created by channel hot carrier stressing in MOS transistors.

Power vdmosfet with schottky on lightly doped drain of lateral driver fet

Abstract: A monolithic semiconductor device comprises a VDMOS transistor having first and second main electrodes and a control electrode, and a lateral MOSFET having first and second main electrodes and a control electrode, wherein one of the first and second electrodes of the lateral MOSFET has a lower doping concentration than that of the first and second main electrodes of the VDMOS transistor for forming a Schottky barrier diode.

Semiconductor memory element and method of fabricating the same

Abstract: In a gain-cell type semiconductor memory element having a first MOSFET and a second MOSFET, the sources of the first and second MOSFETs are connected to a bit line, the drain of the first MOSFET and the gate of the second MOSFET are connected to each other to serve as a charge storage region, the gate of the first MOSFET is connected to a write word line, the drain of the second MOSFET is connected to a power supply line, and the channel region of the second MOSFET is capacitively coupled via an insulating layer with a read word line thereby to receive substrate biasing by capacitive coupling from the read word line.

Analysis of p/sup +/ poly Si double-gate thin-film SOI MOSFETs

Abstract: The authors have fabricated planar p/sup +/ poly Si double-gate thin-film SOI (silicon-on-insulator) nMOSFETs using wafer bonding. The fabricated devices have shown a transconductance, Gm, exceeding twice that of the single-gate SOI-MOSFET. It was confirmed that conduction in the double-gate SOI MOSFET originates from a fully flat potential and charge injection. An analytical model developed by the authors has displayed electrical characteristics that agree well with those of the fabricated devices. >

Physics and technology of ultra short channel MOSFET devices

Abstract: It is pointed out that, as MOSFET channel lengths are scaled below about 0.15 mu m, nonstationary carrier transport effects become increasingly important. These effects can result in increased drain current over what is expected from stationary transport theory (i.e. velocity saturation), and in decreased hot-carrier energy spectrum spread, or carrier temperature, leading to improved device reliability. However, the magnitude of these effects depends strongly not only on channel length but also on overall device design such as channel doping configuration, drain junction depth, etc. Besides minimization of junction depths, optimal device design requires a super-steep-retrograde channel doping, with surface doping concentration no higher than mid-10/sup 16/ cm/sup -3/. This can be achieved with indium doping for NMOS, and antimony or arsenic doping for PMOS extreme submicron transistors. >

Properties of ultra-thin wafer-bonded silicon-on-insulator MOSFET's

Abstract: Strong interface coupling effects on the subthreshold and transconductance characteristics have been experimentally observed and analytically modeled. For total depletion, the subthreshold swing reaches a nearly ideal value. The front channel subthreshold slope of ultrathin MOSFETs is very sensitive to the density of states at the buried Si-SiO/sub 2/ interface so that a thicker fully depleted film is preferable when the quality of this interface is poor. The transconductance reaches a maximum for total depletion. Simple theoretical models are proposed which explain the substantial variations of the transconductance and subthreshold slope as the opposite interface is scanned from inversion to total depletion and accumulation. These MOSFETs behave very well and demonstrate that high carrier mobilities and low densities of defects can be obtained at both interfaces even in ultrathin silicon-on-insulator (SOI) structures. >

Performance and reliability design issues for deep-submicrometer MOSFETs

Abstract: Device design constraints, such as threshold voltage variation due to short-channel and drain-induced-barrier-lowering effects, off-state leakage current due to punchthrough and gate-induced drain leakage, hot-carrier effects such as hot-electron degradation and avalanche breakdown, and time-dependent dielectric breakdown, are examined. The current-driving capability, ring-oscillator switching speed, and small-signal voltage gain are examined. The impact that each of these factors has on the allowable choice of MOSFET channel length, oxide thickness, and power supply voltage is examined. Based on experimental results, a set of design curves, using a set of typical performance and reliability criteria, is presented for deep-submicrometer nonlightly doped drain (non-LDD) n-channel devices. From these curves, the relative importance of each particular performance/reliability mechanism for a given technology and design criteria can be determined. Because the performance and reliability issues addressed are also relevant to other MOSFET technologies, the design guidelines can also be extended to other technologies, including p-channel and LDD devices. >

Physical understanding of low-field carrier mobility in silicon MOSFET inversion layer

Abstract: Experimental and theoretical studies of the gate field dependencies of the low-field mobilities of electrons and holes show that by changing surface orientations and oxidation conditions the two-dimensional electron gas formulation can successfully explain eta =1/3 (where eta is the weighting factor of mobile charge density used in calculating the effective field for the universal mobility curve) for

Nonvolatile random access memory device having transistor and capacitor made in silicon carbide substrate

Abstract: A random access memory (RAM) cell in 6H-SiC having storage times when all bias is removed long enough to be considered nonvolatile. The nonvolatile random access memory (NVRAM) cell comprises a bit line, a charge storage device in silicon carbide, and a transistor in silicon carbide connecting the charge storage device to the bit line. The bipolar NVRAM cell has a bipolar transistor with a base region, an emitter region, and a floating collector region, wherein the charge storage device in the bipolar NVRAM is a p-n junction adjacent the floating collector region of the cell. The metal-oxide-semiconductor (MOS) NVRAM has a MOS field effect transistor (MOSFET) with a channel region, a source region, and a drain region, wherein the charge storage device in the MOS NVRAM is a MOS capacitor adjacent the drain region of the MOSFET.

A circuit simulation model for high-frequency power MOSFETs

Abstract: A circuit simulation model suitable for modeling the static and dynamic switching characteristics of high-frequency power MOSFETs is reported. The model parameters were obtained from physical device layout, silicon doping, and measured electrical characteristics of power MOSFETs. Accurate voltage dependencies of the interelectrode capacitances were obtained from extensive two-dimensional device simulations. The voltage dependence of gate-drain capacitance was modeled using an analytic expression. The measured static current-voltage and transient-switching responses under resistive switching conditions are in excellent agreement with simulation results obtained from SPICE. The MOSFET subcircuit model was used to accurately predict the performance of a series-parallel resonant DC-DC converter using a multilevel system simulator. >

Practical application of MOSFET synchronous rectifiers

Abstract: The application of MOSFET synchronous rectifiers (SRs) to a forward power converter with resonant reset is analyzed. Under the assumptions of ideal gate-drive waveforms, the theoretical minimum losses are determined. The analysis shows that the gate charge and on-resistance of the current generation of power MOSFETs are low enough to yield a significant increase in rectifier efficiency. Two simple gate drive circuits are presented, and the effects of parasitic circuit inductances on the gate voltage waveforms are shown. The measured converter losses for these SR drive circuits are compared to the losses for the Schottky rectifiers, as well as to the theoretical minimum losses. For the 3.3 V output at load currents between 5 and 10 A, the losses approach the theoretical minimum. For higher load currents, the MOSFET body-drain diode causes losses during its reverse recovery, due to the nonideal timing of gate drive voltages. >

Scaling the Si metal‐oxide‐semiconductor field‐effect transistor into the 0.1‐μm regime using vertical doping engineering

Abstract: Conventional scaling of the Si MOSFET into the deep submicron regime requires high substrate doping levels. This extracts a severe speed penalty, if lower standby power consumption (i.e., good subthreshold behavior) is to be maintained. We explore the scaling of fully depleted silicon‐on‐insulator (SOI) structures, and show, both analytically and by numerical simulation, how the horizontal leakage is controlled by vertical doping engineering. Our analysis allows different structures to be evaluated in terms of a natural length scale indicating good subthreshold behavior. Finally, we describe how retrograde doping may be used to mimic the SOI concept in bulk Si. Our results show good subthreshold behavior in the deep submicron regime can be achieved without large junction capacitance, high threshold voltage, or heavy channel doping.

Observation of MOSFET degradation due to electrical stressing through gate-to-source and gate-to-drain capacitance measurement

Abstract: The authors present observations of changes in the gate capacitances of a MOSFET as a result of hot-carrier stressing and propose capacitance measurement as a method for evaluation of trapped charge. The effect of hot-carrier stressing on 2- mu m effective channel length n-channel MOSFETs was monitored by measuring the gate-to-source capacitance and the gate-to drain capacitance. It was found that after electrically stressing a junction of the transistor, capacitances associated with the stressed junction were reduced, whereas the capacitances of the unstressed junction were found to have increased. The observation is explained in terms of the change in channel potential near the stressed junction due to negative trapped charge. >

A new stacked cell structure for giga-bit DRAMs using vertical ultra-thin SOI (DELTA) MOSFETs

Abstract: Summary form only given The first stacked DRAM (dynamic RAM) cell using vertical ultra-thin SOI (silicon-on-insulator) MOSFET (DELTA, or fully depleted lean-channel transistor) is proposed Since the ultra-thin SOI structure provides high noise immunity, the storage node capacitance can be reduced by more than 50% Therefore, in the proposed DRAM cell a large storage capacitor need not be essential, and this will extend the DRAMs miniaturization to the gigabit levels The cell structure schematic is shown and threshold voltage dependences on channel length of DELTA-, conventional NMOS-, and PMOS-FETs are demonstrated DELTA shows good short channel characteristics compared to conventional NMOS >

High-voltage current saturation in emitter switched thyristors

Abstract: Current saturation at high voltages in MOS-gated emitter switched thyristors (ESTs) is demonstrated. It is shown that by using an improved EST structure containing a dual-channel lateral MOSFET, the thyristor current can be saturated to high voltages through MOS gate control. In experimental devices with 600-V forward blocking capability, it is observed that current densities of 110 A/cm/sup 2/ could be saturated up to 450 V with a gate bias of 3.5 V. Experimental measurements and numerical simulations indicate that, during current saturation, the voltage appears across the junction between the P-base region and the N/sup -/ drift region and not across the lateral MOSFET. >