Showing papers on "MOSFET published in 1999"

Sub 50-nm FinFET: PMOS

Abstract: High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 /spl mu/A//spl mu/m depending on the definition of the width of a double-gate device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.

MOS capacitance measurements for high-leakage thin dielectrics

Abstract: As oxide thickness is reduced below 2.5 nm in MOS devices, both series and shunt parasitic resistances become significant in capacitance-voltage (C-V) measurements. A new technique is presented which allows the frequency-independent device capacitance to be accurately extracted from impedance measurements at two frequencies. This technique is demonstrated for a 1.7 nm SiO/sub 2/ capacitor.

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

Abstract: The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

COOLMOS/sup TM/-a new milestone in high voltage power MOS

Abstract: Recently, a new technology for high voltage power MOSFETs has been introduced: the CoolMOS/sup TM/. Based on the new device concept of charge compensation, the R/sub DS(on)/ area product for e.g. 600 V transistors has been reduced by a factor of 5. The devices show no bipolar current contribution like the well known tail current observed during the turn-off phase of IGBTs. CoolMOS/sup TM/ virtually combines the low switching losses of a MOSFET with the on-state losses of an IGBT. Furthermore, the dependence of R/sub DS(on)/ on the breakdown voltage has been redefined. The more than square-law dependence in the case of standard MOSFET has been broken and a linear voltage dependence achieved. This opens the way to new fields of application even without avalanche operation. System miniaturization, higher switching frequencies, lower circuit parasitics, higher efficiency, and reduced system costs are pointing the way towards future developments. Not only has the new technology achieved breakthrough at reduced R/sub DS(on)/ values, but new benchmarks have also been set for the device capacitances. Due to chip shrinkage and a novel internal structure, the technology shows both a very small input capacitance and a strongly nonlinear output capacitance. The drastically lower gate charge facilitates and reduces the cost of controllability, and the smaller feedback capacitance reduces the dynamic losses. With this new technology, the minimum R/sub DS(on)/ values in all packages are being redefined in the important 600-1000 V categories.

Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices

Abstract: Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage.

NMOS drive current reduction caused by transistor layout and trench isolation induced stress

Abstract: This paper describes a previously unreported phenomenon wherein NMOS transistors of identical gate length exhibit a significant sensitivity to layout. Drive current may be reduced up to 13%, depending on diffusion overlap of gate. Mobility reduction, induced by stress from the trench isolation edge, is the root cause of the performance degradation. PMOS devices are not affected. Simulation results show that stress varies strongly with distance from the trench edge, and with overall diffusion size. Stress is also a major component of narrow-width effects, and explains why Idsat scaling with W differs for NMOS and PMOS devices.

Method for fabricating singe crystal materials over CMOS devices

Abstract: An aspect of the present invention is a method for making a functional active device (photodetector, laser, LED, optical modulator, optical switch, field effect transistor, MOSFET, MODFET, high electron mobility transistor, heterojunction bipolar transistor, resonant tunneling device, Esaki tunneling device etc.) disposed over a complementary metal oxide semiconductor (CMOS) device, having the steps; (a) forming an ultrathin compliant layer direct bonded to an oxide layer over said-CMOS device; (b) growing an epitaxial layer on said ultra-thin compliant layer (c) forming a functional active device in said epitaxial layer grown on said epitaxial layer that is grown on said ultrathin compliant layer; and (c) interconnecting said functional active device and said CMOS device, wherein said CMOS device is configured as either a readout circuit or a control circuit for said photodetector.

High channel mobility in inversion layers of 4H-SiC MOSFETs by utilizing (112~0) face

Abstract: A dramatic improvement of inversion channel mobility in 4H-SiC MOSFETs was successfully achieved by utilizing the (112~0) face: 17 times higher (95.9 cm/sup 2//Vs) than that on the conventional (0001) Si-face (5.59 cm/sup 2//Vs). A low threshold voltage of MOSFETs on the (112~0) face indicates that the (112~0) MOS interface has fewer negative charges than the (0001) MOS interface. Small anisotropy of channel mobility in 4H-SiC MOSFETs (/spl mu//sub (11~00)///spl mu//sub (0001)/=0.85) reflects the small anisotropy in bulk electron mobility.

A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects

Abstract: In this work, we investigate the electrical properties of the Double-Gate MOSFET (DG-MOSFET), which turn out to be very promising for device miniaturization below 0.1 /spl mu/m. A compact model which accounts for charge quantization within the channel, Fermi statistics, and nonstatic effects in the transport model is worked out. The main results of this investigation are: (1) the ideality factor in subthreshold is equal to unity, i.e., the slope of the turn-on characteristic is 60 mV/decade at room temperature; (2) the drain-induced barrier lowering is minimized by the shielding effect of the double gate, which allows us to reduce the channel length below 30 nm; and (3) the device transconductance per unit width is maximized by the combination of the double gate and by a strong velocity overshoot which occurs in response to the sudden variation of the electric field at the source end of the channel, and which can be further strengthened near the drain in view of the short device length. As a result, a sustained electron velocity of nearly twice the saturation velocity is achievable. The above results prove that the potential performance advantages of the double-gate device architecture may be worth the development effort.

The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length

Abstract: We have fabricated and demonstrated a new device called the Vertical Replacement-Gate (VRG) MOSFET This is the first MOSFET ever built that combines (1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and (2) a high-quality gate oxide grown on a single-crystal Si channel In addition to this unique combination, the VRG-MOSFET includes a self-aligned S/D formed by solid source diffusion (SSD) and small parasitic overlap, junction, and S/D capacitances The drive current per /spl mu/m of coded width is significantly higher than that of advanced planar MOSFETs because each rectangular device pillar (with a thickness of minimum lithographic dimension) contains two MOSFETs driving in parallel All of this is achieved using current manufacturing methods, materials, and tools, and competitive devices with 50-nm gate lengths (L/sub G/) have been demonstrated without advanced lithography

Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-/spl mu/m MOSFET's with epitaxial and /spl delta/-doped channels

Abstract: A detailed three-dimensional (3-D) statistical "atomistic" simulation study of fluctuation-resistant sub 0.1-/spl mu/m MOSFET architectures with epitaxial channels and delta doping is presented. The need for enhancing the fluctuation resistance of the sub-0.1-/spl mu/m generation transistors is highlighted by presenting summarized results from atomistic simulations of a wide range of conventional devices with uniformly doped channels. According to our atomistic results, the doping concentration dependence of the random dopant-induced threshold voltage fluctuations in conventional devices is stronger than the analytically predicted fourth-root dependence. As a result of this, the scaling of such devices will be restricted by the "intrinsic" random dopant-induced fluctuations earlier than anticipated. Our atomistic simulations confirm that the introduction of a thin epitaxial layer in the MOSFET's channel can efficiently suppress the random dopant-induced threshold voltage fluctuations in sub-0.1-/spl mu/m devices. For the first time, we observe an "anomalous" reduction in the threshold voltage fluctuations with an increase in the doping concentration behind the epitaxial channel, which we attribute to screening effects. Also, for the first time we study the effect of a delta doping, positioned behind the epitaxial layer, on the intrinsic threshold voltage fluctuations. Above a certain thickness of epitaxial layer, we observe a pronounced anomalous decrease in the threshold voltage fluctuation with the increase of the delta doping. This phenomenon, which is also associated with screening, enhances the importance of the delta doping in the design of properly scaled fluctuation-resistant sub-0.1-/spl mu/m MOSFET's.

Experimental evidence of inelastic tunneling in stress-induced leakage current

Abstract: We propose a new experimental technique to study the transport properties of stress-induced leakage current (SILC). Based on the carrier separation measurement for p-channel MOSFETs, the quantum yield of impact ionization for electrons involved in the SILC process is evaluated directly from the change in the source and gate currents of p-MOSFETs before and after stressing. Since the relationship between the electron energy and the quantum yield is established for direct and FN tunneling currents, the electron energy of electrons involved in the SILC process can be determined from the quantum yield. The results reveal that the measured energy of electrons in the SILC process is lower roughly by 1.5 eV than the energy expected in the elastic tunneling process. Trap-assisted inelastic tunneling model is proposed as a conduction mechanism of SILC accompanied by energy relaxation. It is shown, through the evaluation of the substrate hole current in n-channel MOSFETs, that the contribution of trap-assisted valence electron tunneling, another possible mechanism to explain the energy relaxation, to SILC is small.

Sub-40 nm ptsi schottky source/drain metal-oxide-semiconductor field-effect transistors

Abstract: PtSi source/drain p-type metal–oxide–semiconductor field-effect transistors (MOSFETs) have been fabricated at sub-40 nm channel lengths with 19 A gate oxide. These devices employ gate-induced field emission through the PtSi ∼0.2 eV hole barrier to achieve current drives of ∼350 μA/μm at 1.2 V supply. Delay times estimated by the CV/I metric extend scaling trends of conventional p-MOSFETs to ∼2 ps. Thermal emission limits on/off current ratios to ∼20–50 in undoped devices at 300 K, while ratios of ∼107 are measured at 77 K. Off-state leakage can be reduced by implanting a thin layer of fully depleted donors beneath the active region to augment the Schottky barrier height or by use of ultrathin silicon-on-insulator substrates.

Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs

Abstract: In sub 1 V CMOS designs, especially around 0.5 V CMOS designs, the on-state drain current of MOSFET's shows positive temperature dependence, being different from the negative temperature dependence in the conventional voltage designs. Together with the low threshold voltage less than 0.2 V in the low-voltage CMOS, a possibility of temperature instability increases. The paper describes possible temperature instabilities in the low-voltage regime by using circuit simulation environments incorporating temperature change in time and experiments using MOSFET's and 32-bit adder circuit in quarter micron CMOS technology with low threshold voltage of 0.25 V.

A physical alpha-power law MOSFET model

Abstract: A new compact physics-based alpha-power law MOSFET model is introduced to enable projections of low power circuit performance for future generations of technology by linking the simple mathematical expressions of the original alpha-power law model with their physical origins. The new model, verified by HSPICE simulations and measured data, includes: 1) a subthreshold region of operation for evaluating the on/off current tradeoff that becomes a dominant low power design issue as technology scales, 2) the effects of vertical and lateral high field mobility degradation and velocity saturation, and 3) threshold voltage roll-off. Model projections for MOSFET CV/I indicate a 2X-performance opportunity compared to the National Technology Roadmap for Semiconductors (NTRS) extrapolations for the 250, 180, and 150 nm generations subject to maximum leakage current estimates of the roadmap. NTRS and model calculations converge at the 70 nm technology generation, which exhibits pronounced on/off current interdependence for low power gigascale integration.

MOSCAP and MOSFET characteristics using ZrO/sub 2/ gate dielectric deposited directly on Si

Abstract: MOSCAP and MOSFET characteristics using ZrO/sub 2/ gate dielectric deposited directly on Si have been investigated Thin equivalent oxide thickness (EOT), low leakage, negligible frequency dispersion, interface density less than 10/sup 11/ cm/sup -2/ eV/sup -1/, small hysteresis, excellent reliability characteristics have been demonstrated The ZrO/sub 2/ film has been shown to be amorphous A thin interfacial Zr-silicate layer (k>8) exists and is beneficial in maintaining good interfacial quality This Zr-silicate layer grows after annealing and can be minimized through process optimization Well-behaved p-channel MOS transistor characteristics with a subthreshold swing of 80 mV/decade have also been achieved

A new I-V model for stress-induced leakage current including inelastic tunneling

Abstract: A new I-V model to quantitatively represent stress-induced leakage current (SILC) is presented and compared with the experimental I-V characteristics. The trap-assisted tunneling model is modified so as to include the energy relaxation of tunneling electrons, which has been experimentally verified by applying the carrier separation technique to MOSFETs with the SILC component. The energy relaxation is treated in the new model as the change in the energy level of traps before and after the capture of electrons during two-step tunneling. It is demonstrated that this model successfully represents the experimental I-V characteristics of the SILC component and, particularly, the low apparent barrier height in the Fowler-Nordheim (FN) plot of the SILC component. The calculated low barrier height is attributed to the dominance of direct tunneling mechanism on both tunneling into traps and out of traps. The impact of the energy relaxation during tunneling, used in the present model, on the I-V characteristics is discussed in terms of the trap distribution inside the gate oxide, compared with conventional elastic tunneling model.

Stacked PMOS clamps for high voltage power supply protection

Abstract: Large PMOS FETs with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron CMOS integrated circuits. These clamps divide the supply voltage among several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The high voltage designs are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.

Bootstrapped low-voltage analog switches

Abstract: Novel low-voltage constant-impedance analog switch circuits are proposed. The switch element is a single MOSFET, and constant-impedance operation is obtained using simple circuits to adjust the gate and bulk voltages relative to the switched signal. Low-voltage (1-volt) operation is made feasible by employing a feedback loop. The gate oxide will not be subject to voltages exceeding the supply voltage difference. Realistic switches have been simulated with HSPICE. The simulations show that the switch circuits operate very well, even when the supply voltage approaches the technology's threshold voltage.

Coreless printed circuit board (PCB) transformers for power MOSFET/IGBT gate drive circuits

Abstract: Gate drive circuits for modern power electronic switches, such as MOSFET and insulated gate bipolar transistor (IGBT), often require electrical isolation. This paper describes the modeling and experimental results of some coreless printed circuit board (PCB)-based transformers that can be used for MOSFET and IGBT devices at high-frequency (500 kHz to 2 MHz) operation. PCB-based transformers do not require the manual winding procedure and thus simplify the manufacturing process of transformer-isolated gate drive circuits. With no core loss, coreless transformers are found to have favorable characteristics at high-frequency operations. This project demonstrates an important point that the size of the magnetic core can approach zero and become zero when the frequency is sufficiently high.

Elevated channel mosfet

Abstract: The present invention provides a method of producing a semiconductor device (e.g., a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) with a gate length less than 0.25 microns using standard process techniques arranged in an unstandardized process order. The process flow of the present invention provides for the implantation and thermal processing of the wells and junctions prior to the growth of a channel or the deposition of the gate stack. By implanting and annealing the wells and junctions prior to the formation of the channel and gate, the present invention allows a greater variety of materials to be utilized as the channel and gate materials than are available under process flows currently known; undoped materials may be used to form the channel, metal oxides and similar materials with large dielectrics may be used to form a gate stack, and barrier metals and pure metals (copper, tungsten, etc.) may be used as gate electrodes. The present invention also provides for the selective epitaxial growth of a channel material elevated above the surface of a wafer containing a well and junctions. By providing an elevated channel, higher mobility may be achieved; thereby enabling a higher current flow at a lower voltage through a semiconductor device.

An analytical thermal noise model of deep submicron MOSFET's

Abstract: An analytical model for circuit simulation to describe the channel thermal noise in MOSFET's for all channel length down to deep submicron is presented and verified by measurements. Contrary to the thermal equilibrium assumption, this model includes the influence of the increasing electrical field with downscaling on the channel carrier (electron, hole) equivalent noise temperature. If not taken into account, simulation errors of up to 100% and more in the thermal noise of half micron transistors and below occur.

SON (silicon on nothing)-a new device architecture for the ULSI era

Abstract: A novel device architecture called SON (silicon on nothing) is proposed, allowing extremely thin buried oxides and silicon films to be fabricated and thereby provide better resistance to short channel effects (SCE) and DIBL than any other device architecture. SON devices are shown to present excellent I/sub on//I/sub off/ trade-off, V/sub th/ roll-off suppression down to 15 nm channel length, and to be free from the shortcomings of conventional SOI, such as self-heating, high S/D series resistances, and expensive SOI substrates since SON devices are fabricated on bulk silicon.

Distributed MOSFET structure with enclosed gate for improved transistor size/layout area ratio and uniform ESD triggering

Abstract: A MOSFET structure uses angled poly-gate segments positioned between drain and source diffusion regions such that the entire continuous gate element structure is within the active region in a substrate. The gate-to-source diffusion edges are continuous along the gate body, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. The angled gate segments provide a total gate-to-area ratio greater than that of a multi-finger-gate configuration within an equal size active region. In addition, the gate signal RC delay is sufficient to provide noise suppression of the output voltage when the MOSFET is used as a high current-drive CMOS output buffer.

MOSFET-only switched-capacitor circuits in digital CMOS technology

Abstract: Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology.

Analysis of Short-Channel Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistor on Silicon-on-Insulator Substrate and Demonstration of Sub-50-nm n-type Devices with Metal Gate

Abstract: The Schottky source/drain metal-oxide-semiconductor field-effect transistor (MOSFET) has potential for scaling to the nanometer regime, because low electrode resistances with very shallow extension can be realized using metal source/drain. In this study, very short channel n- and p-type Schottky source/drain MOSFETs with silicon-on-insulator (SOI) structure were analyzed theoretically, and n-type devices were demonstrated experimentally. It was shown theoretically that a drivability of the Schottky source/drain MOSFET comparable to that of conventional MOSFETs can be realized with a low Schottky barrier height. The short-channel effect can be suppressed even with a 15-nm-long channel at tOX = 1 nm and tSOI = 3 nm. The room-temperature operation of sub-50-nm n-type ErSi2 Schottky source/drain MOSFETs on a separation by implanted oxygen (SIMOX) substrate was demonstrated.

On the tunneling component of charge pumping current in ultrathin gate oxide MOSFETs

Abstract: A simple method is described for separating the charge pumping current from the parasitic tunneling component in a charge pumping measurement performed on MOS transistors with ultrathin (<2 nm) gate oxide thickness. The method is presented here for a two-level charge pumping signal and can be used to significantly increase the accuracy of the technique to extract interface trap parameters in tunnel MOS devices.

Method of forming mosfet

Abstract: A method for fabricating a metal oxide silicon field effect transistor (MOSFET) wherein a polysilicon layer is deposited over a gate oxide film serving to insulate the gate of the MOSFET from the substrate of the MOSFET The polysilicon layer serves to prevent the gate oxide film from being etched upon forming a gate electrode using a metal film or metal silicide side walls as a mask Accordingly, it is possible to prevent a short circuit from occurring between the semiconductor substrate and gate electrode of the MOSFET upon forming the gate electrode